IT202000005767A1 - MANUFACTURE OF SEMICONDUCTOR PRODUCTS - Google Patents

Description

DESCRIPTION of the industrial invention entitled:

? Manufacturing of semiconductor products?

TEXT OF THE DESCRIPTION

Technical field

The description ? relating to the manufacture of semiconductor products, such as integrated circuits, IC (? Integrated Circuit?) for short, for example.

One or more? embodiments can be applied to semiconductor products with small-outline package, in short SOP (? Small-Outline Package?), with exposed pad or, more? in general, to semiconductor products that adopt surface-mount technology, SMT (? Surface-Mount Technology?) for short.

Technological background

Integrated circuits may include at least one semiconductor die encased in an insulating package that provides protection from the environment and facilitates electrical interconnection between the die and an underlying substrate, such as a printed circuit board (PCB). .

The integrated circuits may similarly comprise a lead frame. The designation? Lead frame? (or? leadframe?)? currently used (see, for example, the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support for an integrated circuit chip or die, so? as electrical leads to interconnect the integrated circuit in the die or chip to other electrical contacts or components. Basically, a leadframe comprises an array (? Array?) Of electrically conductive formations (leads) that, from a peripheral position, extend inwards in the direction of a die or a semiconductor chip, thus forming? an array of electrically conductive formations from a die pad configured to have at least one semiconductor die or chip attached to it. There? can take place using a die attachment adhesive (a die attachment film or DAF - Die Attach Film, for example).

In a traditional configuration, a packaged semiconductor device can? comprise a metal leadframe, at least one semiconductor die or chip attached to a die pad in the leadframe, bond wires that electrically connect the pads on the IC die to the individual leads of the leadframe, and a material hard insulating encapsulant, such as a plastic resin molding compound, which covers the other components and forms the exterior of the package.

The leadframe can? provide the support structure for the positioning of the semiconductor die, in particular during the assembly of the IC with package, and external contactors (lead or pad).

Power semiconductor devices and IC devices that generate high power can be built with a package with a heat sink configured to dissipate heat and to conductively connect the die pad to a ground plane of a printed circuit board (PCB). The heatsink can? be placed near or against the semiconductor device and can? be encapsulated inside the device package with a heatsink surface left exposed through the package encapsulant, which? discovered by the encapsulant.

Semiconductor packages, such as a smalloutline (for short, SOP), dual in-line, and quad-flat pack (for short, QFP) package indicate semiconductor device families that favor a number of high-power applications.

The use of an integrated heatsink (? Embedded?) In the leadframe package can? consume a large portion of the total internal volume of the package, which is opposed to using this approach for low-volume packages.

Purpose and summary

A purpose of one or more? forms of implementation? to help overcome the drawbacks outlined above.

According to one or more? forms of implementation, this purpose can? be achieved by means of a process having the characteristics set out in the following claims.

One or more? forms of implementation can be related to a leadframe that can? be used in the manufacture of a semiconductor product.

Such a leadframe can? represent in itself? a product adapted to be produced and delivered for the completion (in a different location, for example) of the manufacturing process of semiconductor products.

A leadframe having a die pad portion and a lead array, wherein the leadframe comprises at least one pair of opposite channel-shaped (concave) sides configured to hold the die pad in a downset position relative to the proximal ends. dei) lead pu? be an example of such an article.

One or more? embodiments may relate to a semiconductor product manufacturing process using such a leadframe.

One or more? embodiments can be related to a corresponding semiconductor product.

The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

One or more? embodiments can facilitate providing a larger heatsink / die pad size? large of the size available in traditional semiconductor packaging (? packaging?) solutions.

One or more? embodiments can facilitate the coupling of a semiconductor die pi? large to the die pad in a leadframe for a given package size.

One or more? embodiments can facilitate allowing for better heat dissipation or thermal runoff.

Brief description of the various views of the drawings

One or more? embodiments will now be described, purely by way of non-limiting example, with reference to the attached Figures, in which:

Figures 1 and 2 are perspective views of a semiconductor device,

Figures 3 and 4 are respectively a perspective view and a top view of a leadframe for semiconductor devices,

Figure 5? a cross-sectional view along the line V-V of Figure 4,

Figure 6? a cross-sectional view of a possible alternative implementation of the parts illustrated in Figure 4,

Figures 7 and 8 are respectively a perspective view and a top view of one or more? embodiments of a leadframe according to the present description, Figure 9? a perspective view of one or more? embodiments of a semiconductor product according to the present description,

Figure 10? a cross-sectional view along the line X-X of Figure 9,

Figure 11? an example of a flowchart of acts in a method according to the present description.

Detailed description of examples of embodiments

In the following description, one or more are illustrated. specific details, in order to provide a thorough understanding of examples of embodiments of this disclosure. The embodiments can be obtained without one or more? specific details or with other processes, components, materials, etc. In other cases, known operations, materials or structures are not illustrated or described in detail so as to avoid making certain aspects of the embodiments unclear.

A reference to? An embodiment? within the framework of the present description it intends to indicate that a particular configuration, structure, or feature described with reference to the embodiment? included in at least one embodiment. So, phrases like? In an implementation form? that can be present in one or more? points of the present description do not necessarily refer to the same embodiment.

Furthermore, particular conformations, structures or features can be combined in any suitable way into one or more? forms of implementation.

The references used here are provided simply for convenience and therefore do not define the scope or scope of the embodiments.

As exemplified herein, the drawings are in simplified form and may not be to an accurate scale.

Furthermore, similar parts or elements are indicated with similar numbers / references in all the figures annexed here: for the sake of brevity? a corresponding description will not be? repeated for each figure.

Figure 1? an example of a first view of a small-outline package or SOP 10 device that includes a surface mount integrated circuit package with? gullwing? extending out of two opposite sides of the package 10.

Devices commercially available with companies in the STMicroelectronics group and provided with a PSSO SMD package are examples of such devices.

In such packaged semiconductor devices 10, a portion of a leadframe, e.g. a (back side of a) die pad 14, can remain exposed outside the package 10, e.g., for use as a heatsink.

This ? represented by way of example in Figure 2, that? a view of the device 10 from an observation point approximately opposite to the observation point of Figure 1.

Figures 3 and 4 are examples of a traditional leadframe 20 for a surface mount semiconductor (SMD) product package having an exposed die pad.

Such a leadframe 20 can? be formed from a conductive material (a metal, such as copper, for example) using any traditional process known to those skilled in the art for that purpose.

Such traditional processes can lead to the formation of a continuous strip of theoretically infinite length comprising a plurality of? of 20 individual leadframes adjacent to each other.

For simplicity, the following discussion will do? mainly referring to a single leadframe (as shown by way of example with dashed lines in Figures 3 and 4).

For the rest it will be understood? that one or more? of the working acts discussed below can be performed (possibly simultaneously) on multiple leadframes (still) included in such a strip.

As exemplified here, the leadframe 20 can? comprise a die (mounting) pad 14 having (at least) one die attachment area configured to have (at least) mounted (attached) thereon a chip or semiconductor die 30, the contour of which? indicated in dashed lines in Figures 3 and 4.

For example, the semiconductor chip or die 30 can? be placed on the die pad 14 and secured thereon using glue, solder or tape or any other traditional process known to those skilled in the art for this purpose.

Later, for simplicity, it will be? considered only a chip or a semiconductor die 30.

As exemplified here, the leadframe 20 can? have a (peripheral) portion of substantially quadrangular (rectangular, for example) contour comprising, for example, four sides 200, 201, 202, 203, with at least some of these sides carrying respective arrays of elongated leads 12 extending towards the die pad 14.

For example, two lead arrays 12 extending on two opposite sides 201, 203 of the rectangular boundary portion 200, 201, 202, 203 of the leadframe 20 may be provided.

As exemplified herein, the die pad 14 has a substantially rectangular area having four sides.

As exemplified here, a plurality of of arms or bridges 18 (thin) (referred to as tie bars) couple two sides of the die pad 14 to two opposite sides 200, 202 of the rectangular outer portion of the leadframe.

For example, two pairs for a total of four such tie bars 18 can be provided to support die pad 14. Tie bars 18 can be cut during the process of assembling a semiconductor product, such as 10, where only the die pad 14 (with die 30 mounted on it) and leads 12 can be left in the final device package, optionally with a back side of the die pad left exposed to the outer surface of the package (see Figure 2, for example) and with the final package which includes the residues of the tie bars 18 which are cut, after molding close to the support members 200 and 202.

As exemplified here, giving the leadframe an overall concave shape by placing the die pad 14 at a lower level than the lead 12 can? facilitate the supply of an exposed pad.

In fact, an exposed pad (see Figure 2) can be obtained? pushing down? the die pad 14, i.e. applying a force to deform the tie bars 18, forming an inclined or folded portion therein.

The amount for which the die pad 14? recessed with respect to the leads as a result of the bending of the tie bars 18, i.e. the distance D between the plane of the pad 14 and the plane of the leads 12,? currently referred to as? downset ?.

Figure 5? an example of a section of the die pad 14 and tie bars 18 along the V-V plane of Figure 4.

As best appreciated in Figure 5, the die pad 14 can? have a width WD which, due to the presence of the tie bars 18 with slope, can? be (appreciably) less than a total width L of the leadframe 20.

As shown as an example in Figure 5, for a given downset D, the width WD of the die pad - and so on? the size of the die or chip 30 that can? be mounted on it - can hardly? be increased beyond a certain limit value: this would ultimately lead to an increase in the angle? indicative of a steepness of the slope of the tie bars 18 to a value that? likely to result in damage / breakage of such thin metal parts.

For example, in PSSO-16XL packages as manufactured by STMicroelectronics, the angle? can correspond to a (maximum) slope of 55% given to the tie bars 18.

Figure 6? an example of a cross-sectional view of an alternative configuration of die pad 14 and tie bars 18 aiming to increase the space (substantially, the width WD) available for the surface of the heatsink / die pad, potentially reducing a risk of damage or even breakage of the tie bars.

An alternative leadframe configuration 20 as exemplified in Figure 6 may comprise a die pad 14 having a thickness greater than the thickness of the die pad 14 as exemplified in Figure 5, so that the upper surface of the die pad 14 comes closest to the tie bar. For an (approximately) equal value of the downset D, can? be obtained a (slight) increase in the width WD of the die pad and the size of the die or chip 30 mounted on it, possibly with relaxed constraints on the width WD of the die pad given a package dimension L.

Various points relating to a device may be worth considering as exemplified in Figure 6.

For example, leadframe technology? Dual gauge? can be more? expensive compared to that of a thin, single thickness leadframe. In addition, a die pad and a leadframe pi? thick they can be more? susceptible to cracks in the solder during thermal cycling, possibly leading to degradation of the performance of the semiconductor device when assembled.

Figures 7 and 8 are respectively a perspective view and a top view of one or more? embodiments of a leadframe 40 configured to provide an improved exposed die pad, e.g. great, what can? facilitate the coupling of the leadframe 40 to semiconductor devices more? large, as discussed below.

As indicated, the following discussion will do? reference for simplicity? to a single leadframe as exemplified in Figures 7 and 8, it being understood, however, that one or more? of the working acts discussed below can be carried out (possibly simultaneously) on multiple leadframes 40 (still) included in said strip.

Here, again, a 40 leadframe can? comprise a die (mounting) pad 14 having (at least) one die attachment area configured to have at least one semiconductor chip or die 30 mounted (attached) thereon, the contour of which is? indicated in dashed lines in Figures 7 and 8.

For example, the semiconductor chip or die 30 can? be placed on the die pad 14 and secured thereon using glue, solder or tape or any other conventional means for those skilled in the art for this purpose.

Here, again, will be? considered later for simplicity? just a chip or a semiconductor die 30.

As exemplified in Figures 7 and 8, the leadframe 40 has a substantially quadrangular (rectangular) outer boundary (peripheral) portion (rectangular, for example) comprising, for example, four sides 400, 401, 402, 403, with at least some of these sides that carry respective arrays of elongated leads 12 which extend towards die pad 14.

As shown by way of example in Figures 7 and 8, two lead arrays 12 can be provided which extend on two opposite sides 401, 403 of the outer rectangular portion 400, 401, 402, 403 of the leadframe 40.

For the rest it will appreciate? that such a configuration of leads 12? purely as an example and not? in any way mandatory. One or more? Embodiments may relate to leadframe 40 (and to devices) which have any number of leads 12 projecting from any number of opposite or adjacent portions of leadframe 40.

A leadframe 40 for making a quad flat package or QFP having leads 12 protruding from four opposite sides 400, 401, 402, 403 of an outer portion of the leadframe 40 can? be an example of such an embodiment.

As exemplified in Figures 7 and 8, the die pad 14 has a substantially rectangular area having four sides, with a plurality of sides. of bridge formations 48 (short) located so as to couple two sides of the die pad 14 with two opposite sides 400, 402 of the rectangular outer portion 400, 401, 402, 403 of the leadframe 40.

For example, two pairs for a total of four such bridge formations 48 can be provided to support die pad 14. As further discussed below, formations 48 can be cut at the end of an assembly process with respective remnants remaining in the package. of the final device.

Here, again, the shift of die pad 14 to a higher level? low compared to leads 12 pu? facilitate providing an exposed pad, such as 14 in Figure 2.

As shown by way of example in Figures 7 and 8, such a result can? be obtained? pushing down? the die pad 14 during the manufacture of the leadframe.

As shown by way of example in Figures 7 and 8, in one or more? forms of implementation, can? a corresponding pressure force be applied (as exemplified by the downward arrows in Figure 7), in order to impart (at least) to a pair of opposite sides of the leadframe 40 (sides 400, 402 are considered here as an example) a profile recessed similar to a channel or similar to a well.

As a result of such a profile imparted to them (which may also be referred to as inverted mesa shape, inverted trapezoid, valley, trough, for example), the sides (400, 402, for example) of the leadframe 40 to which? applied pressure will include:

a flat, central (? downset?) portion 404a, coplanar with the die pad 14 and coupled to it by means of the bridge formations 48 (recidable),

two side portions 404b, with sloping sides (or? wings?) extending from the central portion 404a towards the other two sides 401, 403 of the perimeter or boundary portion of the leadframe 40.

As discussed, the pressing tool used to impart the channel-like or well-like recessed profile shown in FIGS. 7 and 8 to the sides 400, 402 can. be any type of traditional tool used to shape a leadframe.

A pressure bar, whose contour? illustrated in dashed lines in P in Figure 7 can be an example of such a tool.

In comparison to the tie bars 18 of Figures 3 and 5, the bridge formations 48 of Figures 7 and 8:

are substantially more? court, and

they are not substantially affected by the pressure P applied to the sides 400, 402 and will maintain a non-deformed shape (e.g., planar).

In one or more? embodiments as exemplified, the sides 400, 402, pressed into a concave shape as discussed above, will form a channel-like portion of the leadframe 40 extending between them, with the die pad 14 extending approximately over a length W of said channel-like portion.

A comparison of Figure 8 (and Figure 7) with figures such as Figures 3 and 4 shows that, in one or more? embodiments as exemplified in Figures 7 and 8, the length (or width) W of the die pad 14 can be appreciably more? long of the homologous WD dimension of traditional devices as illustrated in Figures 3 and 4. There? can facilitate providing further extended heatsink area (or additional pins for grounding).

Figure 9? a perspective view of an example of a semiconductor product 100 which can? be obtained using a leadframe 40 as exemplified herein.

In one or more? embodiments, the semiconductor product 100 can? comprise a mass of an electrically insulating package material 52, 54 (an epoxy molding compound or EMC -? Epoxy Molding Compound ?, for example) printed on a leadframe 40 as shown by way of example in Figures 7 and 8 having (at least) one semiconductor chip or die 30 mounted to die pad 14.

Such a phase or these phases of molding can? be implemented (can be implemented) in any manner known to those skilled in the art for this purpose: by a compression molding or transfer molding technique, for example.

In one or more? embodiments as exemplified in Figure 10, molding the electrically insulating package material 52, 54 can understand to use a dedicated mold (not visible individually in the figures) to print a first portion at the top 52 and a second portion at the bottom 54 of the mass of material for packages that cooperate in hermetically encapsulating the chip or the semiconductor die 30 mounted on the die pad 14 in the concave side of the leadframe 40.

In one or more? embodiments (and as traditional for the rest in the art), the semiconductor die 30 pu? to have on its front or upper surface a plurality? of die pads coupled by a wire bonding pattern 60 to leads 12 in leadframe 40, with a backside 14a of die pad 14 exposed to the outer surface of the package (mass 54) at the bottom of the backside of the product 100. The leads 12 may be provided with plated surfaces, for example silver plated, to facilitate the connection of the bond wires 60.

A comparison of Figure 9 with Figures 7 and 8 illustrates that, in one or more? embodiments, the package material 52, 54 electrically insulating? printed (only) on die pad 14 (having the chip or die 30 mounted on it) and on leads 12.

The lateral portions of the leadframe 40 which comprise the? Downset? or the sides 400, 402 deformed in the shape of a channel can cos? be removed by severing the bridge formations 48 (and other similar formations which are visible in Figures 7 and 8, not explicitly indicated for simplicity).

Those skilled in the art will appreciate the rest that, in one or more? embodiments, the side portions of the leadframe 40 comprising the? downset? or the channel-shaped deformed sides 400, 402 may be left in place to be encapsulated in the electrically insulating package material 52, 54 with the bridge formation 48 left uncut.

In both cases, the leadframe 40 can? possibly be subjected to a cut during a phase of? singulation? (? singulation?) of multiple 100 devices produced on a continuous strip of leadframe in a chain.

As indicated, in one or more? embodiments, the length (or width) W of the die pad 14 (across the side portions of the leadframe as discussed above) can be appreciably more? long of the homologous size of traditional devices, eg. W> WD, which can? facilitate the fact of providing a further extended heatsink area.

This effect can? be further improved by the residues of the bridge formations 48 resulting from the fact that these portions which are severed are left in place at the ends. of the die pad 14 as coplanar protrusions or extensions of the die pad surface. The extremities distals of such residues reaching the outer surface of the package material 54 are visible in Figures 9 and 10.

Advantageously, a solution as described here can? facilitate greater availability? and flexibility? the distribution of the package space with respect to existing solutions. In one or more? embodiments as exemplified in Figure 10, the semiconductor device 30 can occupy almost the entire depth? D of the downset.

In one or more? embodiments, the width W of the die pad 14 can? be nearly as wide as the base of the package, providing potentially improved heat dissipation, especially for power electronics applications.

Figure 11? an example of a diagram of one or more? embodiments of a method of manufacturing or supplying a leadframe 40 and / or a semiconductor product 100 according to the present description.

In one or more? embodiments as shown by way of example in Figure 11 such a method (indicated with 700 as a whole) can? comprehend:

block 702: providing a leadframe 40 (metallic, e.g. copper) comprising a boundary portion 400, 401, 402, 403 (flat); as indicated, this can? having the form of a continuous strip comprising multiple leadframes 40 in a chain;

block 704: apply (by means of a tool P, for example) a pressure P to the leadframe 40 to impart a concave shape on its opposite sides 400, 402 (see Figures 7 and 8)? pushing? then the die pad 14 to a depth? D recessed or with a shift (? Offset?) With respect to the leads 12;

block 706: place (stick) at least one chip or semiconductor die 30 on a front (top) surface of die pad 14, i.e. the surface of die pad 14 which? facing leads 12;

block 708: electrically coupling the semiconductor die 30 to the leads 12, for example by wire bonding 60; And

block 710: printing an encapsulating package material 52, 54 on the leadframe 40 with the semiconductor die 30 thereon, while leaving the surface of the die pad 14a exposed to the outside of the encapsulated volume; as discussed, such a molding step can? be followed by a severing of the leadframe 40 into the bridging portions 48 and / or a severing of the leadframe strip into individual sections to effect the? singulation? of 100 individual products.

In one or more? forms of implementation, such a procedure can? include other steps or acts as traditional in the art (such as shaping the distal ends of the leads 12 into a gull-wing shape as illustrated in Figures 9 and 10).

Will it appreciate? that the sequence of phases or acts represented by way of example in Figure 11 does not? mandatory. For example, the fact of? Pushing? the die pad 14 at a depth? D embedded or with an offset with respect to (at the proximal ends of the) leads 12 (block 704) can? take place after the arrangement (attack) of the chip or of the semiconductor die 30 on the die pad 14 (block 706).

The sequence of phases or acts represented by way of example in Figure 11? however advantageous to the extent that the fact of? pushing? the die pad 14 at a depth? D recessed or with an offset with respect to the leads 12 can? provide an intermediate item, i.e. a product capable of being produced and delivered for the completion of the process with the steps or acts represented by way of example by blocks 706 to 710 (in a different location, for example).

One or more? embodiments can be applied advantageously to surface mount packages, such as those with small outline (SOP) packages which have an area reduced from 30% to 50% and a thickness reduced by 70% compared to flat packages.

Examples of such packages include plastic small outline packages (for short, PSOP -? Plastic Small Outline Package?), Thin small-outline packages (TSOP -? Thin Small-Outline Package?), Restricted small-outline packages ( in short, SSOP -? Shrink Small-Outline Package?) and the thin-shrinked small outline packages (TSSOP -? Thin-Shrink Small Outline Package?), the dual inline configurations cos? as quad flat packs, and can be applied to many other packages.

As exemplified here, a process (for example, 700) can comprehend:

provide (e.g., 702) a leadframe (e.g., 40) comprising a planar laminar body comprising a die pad (e.g., 14) having a semiconductor die mounting area configured to have at least one semiconductor die ( for example, 30) arranged thereon, the leadframe comprising electrically conductive leads (for example, 12) around the die pad so? as a polygonal boundary portion (e.g., 400, 401, 402, 403) having at least one pair of opposite sides (e.g., 400, 402) coupled (e.g., 48) to the die pad (e.g., 14) by bridge-like formations (for example, 48),

imparting (e.g., 704) to said opposite sides in said boundary portion a channel-like shape, wherein the leadframe? imparted a concave shape with the die pad recessed for a certain depth? of downset (e.g., D) with respect to said array of electrically conductive leads in the leadframe.

A procedure as exemplified here can? understand leaving said bridge-like formations free of deformation while? imparted said channel-like shape to said opposite sides in said boundary portion.

A procedure as exemplified here can? comprising providing in said opposite sides in said boundary portion a central region (e.g., 404a) coupled to the die pad by said bridge-like formations and lateral regions (e.g., 404b) extending laterally to said central region, wherein, as a result of imparting said channel-like shape to said opposite sides in said boundary portion, said central region coupled to the die pad? embedded for that certain depth? of downset with respect to the array of electrically conductive leads with said lateral regions inclined with respect to said central region.

A procedure as exemplified here can? comprising disposing (for example, 706) at least one semiconductor die (for example, 30) in said mounting area of the semiconductor die of the die pad.

A procedure as exemplified here can? advantageously comprising arranging (for example, 706) at least one semiconductor die (for example, 30) in said mounting area of the semiconductor die of the die pad after imparting to said opposite sides in said boundary portion a shape similar to a channel, in which the? at least one semiconductor die? received in the concave form of the leadframe.

Alternative embodiments, not explicitly discussed above, can provide on the other hand to arrange the at least one semiconductor die in said mounting area of the semiconductor die of the die pad before imparting a shape to said opposite sides in said boundary portion. similar to a channel.

A procedure as exemplified here can? comprise printing (e.g., 710) a package material (e.g., 52, 54) on said leadframe having the at least one semiconductor die disposed in said die pad semiconductor die mounting area, wherein said print a material per package can? understand leaving a rear side (e.g., 14a) of the die pad opposite the at least one semiconductor die discovered by said package material, as a result of the die pad being embedded for a certain depth? of downset (e.g., D) with respect to (at the proximal ends of) said array of electrically conductive leads in the leadframe.

As exemplified herein, said molding of a material for package can? comprising leaving at least a portion of said bridge-like formations (e.g., 48) uncovered by said package material on said back side of the die pad.

A procedure as exemplified here can? comprising severing said bridge-like formations to separate said die pad from said at least one pair of opposite sides of the leadframe boundary portion having said channel-like shape imparted thereto.

A process as exemplified here lends itself to being implemented as a (complete) sequence of steps or acts as illustrated with reference to Figure 11.

However, such an option is not? mandatory.

One or more? embodiments may actually involve manufacturing (through steps 702 and 704) some sort of? intermediate article? in the form of a leadframe (for example, 40) that can? comprise a laminar body that includes a die pad (e.g., 14) having a semiconductor die mounting area configured to have at least one semiconductor die (e.g., 30) disposed thereon and a polygonal boundary portion ( for example, 400, 401, 402, 403) what? as an array of electrically conductive leads (e.g., 12) around the die pad, the polygonal boundary portion having at least one pair of opposite sides (e.g., 400, 402) in the shape of a channel (see e.g. 404a, 404b) coupled to the die pad by bridge-like formations (for example, 48, coplanar with the die pad), in which the leadframe has a concave shape with the die pad recessed for a certain depth? of downset (e.g., D) with respect to said array of electrically conductive leads in the leadframe (e.g., with respect to the proximal ends of the electrically conductive leads, i.e., the ends of the electrically conductive leads 12 which face the die pad 14 ).

In such a leadframe as exemplified herein, said bridge-like formations (e.g., 48) can be (substantially) coplanar with said die pad.

In such a leadframe as exemplified herein, said opposite sides in said boundary portion may comprise a central region (e.g., 404a) coupled to the die pad (14) by said bridge-like formations and side regions (e.g., 404b) extending laterally to said central region, wherein said central region coupled to the die pad? embedded for that certain depth? of downset with respect to said array of electrically conductive leads with said lateral regions inclined with respect to said central region.

Such a leadframe as exemplified here can? comprising a quadrangular die pad and a quadrangular contour portion around a quadrangular die pad, the quadrangular contour portion comprising a first pair of opposite channel-shaped sides coupled to the die pad by bridge-like formations and a second pair of sides opposite (to such a leadframe as exemplified here, 401, 403) with two sets of electrically conductive leads in said second pair of opposite sides.

As an alternative to the embodiments illustrated in Figure 11, a manufacturing process of a semiconductor product (e.g., 100) as exemplified herein, can understand (possibly as a sequence of steps 706 to 710 carried out at a different time and / or place with respect to the supply of a leadframe as previously discussed? through steps 702, 704, for example):

disposing at least one semiconductor die (e.g., 30) in said die pad semiconductor die mounting area in a leadframe (e.g., 40) as discussed above, wherein the at least one semiconductor die (30)? received in the concave form of the leadframe,

printing a package material (e.g., 52, 54) on said leadframe having the at least one semiconductor die disposed in said die pad semiconductor die mounting area,

severing said bridge-like formations (e.g., 48) in said leadframe to separate said die pad from said at least one pair of opposite sides of the leadframe boundary portion having said channel-like shape imparted thereto.

In a process of manufacturing a semiconductor product as exemplified herein, as a result of said bridge-like formations being severed, the boundary portion of the leadframe having said channel-like shape imparted thereto can be removed. be removed on condition that this portion of the outline can no longer? perform useful functions in the final semiconductor product.

A procedure as exemplified here can? comprising printing (for example, 710) said package material leaving a back side (for example, 14a) of the die pad uncovered opposite to the at least one semiconductor die.

Pu? cos? result as a semiconductor product as exemplified herein, comprising:

a leadframe comprising a laminar body comprising a die pad having a semiconductor die mounting area having at least one semiconductor die disposed thereon thereby as an array of electrically conductive leads around the die pad (14), where the die pad (14)? embedded for a certain depth? of downset (D) with respect to (at the proximal ends of) said electrically conductive lead array in the leadframe, a package material printed on said leadframe having the at least one semiconductor die disposed in said semiconductor die mounting area of the die pad, in which said package material leaves uncovered a rear side (for example, 14a) of the die pad opposite to at least one semiconductor die, said die pad having lateral coplanar protrusions (or extensions, resulting from the cutting of formation 48) , left uncovered by said package material on the rear side (e.g., 14a) of the die pad.

In this regard, it will be appreciated? that, leaving out any other point, the fact of cutting traditional (sloping) tie bars, such as 18 in Figures 3 and 4, will have? inevitably as a result lateral protrusions or extensions of the die pad are similarly sloping or inclined with respect to it (and thus not coplanar with it).

Will you understand? likewise that the various individual implementation options represented by way of example in all the figures accompanying this description are not necessarily intended to be adopted in the same combinations represented by way of example in the figures. One or more? forms of implementation can cos? adopt these options (however not mandatory) individually and / or in different combinations with respect to the combination exemplified in the attached figures.

Without prejudice to the basic principles, can the details and forms of implementation vary, even appreciably, with respect to what? been described, purely by way of example, without leaving the scope of protection. The scope of protection? defined by the appended claims.

Claims (15)

CLAIMS 1. Process (700), comprising: provide (702) a leadframe (40) comprising a planar laminar body which includes a die pad (14) having a semiconductor die mounting area configured to have at least one semiconductor die (30) disposed thereon, the leadframe (40) comprising a polygonal boundary portion (400, 401, 402, 403) so? as an array of electrically conductive leads (12) around the die pad (14), the polygonal boundary portion (400, 401, 402, 403) having at least one pair of opposite sides (400, 402) coupled (48) to the die pad (14) by bridge-like formations (48), imparting (704) to said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403) a channel-like shape (404a, 404b), wherein the leadframe (40)? imparted a concave shape with the die pad (14) recessed for a certain depth? of downset (D) with respect to said array of electrically conductive leads (12) in the leadframe (40). A method (700) according to claim 1, comprising leaving said bridge-like formations (48) free from deformation while? imparted (704) said channel-like shape (404a, 404b) to said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403). Method (700) according to claim 1 or claim 2, comprising providing in said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403) a coupled central region (404a) (48 ) to the die pad (14) by said bridge-like formations (48) and lateral regions (404b) extending laterally to said central region (404a), wherein, as a result of imparting (704) said similar shape to a channel (404a, 404b) to said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403), said central region (404a) coupled (48) to the die pad (14)? embedded for that certain depth? of downset (D) with respect to said array of electrically conductive leads (12) with said lateral regions (404b) inclined with respect to said central region (404a). Method (700) according to any one of the preceding claims, comprising arranging (706) at least one semiconductor die (30) in said mounting area of the semiconductor die of the die pad (14). Method (700) according to claim 4, comprising placing (706) at least one semiconductor die (30) in said mounting area of the semiconductor die of the die pad (14) after imparting (704) to said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403) a channel-like shape (404a, 404b), wherein the at least one semiconductor die (30)? received in the concave form of the leadframe (40). Method (700) according to claim 4 or claim 5, comprising printing (710) a package material (52, 54) on said leadframe (40) having the at least one semiconductor die (30) disposed in said mounting area of the semiconductor die of the die pad (14), in which said printing (710) a material for package (52, 54) comprises leaving a rear side (14a) of the die pad (14) opposite to the at least one semiconductor die (30) discovered from said package material (52, 54) as a result of the fact that the die pad (14)? embedded for a certain depth? of downset (D) with respect to said array of electrically conductive leads (12) in the leadframe (40). A method (700) according to claim 6, wherein said molding (710) a package material (52, 54) comprises leaving at least a portion of said bridge-like formations (48) uncovered from said package material ( 52, 54) on said rear side (14a) of the die pad (14). Method (700) according to any one of the preceding claims, comprising severing said bridge-like formations (48) to separate said die pad (14) from said at least one pair of opposite sides (400, 402) of the boundary portion (400, 401, 402, 403) of the leadframe (40) having said channel-like shape (404a, 404b) imparted thereto. 9. Leadframe (40) for semiconductor products, the leadframe (40) comprising a laminar body comprising a die pad (14) having a semiconductor die mounting area configured to have at least one semiconductor die (30) arranged on it and a portion of the polygonal boundary (400, 401, 402, 403) cos? as an array of electrically conductive leads (12) around the die pad (14), the polygonal boundary portion (400, 401, 402, 403) having at least one pair of opposite sides (400, 402) in the shape of a channel (404a , 404b) coupled to the die pad (14) by means of formations similar to a bridge (48), in which the leadframe (40) has a concave shape with the die pad (14) recessed for a certain depth? of downset (D) with respect to said array of electrically conductive leads (12) in the leadframe (40). Leadframe (40) according to claim 9, wherein said bridge-like formations (48) are substantially coplanar with said die pad (14). Leadframe (40) according to claim 9 or claim 10, wherein said opposite sides (400, 402) in said boundary portion (400, 401, 402, 403) comprise a central region (404a) coupled to the die pad (14) by said bridge-like formations (48) and lateral regions (404b) extending laterally to said central region (404a), wherein said central region (404a) coupled to die pad (14)? embedded for that certain depth? of downset (D) with respect to said array of electrically conductive leads (12) with said lateral regions (404b) inclined with respect to said central region (404a). Leadframe (40) according to any one of claims 9 to 11, comprising a quadrangular die pad (14) and a quadrangular contour portion (400, 401, 402, 403) around the quadrangular die pad (14), the portion quadrangular contour (400, 401, 402, 403) comprising a first pair of opposite sides (400, 402) in the shape of a channel (404a, 404b) coupled (48) to the die pad (14) by means of bridge-like formations ( 48) and a second pair of opposite sides (401, 403) with two sets of electrically conductive leads (12) in said second pair of opposite sides (401, 403). 13. Process of manufacturing a semiconductor product (100), comprising: arrange at least one semiconductor die (30) in said semiconductor die mounting area of the die pad (14) in a leadframe (40) according to any one of claims 9 to 12, wherein the at least one semiconductor die ( 30)? received in the concave form of the leadframe (40), printing a package material (52, 54) on said leadframe (40) having the at least one semiconductor die (30) disposed in said semiconductor die mounting area of the die pad (14), severing said bridge-like formations (48) in said leadframe (40) to separate said die pad (14) from said at least one pair of opposite sides (400, 402) of the boundary portion (400, 401, 402, 403) the leadframe (40) having said channel-like shape (404a, 404b) imparted thereto. A method according to claim 13, comprising printing (710) said package material (52, 54) leaving uncovered a rear side (14a) of the die pad (14) opposite to the at least one semiconductor die (30). 15. Semiconductor product, comprising: a leadframe (40) comprising a laminar body comprising a die pad (14) having a semiconductor die mounting area having at least one semiconductor die (30) disposed thereon thereby as an array of electrically conductive leads (12) around the die pad (14), where the die pad (14)? embedded for a certain depth? of downset (D) with respect to said array of electrically conductive leads (12) in the leadframe (40), a package material (52, 54) printed on said leadframe (40) having the at least one semiconductor die (30) disposed in said semiconductor die mounting area of the die pad (14), wherein said package material (52, 54) leaves uncovered a rear side (14a) of the die pad (14) opposite to at least one semiconductor die (30), said die pad having coplanar lateral protrusions (48) left uncovered by said package material (52 , 54) on the back side (14a) of the die pad (14).