IT1394959B1 - Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato - Google Patents

Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato

Info

Publication number
IT1394959B1
IT1394959B1 ITVA2009A000054A ITVA20090054A IT1394959B1 IT 1394959 B1 IT1394959 B1 IT 1394959B1 IT VA2009A000054 A ITVA2009A000054 A IT VA2009A000054A IT VA20090054 A ITVA20090054 A IT VA20090054A IT 1394959 B1 IT1394959 B1 IT 1394959B1
Authority
IT
Italy
Prior art keywords
metal
manufacture
contact
depositor
vertical interconnections
Prior art date
Application number
ITVA2009A000054A
Other languages
English (en)
Inventor
Nunzia Malagnino
Luigi Giuseppe Occhipinti
Rossana Scaldaferri
Maria Viviana Volpe
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITVA2009A000054A priority Critical patent/IT1394959B1/it
Priority to US12/844,347 priority patent/US8062976B2/en
Publication of ITVA20090054A1 publication Critical patent/ITVA20090054A1/it
Application granted granted Critical
Publication of IT1394959B1 publication Critical patent/IT1394959B1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H10K71/611—Forming conductive regions or layers, e.g. electrodes using printing deposition, e.g. ink jet printing

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
ITVA2009A000054A 2009-07-28 2009-07-28 Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato IT1394959B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITVA2009A000054A IT1394959B1 (it) 2009-07-28 2009-07-28 Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato
US12/844,347 US8062976B2 (en) 2009-07-28 2010-07-27 Low cost method of fabrication of vertical interconnections combined to metal top electrodes

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITVA2009A000054A IT1394959B1 (it) 2009-07-28 2009-07-28 Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato

Publications (2)

Publication Number Publication Date
ITVA20090054A1 ITVA20090054A1 (it) 2011-01-29
IT1394959B1 true IT1394959B1 (it) 2012-07-27

Family

ID=41722936

Family Applications (1)

Application Number Title Priority Date Filing Date
ITVA2009A000054A IT1394959B1 (it) 2009-07-28 2009-07-28 Fabbricazione di interconnessioni verticali in stack di integrazione, contattate da strato metallico superiore depositato

Country Status (2)

Country Link
US (1) US8062976B2 (it)
IT (1) IT1394959B1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2432721B (en) * 2005-11-25 2011-06-22 Seiko Epson Corp Electrochemical cell structure and method of fabrication
GB2432723B (en) * 2005-11-25 2010-12-08 Seiko Epson Corp Electrochemical cell and method of manufacture
GB2432722A (en) * 2005-11-25 2007-05-30 Seiko Epson Corp Electrochemical cell and method of manufacture
WO2012158842A1 (en) * 2011-05-18 2012-11-22 Nuventix, Inc. Power delivery to diaphragms
ITVI20110169A1 (it) 2011-06-27 2012-12-28 St Microelectronics Srl Dispositivo elettronico flessibile e metodo per la fabbricazione dello stesso
JP2015523760A (ja) * 2012-05-01 2015-08-13 ナノトン， インコーポレイテッド 無線周波数（ｒｆ）伝導媒体
US9296013B2 (en) * 2013-02-28 2016-03-29 Eastman Kodak Company Making multi-layer micro-wire structure
US9269723B2 (en) * 2014-04-09 2016-02-23 Eastman Kodak Company Printing electronic circuitry logic
KR102515807B1 (ko) * 2016-01-11 2023-03-31 삼성디스플레이 주식회사 표시 장치 및 이의 제조 방법
DE112021002882T5 (de) 2020-05-20 2023-05-17 Board Of Trustees Of Michigan State University Brennkraftmaschine mit mehreren kraftstoffeinspritzungen ausserhalb einer vorkammer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254872A (en) * 1989-03-14 1993-10-19 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
EP1243035B1 (en) * 1999-12-21 2016-03-02 Flexenable Limited Forming interconnects
GB0024294D0 (en) * 2000-10-04 2000-11-15 Univ Cambridge Tech Solid state embossing of polymer devices
JP2005032769A (ja) * 2003-07-07 2005-02-03 Seiko Epson Corp 多層配線の形成方法、配線基板の製造方法、デバイスの製造方法
TWI228389B (en) * 2003-12-26 2005-02-21 Ind Tech Res Inst Method for forming conductive plugs
JP2005209696A (ja) * 2004-01-20 2005-08-04 Seiko Epson Corp 半導体装置の製造方法
EP1831937B1 (en) * 2004-12-06 2019-11-27 Flexenable Limited Method for forming and metallizing vias through a multilayer substrate

Also Published As

Publication number Publication date
US20110027986A1 (en) 2011-02-03
ITVA20090054A1 (it) 2011-01-29
US8062976B2 (en) 2011-11-22

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