IT1296427B1 - Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di - Google Patents

Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di

Info

Publication number
IT1296427B1
IT1296427B1 IT97MI002529A ITMI972529A IT1296427B1 IT 1296427 B1 IT1296427 B1 IT 1296427B1 IT 97MI002529 A IT97MI002529 A IT 97MI002529A IT MI972529 A ITMI972529 A IT MI972529A IT 1296427 B1 IT1296427 B1 IT 1296427B1
Authority
IT
Italy
Prior art keywords
voltage
bus
levels higher
input signals
input circuit
Prior art date
Application number
IT97MI002529A
Other languages
English (en)
Inventor
Giorgio Catanzaro
Fabrizio Romano
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT97MI002529A priority Critical patent/IT1296427B1/it
Priority to US09/191,624 priority patent/US6184715B1/en
Publication of ITMI972529A1 publication Critical patent/ITMI972529A1/it
Application granted granted Critical
Publication of IT1296427B1 publication Critical patent/IT1296427B1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
IT97MI002529A 1997-11-14 1997-11-14 Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di IT1296427B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT97MI002529A IT1296427B1 (it) 1997-11-14 1997-11-14 Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di
US09/191,624 US6184715B1 (en) 1997-11-14 1998-11-13 Bus-hold input circuit adapted for receiving input signals with voltage levels higher than the voltage supply thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT97MI002529A IT1296427B1 (it) 1997-11-14 1997-11-14 Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di

Publications (2)

Publication Number Publication Date
ITMI972529A1 ITMI972529A1 (it) 1999-05-14
IT1296427B1 true IT1296427B1 (it) 1999-06-25

Family

ID=11378200

Family Applications (1)

Application Number Title Priority Date Filing Date
IT97MI002529A IT1296427B1 (it) 1997-11-14 1997-11-14 Circuito di ingresso bus-hold in grado di ricevere segnali di ingresso con livelli di tensione superiori alla propria tensione di

Country Status (2)

Country Link
US (1) US6184715B1 (it)
IT (1) IT1296427B1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6774675B1 (en) * 2003-06-24 2004-08-10 Fairchild Semiconductor Corporation Bus hold circuit with power-down and over-voltage tolerance
JP3948621B2 (ja) * 2003-06-30 2007-07-25 株式会社山武 インターフェース回路
US7504865B2 (en) * 2004-03-09 2009-03-17 Panasonic Corporation Frequency sensor and semiconductor device
US7064593B2 (en) * 2004-09-20 2006-06-20 Texas Instruments Incorporated Bus-hold circuit
EP2005591A1 (en) * 2006-03-30 2008-12-24 Tte Technology, Inc. Communication circuit with selectable signal voltage

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700086A (en) * 1985-04-23 1987-10-13 International Business Machines Corporation Consistent precharge circuit for cascode voltage switch logic
US4800303A (en) * 1987-05-19 1989-01-24 Gazelle Microcircuits, Inc. TTL compatible output buffer
US5027008A (en) * 1990-02-15 1991-06-25 Advanced Micro Devices, Inc. CMOS clamp circuits
US5486779A (en) * 1994-12-29 1996-01-23 Cyrix Corporation Sense amplifier
KR0146532B1 (ko) * 1995-05-25 1998-11-02 김광호 반도체 메모리 장치의 다이나믹 레벨 컨버터
US5646557A (en) * 1995-07-31 1997-07-08 International Business Machines Corporation Data processing system and method for improving performance of domino-type logic using multiphase clocks
US5933021A (en) * 1996-06-18 1999-08-03 Sun Microsystems, Inc Noise suppression method and circuits for sensitive circuits
US5789937A (en) * 1996-08-14 1998-08-04 International Business Machines Corporation Impedence self-adjusting driver circuit
US5914844A (en) * 1997-10-14 1999-06-22 Cypress Semiconductor Corp. Overvoltage-tolerant input-output buffers having a switch configured to isolate a pull up transistor from a voltage supply
US6049242A (en) * 1997-10-14 2000-04-11 Cypress Semiconductor Corp. Voltage reference source for an overvoltage-tolerant bus interface

Also Published As

Publication number Publication date
ITMI972529A1 (it) 1999-05-14
US6184715B1 (en) 2001-02-06

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0001 Granted