IT1262404B - Procedimento ed apparecchio per il trasferimento di dati con funzionamento a doppia frequenza. - Google Patents

Procedimento ed apparecchio per il trasferimento di dati con funzionamento a doppia frequenza.

Info

Publication number
IT1262404B
IT1262404B ITRM930583A ITRM930583A IT1262404B IT 1262404 B IT1262404 B IT 1262404B IT RM930583 A ITRM930583 A IT RM930583A IT RM930583 A ITRM930583 A IT RM930583A IT 1262404 B IT1262404 B IT 1262404B
Authority
IT
Italy
Prior art keywords
data transfer
transfer system
control module
state
data
Prior art date
Application number
ITRM930583A
Other languages
English (en)
Inventor
Jeffrey W Tripp
Jae H Shim
Bruce M Paggeot
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of ITRM930583A0 publication Critical patent/ITRM930583A0/it
Publication of ITRM930583A1 publication Critical patent/ITRM930583A1/it
Application granted granted Critical
Publication of IT1262404B publication Critical patent/IT1262404B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/044—Speed or phase control by synchronisation signals using special codes as synchronising signal using a single bit, e.g. start stop bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Information Transfer Systems (AREA)
  • Transceivers (AREA)
  • Transmitters (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)

Abstract

La presente descrizione comprende una discussione di un sistema di trasferimento di dati. Il sistema di trasferimento di dati è responsabile del trasferimento di dati verso e da un ricetrasmettitore radio (107) e da tutti i corrispondenti dispositivi periferici (111, 113) contenuti nel radiotelefono (103). Il sistema di trasferimento di dati comprende un bus di dati (109), un modulo di controllo principale nel ricetrasmettitore (107) ed un modulo di controllo periferico in ciascuno dei dispositivi periferici. Il sistema di trasferimento di dati presenta uno stato di inizializzazione ed uno stato operativo. Durante lo stato di inizializzazione, il bus di dati (109) opera ad una frequenza inferiore in confronto con lo stato operativo. La più bassa velocità aumenta il tempo concesso per l'assegnazione degli indirizzi univoci per ciascuno dei moduli di controllo periferici. Dopo la rivelazione del completamento dello stato di inizializzazione, il modulo di controllo principale conduce la commutazione allo stato operativo.
ITRM930583A 1992-09-04 1993-09-01 Procedimento ed apparecchio per il trasferimento di dati con funzionamento a doppia frequenza. IT1262404B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/940,551 US5396654A (en) 1992-09-04 1992-09-04 Data transfer method and apparatus having dual frequency operation

Publications (3)

Publication Number Publication Date
ITRM930583A0 ITRM930583A0 (it) 1993-09-01
ITRM930583A1 ITRM930583A1 (it) 1995-03-01
IT1262404B true IT1262404B (it) 1996-06-19

Family

ID=25475034

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM930583A IT1262404B (it) 1992-09-04 1993-09-01 Procedimento ed apparecchio per il trasferimento di dati con funzionamento a doppia frequenza.

Country Status (18)

Country Link
US (1) US5396654A (it)
JP (1) JP3216135B2 (it)
KR (2) KR940703104A (it)
CN (1) CN1043107C (it)
AU (1) AU660850B2 (it)
BR (1) BR9305630A (it)
CA (1) CA2118719C (it)
DE (2) DE4394368T1 (it)
FR (1) FR2695495B1 (it)
GB (1) GB2275399B (it)
HU (1) HU9401301D0 (it)
IL (1) IL106570A (it)
IT (1) IT1262404B (it)
MX (1) MX9305412A (it)
SE (1) SE515886C2 (it)
SG (1) SG64298A1 (it)
TR (1) TR27600A (it)
WO (1) WO1994006214A1 (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1182810A (fr) * 1957-09-16 1959-06-30 Snecma Perfectionnements aux tuyères d'éjection à section réglable
JP3252487B2 (ja) * 1992-10-23 2002-02-04 松下電器産業株式会社 セルラ無線電話システム
US5754961A (en) 1994-06-20 1998-05-19 Kabushiki Kaisha Toshiba Radio communication system including SDL having transmission rate of relatively high speed
US5818826A (en) * 1996-06-17 1998-10-06 International Business Machines Corporation Media access control protocols in a wireless communication network supporting multiple transmission rates
US6167259A (en) * 1998-06-19 2000-12-26 Ericsson Inc. System and method of quantifying the degree of balance on forward link and reverse link channels
GB2363218A (en) * 2000-06-07 2001-12-12 Ubinetics Ltd A method of accessing application data for a peripheral device
DE10055938A1 (de) * 2000-11-10 2002-05-23 Hirschmann Electronics Gmbh Datenübertragung
KR100602204B1 (ko) * 2004-07-28 2006-07-19 삼성전자주식회사 메인 제어부와 부 제어부로 구성된 제어 시스템 및 버스연결 방법

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809297A (en) * 1984-10-04 1989-02-28 Williams Electronics Ltd. Interface device
DE3636511A1 (de) * 1986-10-27 1988-04-28 Weiss Dieter Einrichtung zum adressieren von baugruppen
US4905282A (en) * 1988-10-19 1990-02-27 Hayes Microcomputer Products, Inc. Feature negotiation protocol and dynamically adjustable retraining sequence for a high speed half duplex modem
US4972432A (en) * 1989-01-27 1990-11-20 Motorola, Inc. Multiplexed synchronous/asynchronous data bus
US5214774A (en) * 1990-07-30 1993-05-25 Motorola, Inc. Segmented memory transfer and message priority on synchronous/asynchronous data bus
US5204669A (en) * 1990-08-30 1993-04-20 Datacard Corporation Automatic station identification where function modules automatically initialize
BR9205316A (pt) * 1991-03-04 1994-08-02 Motorola Inc Sistema de comunicações de dados, radiotelefone e aparelho de interface de condutor
KR0131142B1 (ko) * 1991-07-18 1998-04-21 안토니 제이. 살리 2세 무선전화기의 주변 장치에 대해 우선권 부여 데이타 전달 방법 및 장치
WO1993007569A1 (en) * 1991-10-04 1993-04-15 Wellfleet Communications, Inc. Method and apparatus for concurrent packet bus

Also Published As

Publication number Publication date
AU660850B2 (en) 1995-07-06
KR940703104A (ko) 1994-09-17
HU9401301D0 (en) 1994-08-29
SE515886C2 (sv) 2001-10-22
CA2118719A1 (en) 1994-03-17
BR9305630A (pt) 1995-07-25
JPH07500960A (ja) 1995-01-26
IL106570A0 (en) 1993-12-08
JP3216135B2 (ja) 2001-10-09
GB2275399A (en) 1994-08-24
WO1994006214A1 (en) 1994-03-17
DE4394368T1 (de) 1994-10-20
CA2118719C (en) 1998-12-22
US5396654A (en) 1995-03-07
IL106570A (en) 1998-01-04
SE9401517L (sv) 1994-06-22
CN1086362A (zh) 1994-05-04
AU4790793A (en) 1994-03-29
CN1043107C (zh) 1999-04-21
MX9305412A (es) 1995-01-31
FR2695495A1 (fr) 1994-03-11
FR2695495B1 (fr) 1995-03-31
DE4394368C2 (de) 2003-03-06
SE9401517D0 (sv) 1994-05-03
KR970006878B1 (ko) 1997-04-30
TR27600A (tr) 1995-06-13
GB2275399B (en) 1996-10-02
GB9406368D0 (en) 1994-06-08
ITRM930583A1 (it) 1995-03-01
SG64298A1 (en) 1999-04-27
ITRM930583A0 (it) 1993-09-01

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960722