IT1244912B - Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento. - Google Patents

Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento.

Info

Publication number
IT1244912B
IT1244912B ITRM910077A ITRM910077A IT1244912B IT 1244912 B IT1244912 B IT 1244912B IT RM910077 A ITRM910077 A IT RM910077A IT RM910077 A ITRM910077 A IT RM910077A IT 1244912 B IT1244912 B IT 1244912B
Authority
IT
Italy
Prior art keywords
learning
neuronic network
neuronic
network
inserable
Prior art date
Application number
ITRM910077A
Other languages
English (en)
Inventor
Giuliano Imondi
Giulio Marotta
Giulio Porrovecchio
Giuseppe Savarese
Original Assignee
Texas Instruments Italia Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Italia Spa filed Critical Texas Instruments Italia Spa
Priority to ITRM910077A priority Critical patent/IT1244912B/it
Publication of ITRM910077A0 publication Critical patent/ITRM910077A0/it
Priority to US07/828,062 priority patent/US5274743A/en
Priority to JP4040521A priority patent/JPH0591901A/ja
Publication of ITRM910077A1 publication Critical patent/ITRM910077A1/it
Application granted granted Critical
Publication of IT1244912B publication Critical patent/IT1244912B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Oggetto dell'invenzione è un sistema di apprendimento per rete neuronica fisicamente inseribile nel processo di apprendimento, che comprende un organo rivelatore per presentare a detta rete neuronica il complesso delle informazioni di base che detta rete neuronica deve apprendere per fornire una risposta desiderata; un microprocessore atto ad eseguire in maniera iterativa un algoritmo di apprendimento basato su un confronto tra detto stesso complesso di informazioni di base presentato alla rete neuronica, la risposta che la rete neuronica fornisce e la risposta che si desidera ottenere dalla rete neuronica.Vedere Figura 1.
ITRM910077A 1991-01-31 1991-01-31 Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento. IT1244912B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITRM910077A IT1244912B (it) 1991-01-31 1991-01-31 Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento.
US07/828,062 US5274743A (en) 1991-01-31 1992-01-30 Learning system for a neural net of a suitable architecture, physically insertable in the learning process
JP4040521A JPH0591901A (ja) 1991-01-31 1992-01-31 サツカーシユーズに特に適用可能な被覆要素

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITRM910077A IT1244912B (it) 1991-01-31 1991-01-31 Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento.

Publications (3)

Publication Number Publication Date
ITRM910077A0 ITRM910077A0 (it) 1991-01-31
ITRM910077A1 ITRM910077A1 (it) 1992-07-31
IT1244912B true IT1244912B (it) 1994-09-13

Family

ID=11399821

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM910077A IT1244912B (it) 1991-01-31 1991-01-31 Sistema di apprendimento per rete neuronica di opportuna architettura fisicamente inseribile nel processo di apprendimento.

Country Status (3)

Country Link
US (1) US5274743A (it)
JP (1) JPH0591901A (it)
IT (1) IT1244912B (it)

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Publication number Priority date Publication date Assignee Title
US5479572A (en) * 1992-06-17 1995-12-26 Siemens Corporate Research, Inc. Artificial neural network (ANN) classifier apparatus for selecting related computer routines and methods
EP0612035B1 (en) * 1993-02-19 2002-01-30 International Business Machines Corporation Neural net for the comparison of image pattern features
US5583964A (en) * 1994-05-02 1996-12-10 Motorola, Inc. Computer utilizing neural network and method of using same
US5666468A (en) * 1994-12-02 1997-09-09 Grumman Corporation Neural network binary code recognizer
JP4886922B2 (ja) * 2009-09-28 2012-02-29 美津濃株式会社 フットボールシューズ用アッパー構造
US8676734B2 (en) * 2010-07-07 2014-03-18 Qualcomm, Incorporated Methods and systems for replaceable synaptic weight storage in neuro-processors
US10387298B2 (en) 2017-04-04 2019-08-20 Hailo Technologies Ltd Artificial neural network incorporating emphasis and focus techniques
US11544545B2 (en) 2017-04-04 2023-01-03 Hailo Technologies Ltd. Structured activation based sparsity in an artificial neural network
US11238334B2 (en) 2017-04-04 2022-02-01 Hailo Technologies Ltd. System and method of input alignment for efficient vector operations in an artificial neural network
US11615297B2 (en) 2017-04-04 2023-03-28 Hailo Technologies Ltd. Structured weight based sparsity in an artificial neural network compiler
US11551028B2 (en) 2017-04-04 2023-01-10 Hailo Technologies Ltd. Structured weight based sparsity in an artificial neural network
US11221929B1 (en) 2020-09-29 2022-01-11 Hailo Technologies Ltd. Data stream fault detection mechanism in an artificial neural network processor
US11874900B2 (en) 2020-09-29 2024-01-16 Hailo Technologies Ltd. Cluster interlayer safety mechanism in an artificial neural network processor
US11263077B1 (en) 2020-09-29 2022-03-01 Hailo Technologies Ltd. Neural network intermediate results safety mechanism in an artificial neural network processor
US11237894B1 (en) 2020-09-29 2022-02-01 Hailo Technologies Ltd. Layer control unit instruction addressing safety mechanism in an artificial neural network processor
US11811421B2 (en) 2020-09-29 2023-11-07 Hailo Technologies Ltd. Weights safety mechanism in an artificial neural network processor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5155802A (en) * 1987-12-03 1992-10-13 Trustees Of The Univ. Of Penna. General purpose neural computer
US4866645A (en) * 1987-12-23 1989-09-12 North American Philips Corporation Neural network with dynamic refresh capability
JP2764277B2 (ja) * 1988-09-07 1998-06-11 株式会社日立製作所 音声認識装置
JPH02287670A (ja) * 1989-04-27 1990-11-27 Mitsubishi Electric Corp 半導体神経回路網
US5146542A (en) * 1989-06-15 1992-09-08 General Electric Company Neural net using capacitive structures connecting output lines and differentially driven input line pairs
US5039871A (en) * 1990-05-21 1991-08-13 General Electric Company Capacitive structures for weighted summation as used in neural nets
US5140531A (en) * 1990-08-01 1992-08-18 General Electric Company Analog neural nets supplied digital synapse signals on a bit-slice basis
US5150450A (en) * 1990-10-01 1992-09-22 The United States Of America As Represented By The Secretary Of The Navy Method and circuits for neuron perturbation in artificial neural network memory modification

Also Published As

Publication number Publication date
ITRM910077A1 (it) 1992-07-31
ITRM910077A0 (it) 1991-01-31
US5274743A (en) 1993-12-28
JPH0591901A (ja) 1993-04-16

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