IT1165434B - Processo per formare collegamenti in sistemi di metallurgia a piu' livelli - Google Patents
Processo per formare collegamenti in sistemi di metallurgia a piu' livelliInfo
- Publication number
- IT1165434B IT1165434B IT28131/79A IT2813179A IT1165434B IT 1165434 B IT1165434 B IT 1165434B IT 28131/79 A IT28131/79 A IT 28131/79A IT 2813179 A IT2813179 A IT 2813179A IT 1165434 B IT1165434 B IT 1165434B
- Authority
- IT
- Italy
- Prior art keywords
- forming connections
- level metallurgy
- metallurgy systems
- systems
- level
- Prior art date
Links
- 238000005272 metallurgy Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US97457278A | 1978-12-29 | 1978-12-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
IT7928131A0 IT7928131A0 (it) | 1979-12-18 |
IT1165434B true IT1165434B (it) | 1987-04-22 |
Family
ID=25522196
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT28131/79A IT1165434B (it) | 1978-12-29 | 1979-12-18 | Processo per formare collegamenti in sistemi di metallurgia a piu' livelli |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0013728B1 (it) |
JP (1) | JPS5591843A (it) |
CA (1) | CA1120611A (it) |
DE (1) | DE2966841D1 (it) |
IT (1) | IT1165434B (it) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6044829B2 (ja) * | 1982-03-18 | 1985-10-05 | 富士通株式会社 | 半導体装置の製造方法 |
DE3232837A1 (de) * | 1982-09-03 | 1984-03-08 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen einer 2-ebenen-metallisierung fuer halbleiterbauelemente, insbesondere fuer leistungshalbleiterbauelemente wie thyristoren |
GB8316476D0 (en) * | 1983-06-16 | 1983-07-20 | Plessey Co Plc | Producing layered structure |
DE3331759A1 (de) * | 1983-09-02 | 1985-03-21 | Siemens AG, 1000 Berlin und 8000 München | Integrierte halbleiterschaltung mit einer aus aluminium oder aus einer aluminium-legierung bestehenden mehrlagenverdrahtung und verfahren zu ihrer herstellung. |
US4672420A (en) * | 1984-03-26 | 1987-06-09 | Advanced Micro Devices, Inc. | Integrated circuit structure having conductive, protective layer for multilayer metallization to permit reworking |
US4541168A (en) * | 1984-10-29 | 1985-09-17 | International Business Machines Corporation | Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes |
JPS61161740A (ja) * | 1985-01-07 | 1986-07-22 | モトロ−ラ・インコ−ポレ−テツド | 多層金属化集積回路およびその製造方法 |
EP0490877A3 (en) * | 1985-01-22 | 1992-08-26 | Fairchild Semiconductor Corporation | Interconnection for an integrated circuit |
JP3708732B2 (ja) * | 1998-12-25 | 2005-10-19 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN113380144B (zh) * | 2021-06-07 | 2022-11-25 | 武汉天马微电子有限公司 | 一种显示面板及显示装置 |
CN113766758B (zh) * | 2021-09-30 | 2023-04-11 | 深圳市电通材料技术有限公司 | 一种立体线路的生成方法和线路板 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4851595A (it) * | 1971-10-29 | 1973-07-19 | ||
US4029562A (en) * | 1976-04-29 | 1977-06-14 | Ibm Corporation | Forming feedthrough connections for multi-level interconnections metallurgy systems |
-
1979
- 1979-10-15 CA CA000337633A patent/CA1120611A/en not_active Expired
- 1979-10-19 JP JP13431379A patent/JPS5591843A/ja active Pending
- 1979-12-10 DE DE7979105056T patent/DE2966841D1/de not_active Expired
- 1979-12-10 EP EP79105056A patent/EP0013728B1/de not_active Expired
- 1979-12-18 IT IT28131/79A patent/IT1165434B/it active
Also Published As
Publication number | Publication date |
---|---|
IT7928131A0 (it) | 1979-12-18 |
EP0013728B1 (de) | 1984-03-21 |
CA1120611A (en) | 1982-03-23 |
DE2966841D1 (en) | 1984-04-26 |
JPS5591843A (en) | 1980-07-11 |
EP0013728A1 (de) | 1980-08-06 |
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