IT1051796B - Disposizione circuitale per l addizione e la sottrazione in impianti elettronici per la elaborazione di dati - Google Patents

Disposizione circuitale per l addizione e la sottrazione in impianti elettronici per la elaborazione di dati

Info

Publication number
IT1051796B
IT1051796B IT29905/75A IT2990575A IT1051796B IT 1051796 B IT1051796 B IT 1051796B IT 29905/75 A IT29905/75 A IT 29905/75A IT 2990575 A IT2990575 A IT 2990575A IT 1051796 B IT1051796 B IT 1051796B
Authority
IT
Italy
Prior art keywords
circuitive
subtraction
provision
data
processing
Prior art date
Application number
IT29905/75A
Other languages
English (en)
Original Assignee
Olympia Werke Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympia Werke Ag filed Critical Olympia Werke Ag
Application granted granted Critical
Publication of IT1051796B publication Critical patent/IT1051796B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Complex Calculations (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Devices For Executing Special Programs (AREA)
IT29905/75A 1974-12-21 1975-12-02 Disposizione circuitale per l addizione e la sottrazione in impianti elettronici per la elaborazione di dati IT1051796B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2460897A DE2460897C3 (de) 1974-12-21 1974-12-21 Parallel-Rechenwerk für Addition und Subtraktion

Publications (1)

Publication Number Publication Date
IT1051796B true IT1051796B (it) 1981-05-20

Family

ID=5934289

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29905/75A IT1051796B (it) 1974-12-21 1975-12-02 Disposizione circuitale per l addizione e la sottrazione in impianti elettronici per la elaborazione di dati

Country Status (7)

Country Link
US (1) US4010359A (it)
JP (1) JPS5186938A (it)
DE (1) DE2460897C3 (it)
FR (1) FR2295481A1 (it)
GB (1) GB1531470A (it)
IT (1) IT1051796B (it)
NL (1) NL172992C (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4100603A (en) * 1976-12-16 1978-07-11 Joseph Lyndon Boyd Feet, inches and sixteenths adder
JPS5380933A (en) * 1976-12-25 1978-07-17 Toshiba Corp Decimal correction circuit
US4471454A (en) * 1981-10-27 1984-09-11 Ibm Corporation Fast, efficient, small adder
US6546411B1 (en) 1999-12-03 2003-04-08 International Business Machines Corporation High-speed radix 100 parallel adder

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB802705A (en) * 1956-05-14 1958-10-08 British Tabulating Mach Co Ltd Improvements in or relating to digital calculating apparatus
NL133891C (it) * 1957-04-02
GB913605A (en) * 1959-03-24 1962-12-19 Developments Ltd Comp Improvements in or relating to electronic calculating apparatus
NL276777A (it) * 1961-04-04
US3339064A (en) * 1962-09-28 1967-08-29 Nippon Electric Co Decimal addition system
GB1103384A (en) * 1964-03-02 1968-02-14 Olivetti & Co Spa Improvements in or relating to electronic computers
DE2352686B2 (de) * 1973-10-20 1978-05-11 Vereinigte Flugtechnische Werke- Fokker Gmbh, 2800 Bremen Dezimaler Parallel-Addierer/Substrahierer

Also Published As

Publication number Publication date
FR2295481A1 (fr) 1976-07-16
NL172992B (nl) 1983-06-16
JPS5186938A (en) 1976-07-30
GB1531470A (en) 1978-11-08
NL7514786A (nl) 1976-06-23
DE2460897B2 (de) 1978-01-26
NL172992C (nl) 1983-11-16
DE2460897C3 (de) 1978-10-05
FR2295481B1 (it) 1981-04-10
US4010359A (en) 1977-03-01
DE2460897A1 (de) 1976-07-01

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