IT1049044B - Unita di interfaccia di memoria - Google Patents

Unita di interfaccia di memoria

Info

Publication number
IT1049044B
IT1049044B IT29118/75A IT2911875A IT1049044B IT 1049044 B IT1049044 B IT 1049044B IT 29118/75 A IT29118/75 A IT 29118/75A IT 2911875 A IT2911875 A IT 2911875A IT 1049044 B IT1049044 B IT 1049044B
Authority
IT
Italy
Prior art keywords
interface unit
memory interface
memory
unit
interface
Prior art date
Application number
IT29118/75A
Other languages
English (en)
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Application granted granted Critical
Publication of IT1049044B publication Critical patent/IT1049044B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/128—Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0851—Cache with interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
IT29118/75A 1974-11-11 1975-11-07 Unita di interfaccia di memoria IT1049044B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/522,553 US3967247A (en) 1974-11-11 1974-11-11 Storage interface unit

Publications (1)

Publication Number Publication Date
IT1049044B true IT1049044B (it) 1981-01-20

Family

ID=24081323

Family Applications (1)

Application Number Title Priority Date Filing Date
IT29118/75A IT1049044B (it) 1974-11-11 1975-11-07 Unita di interfaccia di memoria

Country Status (8)

Country Link
US (1) US3967247A (it)
JP (1) JPS6118222B2 (it)
CH (1) CH607139A5 (it)
DE (2) DE2550339C2 (it)
FR (1) FR2290710A1 (it)
GB (1) GB1532798A (it)
IT (1) IT1049044B (it)
SE (1) SE411404B (it)

Families Citing this family (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4073005A (en) * 1974-01-21 1978-02-07 Control Data Corporation Multi-processor computer system
FR2348544A1 (fr) * 1976-04-15 1977-11-10 Honeywell Bull Soc Ind Ensemble double de memoire associative
DE2703559A1 (de) * 1977-01-28 1978-08-03 Siemens Ag Rechnersystem
US4126893A (en) * 1977-02-17 1978-11-21 Xerox Corporation Interrupt request controller for data processing system
US4158235A (en) * 1977-04-18 1979-06-12 Burroughs Corporation Multi port time-shared associative buffer storage pool
US4149262A (en) * 1977-04-19 1979-04-10 Semionics Associates Associative memory device with variable recognition criteria
US4092713A (en) * 1977-06-13 1978-05-30 Sperry Rand Corporation Post-write address word correction in cache memory system
US4141067A (en) * 1977-06-13 1979-02-20 General Automation Multiprocessor system with cache memory
US4142234A (en) * 1977-11-28 1979-02-27 International Business Machines Corporation Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system
JPS5489444A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Associative memory processing system
US4168541A (en) * 1978-09-25 1979-09-18 Sperry Rand Corporation Paired least recently used block replacement system
US4432050A (en) * 1978-10-02 1984-02-14 Honeywell Information Systems, Inc. Data processing system write protection mechanism
US4258417A (en) * 1978-10-23 1981-03-24 International Business Machines Corporation System for interfacing between main store memory and a central processor
CA1123964A (en) * 1978-10-26 1982-05-18 Anthony J. Capozzi Integrated multilevel storage hierarchy for a data processing system
US4323968A (en) * 1978-10-26 1982-04-06 International Business Machines Corporation Multilevel storage system having unitary control of data transfers
GB2037039B (en) * 1978-12-11 1983-08-17 Honeywell Inf Systems Cache memory system
US4225922A (en) * 1978-12-11 1980-09-30 Honeywell Information Systems Inc. Command queue apparatus included within a cache unit for facilitating command sequencing
US4276609A (en) * 1979-01-04 1981-06-30 Ncr Corporation CCD memory retrieval system
US4298929A (en) * 1979-01-26 1981-11-03 International Business Machines Corporation Integrated multilevel storage hierarchy for a data processing system with improved channel to memory write capability
US5241666A (en) * 1979-06-04 1993-08-31 Unisys Corporation Variable rate improvement of disc cache subsystem
US4868734A (en) * 1984-04-30 1989-09-19 Unisys Corp. Variable rate improvement of disc cache subsystem
US4298932A (en) * 1979-06-11 1981-11-03 International Business Machines Corporation Serial storage subsystem for a data processor
US4445191A (en) * 1979-08-13 1984-04-24 Burroughs Corporation Data word handling enhancement in a page oriented named-data hierarchical memory system
DE2934771C3 (de) * 1979-08-28 1982-03-25 Siemens AG, 1000 Berlin und 8000 München Speichervorrichtung.
US4317168A (en) * 1979-11-23 1982-02-23 International Business Machines Corporation Cache organization enabling concurrent line castout and line fetch transfers with main storage
JPS5680872A (en) * 1979-12-06 1981-07-02 Fujitsu Ltd Buffer memory control system
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4323967A (en) * 1980-04-15 1982-04-06 Honeywell Information Systems Inc. Local bus interface for controlling information transfers between units in a central subsystem
US4371929A (en) * 1980-05-05 1983-02-01 Ibm Corporation Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory
US4382278A (en) * 1980-06-05 1983-05-03 Texas Instruments Incorporated Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache
US4370710A (en) * 1980-08-26 1983-01-25 Control Data Corporation Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
US4381541A (en) * 1980-08-28 1983-04-26 Sperry Corporation Buffer memory referencing system for two data words
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
EP0055579B1 (en) * 1980-12-31 1991-03-20 Bull HN Information Systems Inc. Cache memories with double word access
US4355306A (en) * 1981-01-30 1982-10-19 International Business Machines Corporation Dynamic stack data compression and decompression system
US4414644A (en) * 1981-04-03 1983-11-08 International Business Machines Corporation Method and apparatus for discarding data from a buffer after reading such data
US4821184A (en) * 1981-05-22 1989-04-11 Data General Corporation Universal addressing system for a digital data processing system
CA1187198A (en) * 1981-06-15 1985-05-14 Takashi Chiba System for controlling access to channel buffers
US4439837A (en) * 1981-06-16 1984-03-27 Ncr Corporation Non-volatile memory system for intelligent terminals
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
JPS58147879A (ja) * 1982-02-26 1983-09-02 Toshiba Corp キヤツシユメモリ制御方式
US4811203A (en) * 1982-03-03 1989-03-07 Unisys Corporation Hierarchial memory system with separate criteria for replacement and writeback without replacement
US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US4574346A (en) * 1982-09-29 1986-03-04 International Business Machines Corporation Method and apparatus for peripheral data handling hierarchies
US4675812A (en) * 1983-02-14 1987-06-23 International Business Machines Corp. Priority circuit for channel subsystem having components with diverse and changing requirement for system resources
US4607331A (en) * 1983-05-13 1986-08-19 Motorola, Inc. Method and apparatus for implementing an algorithm associated with stored information
US4695951A (en) * 1983-07-07 1987-09-22 Honeywell Bull Inc. Computer hierarchy control
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
US4625273A (en) * 1983-08-30 1986-11-25 Amdahl Corporation Apparatus for fast data storage with deferred error reporting
US4710966A (en) * 1984-01-04 1987-12-01 Itek Corporation Digital frame processor pipe line circuit
US4736293A (en) * 1984-04-11 1988-04-05 American Telephone And Telegraph Company, At&T Bell Laboratories Interleaved set-associative memory
USRE34052E (en) * 1984-05-31 1992-09-01 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
US4630195A (en) * 1984-05-31 1986-12-16 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
DE3429571A1 (de) * 1984-08-10 1986-02-20 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zur prioritaetsbezogenen einordnung und registrierung von speicherabschnitten bzw. speicherbaenken, unter anwendung des lru-algorithmus
ATE48195T1 (de) * 1984-08-10 1989-12-15 Siemens Ag Schaltungsanordnung zur prioritaetsbezogenen einordnung und registrierung einzelner speicherabschnitte bzw. baenke unter anwendung des lru-algorithmus.
JPH0670773B2 (ja) * 1984-11-01 1994-09-07 富士通株式会社 先行制御方式
US4714994A (en) * 1985-04-30 1987-12-22 International Business Machines Corp. Instruction prefetch buffer control
CH672816A5 (it) * 1986-10-03 1989-12-29 Pantex Stahl Ag
US5034885A (en) * 1988-03-15 1991-07-23 Kabushiki Kaisha Toshiba Cache memory device with fast data-write capacity
US4939641A (en) * 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
US5097409A (en) * 1988-06-30 1992-03-17 Wang Laboratories, Inc. Multi-processor system with cache memories
US5027270A (en) * 1988-10-11 1991-06-25 Mips Computer Systems, Inc. Processor controlled interface with instruction streaming
US5025365A (en) * 1988-11-14 1991-06-18 Unisys Corporation Hardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors
US5202972A (en) * 1988-12-29 1993-04-13 International Business Machines Corporation Store buffer apparatus in a multiprocessor system
EP0419961A3 (en) * 1989-09-26 1991-10-23 Siemens Aktiengesellschaft Method and circuit for replacement control, particularly for a system containing digital memory elements
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5434990A (en) * 1990-08-06 1995-07-18 Ncr Corporation Method for serially or concurrently addressing n individually addressable memories each having an address latch and data latch
US5218246A (en) * 1990-09-14 1993-06-08 Acer, Incorporated MOS analog XOR amplifier
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
US5345582A (en) * 1991-12-20 1994-09-06 Unisys Corporation Failure detection for instruction processor associative cache memories
US5404484A (en) * 1992-09-16 1995-04-04 Hewlett-Packard Company Cache system for reducing memory latency times
US5673415A (en) * 1993-12-03 1997-09-30 Unisys Corporation High speed two-port interface unit where read commands suspend partially executed write commands
JP3266470B2 (ja) * 1994-10-03 2002-03-18 インターナショナル・ビジネス・マシーンズ・コーポレーション 強制順序で行う要求毎ライト・スルー・キャッシュを有するデータ処理システム
WO1996012229A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. Indexing and multiplexing of interleaved cache memory arrays
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
IL142400A0 (en) * 1998-09-18 2002-03-10 Harris Corp Distributed trunking mechanism for vhf networking
US7069406B2 (en) * 1999-07-02 2006-06-27 Integrated Device Technology, Inc. Double data rate synchronous SRAM with 100% bus utilization
US9274964B2 (en) 2012-02-02 2016-03-01 Qualcomm Incorporated Multi-bank cache memory

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE622921A (it) * 1961-10-06
BE629069A (it) * 1962-03-05
US3275991A (en) * 1962-12-03 1966-09-27 Bunker Ramo Memory system
US3569938A (en) * 1967-12-20 1971-03-09 Ibm Storage manager
US3581291A (en) * 1968-10-31 1971-05-25 Hitachi Ltd Memory control system in multiprocessing system
US3588839A (en) * 1969-01-15 1971-06-28 Ibm Hierarchical memory updating system
US3670309A (en) * 1969-12-23 1972-06-13 Ibm Storage control system
US3647348A (en) * 1970-01-19 1972-03-07 Fairchild Camera Instr Co Hardware-oriented paging control system
US3737871A (en) * 1971-07-28 1973-06-05 Hewlett Packard Co Stack register renamer
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories

Also Published As

Publication number Publication date
JPS6118222B2 (it) 1986-05-12
SE7512524L (sv) 1976-05-12
DE2550339A1 (de) 1976-06-16
CH607139A5 (it) 1978-11-30
US3967247A (en) 1976-06-29
DE2560206C2 (de) 1983-01-20
GB1532798A (en) 1978-11-22
JPS5176936A (it) 1976-07-03
FR2290710B1 (it) 1980-04-18
DE2550339C2 (de) 1982-10-14
SE411404B (sv) 1979-12-17
FR2290710A1 (fr) 1976-06-04

Similar Documents

Publication Publication Date Title
IT1049044B (it) Unita di interfaccia di memoria
IT1041829B (it) Unita di emissione
IT1052353B (it) Unita di immagazzinaggio
IT1045587B (it) Unita di servizio
IT1043638B (it) Memoria perfezionata
IT1050046B (it) Unita di perforazione
IT1037837B (it) Dispositivo di nescolarmento
SE404471B (sv) Borstenhet
SE7514390L (sv) Halvledaraggregat
JPS5176577A (ja) Denkikaiheiki
JPS5113661A (ja) Denkiengeihasami
SE7512541L (sv) Elektrodenhet
IT1042144B (it) Radiatore
JPS5170485A (ja) Denkikonekuta
BE835746A (fr) Radiateur
JPS5167985A (ja) Denkikonekuta
BE832915A (fr) Memoire-tampon
JPS5131191A (ja) Suireikaitentaiinkyoku x senkan
SU522523A1 (ru) Запоминающее устройство
FR2284502A1 (fr) Di
DK155294C (da) Radiator
JPS5121489A (ja) Zenshuhoshagatakaitenyokyoku x senkan
IT1043715B (it) Dispositivo di memoria
JPS5115103A (ja) Shingohatsudenki
JPS51668A (ja) Denkikaiheisochi