IT1031241B - Sistema perfezionato per la fabricazione di resistori su wafer di silicio e simili - Google Patents

Sistema perfezionato per la fabricazione di resistori su wafer di silicio e simili

Info

Publication number
IT1031241B
IT1031241B IT19693/75A IT1969375A IT1031241B IT 1031241 B IT1031241 B IT 1031241B IT 19693/75 A IT19693/75 A IT 19693/75A IT 1969375 A IT1969375 A IT 1969375A IT 1031241 B IT1031241 B IT 1031241B
Authority
IT
Italy
Prior art keywords
resistors
manufacture
similar
silicon wafers
perfected system
Prior art date
Application number
IT19693/75A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1031241B publication Critical patent/IT1031241B/it

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20Resistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/3115Doping the insulating layers
    • H01L21/31155Doping the insulating layers by ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT19693/75A 1974-03-04 1975-01-29 Sistema perfezionato per la fabricazione di resistori su wafer di silicio e simili IT1031241B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US448100A US3922708A (en) 1974-03-04 1974-03-04 Method of producing high value ion implanted resistors

Publications (1)

Publication Number Publication Date
IT1031241B true IT1031241B (it) 1979-04-30

Family

ID=23778996

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19693/75A IT1031241B (it) 1974-03-04 1975-01-29 Sistema perfezionato per la fabricazione di resistori su wafer di silicio e simili

Country Status (7)

Country Link
US (1) US3922708A (US07321065-20080122-C00020.png)
JP (1) JPS50120783A (US07321065-20080122-C00020.png)
CA (1) CA1023875A (US07321065-20080122-C00020.png)
DE (1) DE2458734A1 (US07321065-20080122-C00020.png)
FR (1) FR2263608B1 (US07321065-20080122-C00020.png)
GB (1) GB1451296A (US07321065-20080122-C00020.png)
IT (1) IT1031241B (US07321065-20080122-C00020.png)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2446088A1 (de) * 1974-09-26 1976-04-01 Siemens Ag Statisches speicherelement und verfahren zu seiner herstellung
US4053922A (en) * 1976-05-19 1977-10-11 General Electric Company Light triggered thyristor having controlled turn on delay
US4249196A (en) * 1978-08-21 1981-02-03 Burroughs Corporation Integrated circuit module with integral capacitor
JPS57121254A (en) * 1981-01-21 1982-07-28 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS57201050A (en) * 1981-06-05 1982-12-09 Seiko Epson Corp Multilayer wiring structure
DE3138960A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur erzeugung elektrisch leitender schichten
US4722913A (en) * 1986-10-17 1988-02-02 Thomson Components-Mostek Corporation Doped semiconductor vias to contacts
US4766450A (en) * 1987-07-17 1988-08-23 Xerox Corporation Charging deposition control in electrographic thin film writting head
US4868537A (en) * 1987-09-10 1989-09-19 Siliconix Incorporated Doped SiO2 resistor and method of forming same
US4950620A (en) * 1988-09-30 1990-08-21 Dallas Semiconductor Corp. Process for making integrated circuit with doped silicon dioxide load elements
JPH0756883B2 (ja) * 1990-05-25 1995-06-14 工業技術院長 電気的接続の形成方法とこれを用いて形成される集積回路
US6614088B1 (en) 2000-02-18 2003-09-02 James D. Beasom Breakdown improvement method and sturcture for lateral DMOS device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3390012A (en) * 1964-05-14 1968-06-25 Texas Instruments Inc Method of making dielectric bodies having conducting portions
US3682700A (en) * 1968-08-15 1972-08-08 Gale Ind Inc Method of imparting electrical conductivity to an amorphous substrate by ion implantation,and the product thereof
DE1812130C3 (de) * 1968-12-02 1975-01-16 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zum Herstellen einer Halbleiter- oder Dickfilmanordnung
US3614480A (en) * 1969-10-13 1971-10-19 Bell Telephone Labor Inc Temperature-stabilized electronic devices
US3620945A (en) * 1970-01-19 1971-11-16 Texas Instruments Inc Methods of making a composite dielectric body
US3693011A (en) * 1971-02-02 1972-09-19 Hughes Aircraft Co Ion implanted bolometer
JPS4884580A (US07321065-20080122-C00020.png) * 1972-02-12 1973-11-09

Also Published As

Publication number Publication date
JPS50120783A (US07321065-20080122-C00020.png) 1975-09-22
DE2458734A1 (de) 1975-09-11
CA1023875A (en) 1978-01-03
FR2263608A1 (US07321065-20080122-C00020.png) 1975-10-03
FR2263608B1 (US07321065-20080122-C00020.png) 1976-12-31
GB1451296A (en) 1976-09-29
US3922708A (en) 1975-11-25

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