IT1027154B - Dispositivo operatore di caratteri a cifre decimali codificate nel sistema binaric - Google Patents

Dispositivo operatore di caratteri a cifre decimali codificate nel sistema binaric

Info

Publication number
IT1027154B
IT1027154B IT70724/74A IT7072474A IT1027154B IT 1027154 B IT1027154 B IT 1027154B IT 70724/74 A IT70724/74 A IT 70724/74A IT 7072474 A IT7072474 A IT 7072474A IT 1027154 B IT1027154 B IT 1027154B
Authority
IT
Italy
Prior art keywords
binaric
characters
operator device
decimal digits
digits coded
Prior art date
Application number
IT70724/74A
Other languages
English (en)
Original Assignee
Cii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cii filed Critical Cii
Application granted granted Critical
Publication of IT1027154B publication Critical patent/IT1027154B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924—Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Complex Calculations (AREA)
  • Debugging And Monitoring (AREA)
  • Image Processing (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
IT70724/74A 1974-01-07 1974-12-20 Dispositivo operatore di caratteri a cifre decimali codificate nel sistema binaric IT1027154B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7400463A FR2291542A1 (fr) 1974-01-07 1974-01-07 Operateur de caracteres travaillant en decimal binaire

Publications (1)

Publication Number Publication Date
IT1027154B true IT1027154B (it) 1978-11-20

Family

ID=9133174

Family Applications (1)

Application Number Title Priority Date Filing Date
IT70724/74A IT1027154B (it) 1974-01-07 1974-12-20 Dispositivo operatore di caratteri a cifre decimali codificate nel sistema binaric

Country Status (8)

Country Link
US (1) US4041290A (it)
BE (1) BE824064A (it)
DE (1) DE2500201C2 (it)
ES (1) ES433614A1 (it)
FR (1) FR2291542A1 (it)
GB (1) GB1490791A (it)
IT (1) IT1027154B (it)
NL (1) NL7416663A (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4276596A (en) * 1979-01-02 1981-06-30 Honeywell Information Systems Inc. Short operand alignment and merge operation
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories
CA1145054A (en) * 1979-01-02 1983-04-19 Honeywell Information Systems Inc. Data processing system with means to align operands
US4246644A (en) * 1979-01-02 1981-01-20 Honeywell Information Systems Inc. Vector branch indicators to control firmware
US4268909A (en) * 1979-01-02 1981-05-19 Honeywell Information Systems Inc. Numeric data fetch - alignment of data including scale factor difference
US4718033A (en) * 1985-06-28 1988-01-05 Hewlett-Packard Company Intermediate decimal correction for sequential addition

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1436161A (fr) * 1964-04-06 1966-04-22 Ibm Unité arithmétique et logique
US3621219A (en) * 1967-08-15 1971-11-16 Hayakawa Denki Kogyo Kk Arithmetic unit utilizing magnetic core matrix registers
US3571582A (en) * 1968-02-29 1971-03-23 Gen Electric Serial bcd adder/subtracter utilizing interlaced data
US3564507A (en) * 1968-04-10 1971-02-16 Ibm Asynchronous interface for use between a main memory and a central processing unit
JPS5036542B1 (it) * 1969-12-15 1975-11-26
US3701105A (en) * 1970-07-24 1972-10-24 Ibm A central processing unit in which all data flow passes through a single arithmetic and logic unit
JPS5021330B1 (it) * 1970-11-30 1975-07-22
JPS5314182B2 (it) * 1972-05-31 1978-05-16
US3899667A (en) * 1972-12-26 1975-08-12 Raytheon Co Serial three point discrete fourier transform apparatus

Also Published As

Publication number Publication date
DE2500201C2 (de) 1985-01-10
DE2500201A1 (de) 1975-07-17
US4041290A (en) 1977-08-09
GB1490791A (en) 1977-11-02
BE824064A (fr) 1975-07-03
NL7416663A (nl) 1975-07-09
FR2291542B1 (it) 1978-03-31
ES433614A1 (es) 1976-11-16
FR2291542A1 (fr) 1976-06-11

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