IN2014CN04649A - - Google Patents

Info

Publication number
IN2014CN04649A
IN2014CN04649A IN4649CHN2014A IN2014CN04649A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A IN 4649CHN2014 A IN4649CHN2014 A IN 4649CHN2014A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A
Authority
IN
India
Prior art keywords
cache
miss
virtual
detector
aliased
Prior art date
Application number
Other languages
English (en)
Inventor
James Norris Dieffenderfer
Robert D Clancy
Thomas Philip Speier
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of IN2014CN04649A publication Critical patent/IN2014CN04649A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN4649CHN2014 2012-01-18 2013-01-17 IN2014CN04649A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201261587756P 2012-01-18 2012-01-18
US13/478,149 US9110830B2 (en) 2012-01-18 2012-05-23 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods
PCT/US2013/021849 WO2013109696A2 (en) 2012-01-18 2013-01-17 Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods

Publications (1)

Publication Number Publication Date
IN2014CN04649A true IN2014CN04649A (zh) 2015-09-18

Family

ID=48780825

Family Applications (1)

Application Number Title Priority Date Filing Date
IN4649CHN2014 IN2014CN04649A (zh) 2012-01-18 2013-01-17

Country Status (9)

Country Link
US (1) US9110830B2 (zh)
EP (1) EP2805245B1 (zh)
JP (1) JP6019136B2 (zh)
KR (1) KR101570155B1 (zh)
CN (1) CN104040509B (zh)
BR (1) BR112014017659A8 (zh)
IN (1) IN2014CN04649A (zh)
TW (1) TWI502349B (zh)
WO (1) WO2013109696A2 (zh)

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CN105793926B (zh) * 2013-12-27 2021-06-01 英特尔公司 具有双电压非对称存储器单元的芯片及其操作方法和装置
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US9934152B1 (en) * 2015-02-17 2018-04-03 Marvell International Ltd. Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache
CN106155937B (zh) * 2015-04-07 2019-03-05 龙芯中科技术有限公司 缓存访问方法、设备和处理器
US10121220B2 (en) * 2015-04-28 2018-11-06 Nvidia Corporation System and method for creating aliased mappings to minimize impact of cache invalidation
US20160378684A1 (en) 2015-06-26 2016-12-29 Intel Corporation Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory
CN105095113B (zh) * 2015-07-21 2018-06-29 浪潮(北京)电子信息产业有限公司 一种缓存管理方法和系统
US9626300B2 (en) * 2015-07-27 2017-04-18 Google Inc. Address caching in switches
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US10042777B2 (en) * 2016-03-30 2018-08-07 Qualcomm Incorporated Hardware-based translation lookaside buffer (TLB) invalidation
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US10067870B2 (en) 2016-04-01 2018-09-04 Intel Corporation Apparatus and method for low-overhead synchronous page table updates
US10120814B2 (en) 2016-04-01 2018-11-06 Intel Corporation Apparatus and method for lazy translation lookaside buffer (TLB) coherence
US20180089094A1 (en) * 2016-09-23 2018-03-29 Qualcomm Incorporated Precise invalidation of virtually tagged caches
US10061698B2 (en) * 2017-01-31 2018-08-28 Qualcomm Incorporated Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur
US10318436B2 (en) * 2017-07-25 2019-06-11 Qualcomm Incorporated Precise invalidation of virtually tagged caches
WO2019025864A2 (en) * 2017-07-30 2019-02-07 Sity Elad ARCHITECTURE OF DISTRIBUTED PROCESSORS BASED ON MEMORIES
US10725782B2 (en) * 2017-09-12 2020-07-28 Qualcomm Incorporated Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
KR102151180B1 (ko) * 2017-11-20 2020-09-02 삼성전자주식회사 효율적인 가상 캐시 구현을 위한 시스템 및 방법
US10545879B2 (en) * 2018-03-26 2020-01-28 Arm Limited Apparatus and method for handling access requests
US10846235B2 (en) 2018-04-28 2020-11-24 International Business Machines Corporation Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator
US10489305B1 (en) 2018-08-14 2019-11-26 Texas Instruments Incorporated Prefetch kill and revival in an instruction cache
CN109144901B (zh) * 2018-10-10 2024-01-02 古进 公式化虚拟地址转换
US10977175B2 (en) * 2019-02-01 2021-04-13 International Business Machines Corporation Virtual cache tag renaming for synonym handling
US11061819B2 (en) 2019-05-28 2021-07-13 Micron Technology, Inc. Distributed computing based on memory as a service
US11169930B2 (en) * 2019-05-28 2021-11-09 Micron Technology, Inc. Fine grain data migration to or from borrowed memory

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Also Published As

Publication number Publication date
JP6019136B2 (ja) 2016-11-02
CN104040509A (zh) 2014-09-10
EP2805245B1 (en) 2019-10-09
KR20140116935A (ko) 2014-10-06
TW201346557A (zh) 2013-11-16
BR112014017659A2 (zh) 2017-06-20
US9110830B2 (en) 2015-08-18
JP2015507810A (ja) 2015-03-12
WO2013109696A2 (en) 2013-07-25
BR112014017659A8 (pt) 2017-07-11
TWI502349B (zh) 2015-10-01
WO2013109696A3 (en) 2013-10-03
EP2805245A2 (en) 2014-11-26
US20130185520A1 (en) 2013-07-18
KR101570155B1 (ko) 2015-11-19
CN104040509B (zh) 2018-01-30

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