IN2014CN04649A - - Google Patents
Info
- Publication number
- IN2014CN04649A IN2014CN04649A IN4649CHN2014A IN2014CN04649A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A IN 4649CHN2014 A IN4649CHN2014 A IN 4649CHN2014A IN 2014CN04649 A IN2014CN04649 A IN 2014CN04649A
- Authority
- IN
- India
- Prior art keywords
- cache
- miss
- virtual
- detector
- aliased
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
- G06F12/1063—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently virtually addressed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261587756P | 2012-01-18 | 2012-01-18 | |
US13/478,149 US9110830B2 (en) | 2012-01-18 | 2012-05-23 | Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods |
PCT/US2013/021849 WO2013109696A2 (en) | 2012-01-18 | 2013-01-17 | Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methods |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014CN04649A true IN2014CN04649A (es) | 2015-09-18 |
Family
ID=48780825
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN4649CHN2014 IN2014CN04649A (es) | 2012-01-18 | 2013-01-17 |
Country Status (9)
Country | Link |
---|---|
US (1) | US9110830B2 (es) |
EP (1) | EP2805245B1 (es) |
JP (1) | JP6019136B2 (es) |
KR (1) | KR101570155B1 (es) |
CN (1) | CN104040509B (es) |
BR (1) | BR112014017659A8 (es) |
IN (1) | IN2014CN04649A (es) |
TW (1) | TWI502349B (es) |
WO (1) | WO2013109696A2 (es) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013097671A (ja) * | 2011-11-02 | 2013-05-20 | Fujitsu Ltd | アドレス変換装置、アドレス変換装置の制御方法及び演算処理装置 |
US20160379706A1 (en) * | 2013-12-27 | 2016-12-29 | Intel Corporation | Dual voltage asymmetric memory cell |
CN104375963B (zh) | 2014-11-28 | 2019-03-15 | 上海兆芯集成电路有限公司 | 基于缓存一致性的控制系统和方法 |
JP6207765B2 (ja) | 2014-12-14 | 2017-10-04 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | モードに応じてセットの1つ又は複数を選択的に選択するように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ |
JP6209689B2 (ja) | 2014-12-14 | 2017-10-04 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | モードに応じてウェイの全部又はサブセットに選択的に割り当てるように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ |
JP6218971B2 (ja) | 2014-12-14 | 2017-10-25 | ヴィア アライアンス セミコンダクター カンパニー リミテッド | アドレス・タグ・ビットに基づく動的キャッシュ置換ウェイ選択 |
US9934152B1 (en) * | 2015-02-17 | 2018-04-03 | Marvell International Ltd. | Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache |
CN106155937B (zh) * | 2015-04-07 | 2019-03-05 | 龙芯中科技术有限公司 | 缓存访问方法、设备和处理器 |
US10121220B2 (en) * | 2015-04-28 | 2018-11-06 | Nvidia Corporation | System and method for creating aliased mappings to minimize impact of cache invalidation |
US20160378684A1 (en) | 2015-06-26 | 2016-12-29 | Intel Corporation | Multi-page check hints for selective checking of protected container page versus regular page type indications for pages of convertible memory |
CN105095113B (zh) * | 2015-07-21 | 2018-06-29 | 浪潮(北京)电子信息产业有限公司 | 一种缓存管理方法和系统 |
US9626300B2 (en) * | 2015-07-27 | 2017-04-18 | Google Inc. | Address caching in switches |
GB2543745B (en) * | 2015-10-15 | 2018-07-04 | Advanced Risc Mach Ltd | An apparatus and method for operating a virtually indexed physically tagged cache |
US10042777B2 (en) * | 2016-03-30 | 2018-08-07 | Qualcomm Incorporated | Hardware-based translation lookaside buffer (TLB) invalidation |
US9772943B1 (en) * | 2016-04-01 | 2017-09-26 | Cavium, Inc. | Managing synonyms in virtual-address caches |
US10120814B2 (en) | 2016-04-01 | 2018-11-06 | Intel Corporation | Apparatus and method for lazy translation lookaside buffer (TLB) coherence |
US10067870B2 (en) | 2016-04-01 | 2018-09-04 | Intel Corporation | Apparatus and method for low-overhead synchronous page table updates |
US20180089094A1 (en) * | 2016-09-23 | 2018-03-29 | Qualcomm Incorporated | Precise invalidation of virtually tagged caches |
US10061698B2 (en) * | 2017-01-31 | 2018-08-28 | Qualcomm Incorporated | Reducing or avoiding buffering of evicted cache data from an uncompressed cache memory in a compression memory system when stalled write operations occur |
US10318436B2 (en) * | 2017-07-25 | 2019-06-11 | Qualcomm Incorporated | Precise invalidation of virtually tagged caches |
CN113918481A (zh) * | 2017-07-30 | 2022-01-11 | 纽罗布拉德有限公司 | 一种存储器芯片 |
US10725782B2 (en) * | 2017-09-12 | 2020-07-28 | Qualcomm Incorporated | Providing variable interpretation of usefulness indicators for memory tables in processor-based systems |
KR102151180B1 (ko) * | 2017-11-20 | 2020-09-02 | 삼성전자주식회사 | 효율적인 가상 캐시 구현을 위한 시스템 및 방법 |
US10545879B2 (en) * | 2018-03-26 | 2020-01-28 | Arm Limited | Apparatus and method for handling access requests |
US10846235B2 (en) * | 2018-04-28 | 2020-11-24 | International Business Machines Corporation | Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator |
US10489305B1 (en) | 2018-08-14 | 2019-11-26 | Texas Instruments Incorporated | Prefetch kill and revival in an instruction cache |
CN109144901B (zh) * | 2018-10-10 | 2024-01-02 | 古进 | 公式化虚拟地址转换 |
US10977175B2 (en) * | 2019-02-01 | 2021-04-13 | International Business Machines Corporation | Virtual cache tag renaming for synonym handling |
US11169930B2 (en) * | 2019-05-28 | 2021-11-09 | Micron Technology, Inc. | Fine grain data migration to or from borrowed memory |
US11061819B2 (en) | 2019-05-28 | 2021-07-13 | Micron Technology, Inc. | Distributed computing based on memory as a service |
US11048636B2 (en) * | 2019-07-31 | 2021-06-29 | Micron Technology, Inc. | Cache with set associativity having data defined cache sets |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02208756A (ja) * | 1989-02-09 | 1990-08-20 | Nec Corp | キャッシュメモリ制御方式 |
JPH07287668A (ja) | 1994-04-19 | 1995-10-31 | Hitachi Ltd | データ処理装置 |
US6175906B1 (en) * | 1996-12-06 | 2001-01-16 | Advanced Micro Devices, Inc. | Mechanism for fast revalidation of virtual tags |
US6298411B1 (en) * | 1999-01-05 | 2001-10-02 | Compaq Computer Corporation | Method and apparatus to share instruction images in a virtual cache |
US8417915B2 (en) | 2005-08-05 | 2013-04-09 | Arm Limited | Alias management within a virtually indexed and physically tagged cache memory |
JP4297968B2 (ja) | 2006-02-14 | 2009-07-15 | 富士通株式会社 | コヒーレンシ維持装置およびコヒーレンシ維持方法 |
US7802055B2 (en) * | 2006-04-19 | 2010-09-21 | Qualcomm Incorporated | Virtually-tagged instruction cache with physically-tagged behavior |
JP4783229B2 (ja) | 2006-07-19 | 2011-09-28 | パナソニック株式会社 | キャッシュメモリシステム |
US7991963B2 (en) * | 2007-12-31 | 2011-08-02 | Intel Corporation | In-memory, in-page directory cache coherency scheme |
US8041894B2 (en) | 2008-02-25 | 2011-10-18 | International Business Machines Corporation | Method and system for a multi-level virtual/real cache system with synonym resolution |
US8090984B2 (en) * | 2008-12-10 | 2012-01-03 | Freescale Semiconductor, Inc. | Error detection and communication of an error location in multi-processor data processing system having processors operating in Lockstep |
US20110145542A1 (en) * | 2009-12-15 | 2011-06-16 | Qualcomm Incorporated | Apparatuses, Systems, and Methods for Reducing Translation Lookaside Buffer (TLB) Lookups |
JP2011198091A (ja) | 2010-03-19 | 2011-10-06 | Toshiba Corp | 仮想アドレスキャッシュメモリ、プロセッサ及びマルチプロセッサシステム |
KR20120083160A (ko) * | 2011-01-17 | 2012-07-25 | 삼성전자주식회사 | 메모리 관리 유닛, 이를 포함하는 장치들, 및 이의 동작 방법 |
US8972642B2 (en) * | 2011-10-04 | 2015-03-03 | Qualcomm Incorporated | Low latency two-level interrupt controller interface to multi-threaded processor |
JP2013097671A (ja) * | 2011-11-02 | 2013-05-20 | Fujitsu Ltd | アドレス変換装置、アドレス変換装置の制御方法及び演算処理装置 |
-
2012
- 2012-05-23 US US13/478,149 patent/US9110830B2/en not_active Expired - Fee Related
-
2013
- 2013-01-17 JP JP2014553396A patent/JP6019136B2/ja not_active Expired - Fee Related
- 2013-01-17 CN CN201380005243.8A patent/CN104040509B/zh active Active
- 2013-01-17 WO PCT/US2013/021849 patent/WO2013109696A2/en active Application Filing
- 2013-01-17 KR KR1020147022880A patent/KR101570155B1/ko active IP Right Grant
- 2013-01-17 EP EP13702155.6A patent/EP2805245B1/en active Active
- 2013-01-17 IN IN4649CHN2014 patent/IN2014CN04649A/en unknown
- 2013-01-17 BR BR112014017659A patent/BR112014017659A8/pt not_active IP Right Cessation
- 2013-01-18 TW TW102102094A patent/TWI502349B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20140116935A (ko) | 2014-10-06 |
CN104040509B (zh) | 2018-01-30 |
EP2805245A2 (en) | 2014-11-26 |
WO2013109696A3 (en) | 2013-10-03 |
US20130185520A1 (en) | 2013-07-18 |
JP2015507810A (ja) | 2015-03-12 |
WO2013109696A2 (en) | 2013-07-25 |
JP6019136B2 (ja) | 2016-11-02 |
CN104040509A (zh) | 2014-09-10 |
TWI502349B (zh) | 2015-10-01 |
EP2805245B1 (en) | 2019-10-09 |
BR112014017659A8 (pt) | 2017-07-11 |
KR101570155B1 (ko) | 2015-11-19 |
BR112014017659A2 (es) | 2017-06-20 |
US9110830B2 (en) | 2015-08-18 |
TW201346557A (zh) | 2013-11-16 |
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