IN2014CN02958A - - Google Patents

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Publication number
IN2014CN02958A
IN2014CN02958A IN2958CHN2014A IN2014CN02958A IN 2014CN02958 A IN2014CN02958 A IN 2014CN02958A IN 2958CHN2014 A IN2958CHN2014 A IN 2958CHN2014A IN 2014CN02958 A IN2014CN02958 A IN 2014CN02958A
Authority
IN
India
Prior art keywords
software
segments
pinned
volatile memory
type
Prior art date
Application number
Other languages
English (en)
Inventor
Fred Charles Thomas Iii
Walter A Gaspard
Chi W So
Original Assignee
Hewlett Packard Development Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co filed Critical Hewlett Packard Development Co
Publication of IN2014CN02958A publication Critical patent/IN2014CN02958A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/222—Non-volatile memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6042—Allocation of cache space to multiple users or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
IN2958CHN2014 2011-10-26 2011-10-26 IN2014CN02958A (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/057913 WO2013062542A1 (en) 2011-10-26 2011-10-26 Segmented caches

Publications (1)

Publication Number Publication Date
IN2014CN02958A true IN2014CN02958A (zh) 2015-07-03

Family

ID=48168213

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2958CHN2014 IN2014CN02958A (zh) 2011-10-26 2011-10-26

Country Status (9)

Country Link
US (1) US9697115B2 (zh)
EP (1) EP2771795B1 (zh)
JP (1) JP2014534520A (zh)
KR (1) KR101842321B1 (zh)
CN (1) CN103999062A (zh)
BR (1) BR112014009920B1 (zh)
IN (1) IN2014CN02958A (zh)
TW (2) TWI574203B (zh)
WO (1) WO2013062542A1 (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10698826B1 (en) 2012-01-06 2020-06-30 Seagate Technology Llc Smart file location
US9268692B1 (en) * 2012-04-05 2016-02-23 Seagate Technology Llc User selectable caching
US9542324B1 (en) * 2012-04-05 2017-01-10 Seagate Technology Llc File associated pinning
US10185501B2 (en) * 2015-09-25 2019-01-22 Intel Corporation Method and apparatus for pinning memory pages in a multi-level system memory
US11165751B2 (en) * 2017-02-16 2021-11-02 Emerald Cactus Ventures, Inc. System and method for establishing simultaneous encrypted virtual private networks from a single computing device
US11122013B2 (en) * 2017-02-16 2021-09-14 Emerald Cactus Ventures, Inc. System and method for encrypting data interactions delineated by zones
US11165825B2 (en) * 2017-02-16 2021-11-02 Emerald Cactus Ventures, Inc. System and method for creating encrypted virtual private network hotspot
US20180336131A1 (en) * 2017-05-22 2018-11-22 Dell Products L.P. Optimizing Memory/Caching Relative to Application Profile
TWI649652B (zh) * 2017-12-29 2019-02-01 國科美國研究實驗室 Fast and safe data storage device and method

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EP0475639A3 (en) * 1990-08-31 1992-06-03 Kawasaki Steel Corporation Hard disk emulator
JPH06282488A (ja) 1993-03-25 1994-10-07 Mitsubishi Electric Corp キャッシュ記憶装置
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JPH10154101A (ja) * 1996-11-26 1998-06-09 Toshiba Corp データ記憶システム及び同システムに適用するキャッシュ制御方法
JPH10333984A (ja) 1997-05-30 1998-12-18 Matsushita Electric Ind Co Ltd 記録再生装置
US20020112116A1 (en) * 2000-11-17 2002-08-15 Nelson Mark Edward Methods, systems, and computer program products for storing data in collections of tagged data pieces
US7089371B2 (en) 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory
JP4095840B2 (ja) 2002-06-25 2008-06-04 株式会社日立製作所 キャッシュメモリ管理方法
JP2004118305A (ja) 2002-09-24 2004-04-15 Sharp Corp キャッシュメモリ制御装置
KR100970933B1 (ko) 2003-07-26 2010-07-20 엘지전자 주식회사 오퍼레이팅 시스템의 고속 부팅장치 및 방법
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US7620773B2 (en) 2005-04-15 2009-11-17 Microsoft Corporation In-line non volatile memory disk read cache and write buffer
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KR100755702B1 (ko) 2005-12-27 2007-09-05 삼성전자주식회사 비휘발성 메모리가 캐쉬로 사용되는 저장 장치 및 그 동작방법
US20080005462A1 (en) 2006-06-30 2008-01-03 Mosaid Technologies Incorporated Method of configuring non-volatile memory for a hybrid disk drive
KR101128234B1 (ko) 2006-08-23 2012-03-23 엘지전자 주식회사 메모리 접근 제어 장치 및 방법
US7554855B2 (en) 2006-12-20 2009-06-30 Mosaid Technologies Incorporated Hybrid solid-state memory system having volatile and non-volatile memory
JP2008250718A (ja) 2007-03-30 2008-10-16 Toshiba Corp 不揮発性キャッシュメモリを用いた記憶装置とその制御方法
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US8214596B2 (en) * 2008-09-30 2012-07-03 Intel Corporation Apparatus and method for segmented cache utilization
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KR20140040870A (ko) 2009-07-07 2014-04-04 엘에스아이 코포레이션 계층화된 비휘발성 스토리지를 위한 시스템 및 방법

Also Published As

Publication number Publication date
EP2771795A1 (en) 2014-09-03
EP2771795B1 (en) 2016-06-01
EP2771795A4 (en) 2015-08-05
TWI498811B (zh) 2015-09-01
TWI574203B (zh) 2017-03-11
BR112014009920B1 (pt) 2021-06-15
BR112014009920A2 (pt) 2017-04-25
KR20140091532A (ko) 2014-07-21
WO2013062542A8 (en) 2014-07-03
WO2013062542A1 (en) 2013-05-02
TW201329858A (zh) 2013-07-16
CN103999062A (zh) 2014-08-20
KR101842321B1 (ko) 2018-03-26
US20140297937A1 (en) 2014-10-02
TW201546712A (zh) 2015-12-16
JP2014534520A (ja) 2014-12-18
US9697115B2 (en) 2017-07-04

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