IN2014CN02550A - - Google Patents
Info
- Publication number
- IN2014CN02550A IN2014CN02550A IN2550CHN2014A IN2014CN02550A IN 2014CN02550 A IN2014CN02550 A IN 2014CN02550A IN 2550CHN2014 A IN2550CHN2014 A IN 2550CHN2014A IN 2014CN02550 A IN2014CN02550 A IN 2014CN02550A
- Authority
- IN
- India
- Prior art keywords
- wafer
- trenches
- via device
- conductive material
- wafer surface
- Prior art date
Links
- 239000004020 conductor Substances 0.000 abstract 4
- 239000000463 material Substances 0.000 abstract 2
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B06—GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS IN GENERAL
- B06B—METHODS OR APPARATUS FOR GENERATING OR TRANSMITTING MECHANICAL VIBRATIONS OF INFRASONIC, SONIC, OR ULTRASONIC FREQUENCY, e.g. FOR PERFORMING MECHANICAL WORK IN GENERAL
- B06B1/00—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency
- B06B1/02—Methods or apparatus for generating mechanical vibrations of infrasonic, sonic, or ultrasonic frequency making use of electrical energy
- B06B1/0292—Electrostatic transducers, e.g. electret-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Engineering (AREA)
- Transducers For Ultrasonic Waves (AREA)
- Micromachines (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Combinations Of Printed Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161547942P | 2011-10-17 | 2011-10-17 | |
PCT/IB2012/055547 WO2013057642A1 (en) | 2011-10-17 | 2012-10-12 | Through-wafer via device and method of manufacturing the same |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2014CN02550A true IN2014CN02550A (enrdf_load_stackoverflow) | 2015-08-07 |
Family
ID=47428773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN2550CHN2014 IN2014CN02550A (enrdf_load_stackoverflow) | 2011-10-17 | 2012-10-12 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9230908B2 (enrdf_load_stackoverflow) |
EP (1) | EP2745315A1 (enrdf_load_stackoverflow) |
CN (1) | CN103875068B (enrdf_load_stackoverflow) |
IN (1) | IN2014CN02550A (enrdf_load_stackoverflow) |
RU (1) | RU2603435C2 (enrdf_load_stackoverflow) |
WO (1) | WO2013057642A1 (enrdf_load_stackoverflow) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104023860B (zh) | 2011-12-20 | 2016-06-15 | 皇家飞利浦有限公司 | 超声换能器设备及制造所述超声换能器设备的方法 |
JP6495322B2 (ja) | 2014-03-31 | 2019-04-03 | コーニンクレッカ フィリップス エヌ ヴェKoninklijke Philips N.V. | Icダイ、超音波プローブ、超音波診断システム及び方法 |
JP6304445B2 (ja) * | 2015-03-16 | 2018-04-04 | 富士電機株式会社 | 半導体装置の製造方法 |
US11097942B2 (en) * | 2016-10-26 | 2021-08-24 | Analog Devices, Inc. | Through silicon via (TSV) formation in integrated circuits |
TW201947717A (zh) * | 2018-05-03 | 2019-12-16 | 美商蝴蝶網路公司 | 用於超音波晶片的垂直封裝及相關方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5381385A (en) | 1993-08-04 | 1995-01-10 | Hewlett-Packard Company | Electrical interconnect for multilayer transducer elements of a two-dimensional transducer array |
US5619476A (en) * | 1994-10-21 | 1997-04-08 | The Board Of Trustees Of The Leland Stanford Jr. Univ. | Electrostatic ultrasonic transducer |
US6430109B1 (en) | 1999-09-30 | 2002-08-06 | The Board Of Trustees Of The Leland Stanford Junior University | Array of capacitive micromachined ultrasonic transducer elements with through wafer via connections |
US6716737B2 (en) | 2002-07-29 | 2004-04-06 | Hewlett-Packard Development Company, L.P. | Method of forming a through-substrate interconnect |
US20040104454A1 (en) | 2002-10-10 | 2004-06-03 | Rohm Co., Ltd. | Semiconductor device and method of producing the same |
US6836020B2 (en) | 2003-01-22 | 2004-12-28 | The Board Of Trustees Of The Leland Stanford Junior University | Electrical through wafer interconnects |
US7257051B2 (en) * | 2003-03-06 | 2007-08-14 | General Electric Company | Integrated interface electronics for reconfigurable sensor array |
JP2005032769A (ja) * | 2003-07-07 | 2005-02-03 | Seiko Epson Corp | 多層配線の形成方法、配線基板の製造方法、デバイスの製造方法 |
WO2005088699A1 (en) * | 2004-03-10 | 2005-09-22 | Koninklijke Philips Electronics N.V. | Method of manufacturing an electronic device and a resulting device |
JP5275565B2 (ja) | 2004-06-07 | 2013-08-28 | オリンパス株式会社 | 静電容量型超音波トランスデューサ |
CN101573861B (zh) | 2005-05-18 | 2012-05-23 | 科隆科技公司 | 微机电换能器 |
US7622848B2 (en) | 2006-01-06 | 2009-11-24 | General Electric Company | Transducer assembly with z-axis interconnect |
EP2036124A2 (en) | 2006-06-26 | 2009-03-18 | Koninklijke Philips Electronics N.V. | Flip-chip interconnection with a small passivation layer opening |
RU2449418C2 (ru) | 2006-09-25 | 2012-04-27 | Конинклейке Филипс Электроникс Н.В. | Межсоединение по методу перевернутого кристалла через сквозные отверстия в микросхеме |
US20100168583A1 (en) * | 2006-11-03 | 2010-07-01 | Research Triangle Institute | Enhanced ultrasound imaging probes using flexure mode piezoelectric transducers |
US8110899B2 (en) * | 2006-12-20 | 2012-02-07 | Intel Corporation | Method for incorporating existing silicon die into 3D integrated stack |
US7843022B2 (en) | 2007-10-18 | 2010-11-30 | The Board Of Trustees Of The Leland Stanford Junior University | High-temperature electrostatic transducers and fabrication method |
US7781238B2 (en) | 2007-12-06 | 2010-08-24 | Robert Gideon Wodnicki | Methods of making and using integrated and testable sensor array |
US8062975B2 (en) * | 2009-04-16 | 2011-11-22 | Freescale Semiconductor, Inc. | Through substrate vias |
-
2012
- 2012-10-12 WO PCT/IB2012/055547 patent/WO2013057642A1/en active Application Filing
- 2012-10-12 CN CN201280050826.8A patent/CN103875068B/zh active Active
- 2012-10-12 US US14/346,824 patent/US9230908B2/en active Active
- 2012-10-12 EP EP12805761.9A patent/EP2745315A1/en not_active Withdrawn
- 2012-10-12 RU RU2014119923/28A patent/RU2603435C2/ru active
- 2012-10-12 IN IN2550CHN2014 patent/IN2014CN02550A/en unknown
Also Published As
Publication number | Publication date |
---|---|
WO2013057642A1 (en) | 2013-04-25 |
RU2603435C2 (ru) | 2016-11-27 |
RU2014119923A (ru) | 2015-11-27 |
EP2745315A1 (en) | 2014-06-25 |
CN103875068A (zh) | 2014-06-18 |
US20140293751A1 (en) | 2014-10-02 |
US9230908B2 (en) | 2016-01-05 |
CN103875068B (zh) | 2018-07-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP4235801A3 (en) | Silicon and silicon germanium nanowire structures | |
GB2494739B (en) | Trench isolation structure | |
GB2522816A (en) | Light emitting device reflective bank structure | |
EP4293707A3 (en) | Direct and sequential formation of monolayers of boron nitride and graphene on substrates | |
IN2015DN00551A (enrdf_load_stackoverflow) | ||
WO2013049042A3 (en) | Coalesced nanowire structures with interstitial voids and method for manufacturing the same | |
GB2497451A (en) | Gate insulator layer for electronic devices | |
WO2015130549A3 (en) | Selective conductive barrier layer formation | |
WO2010120704A3 (en) | Power semiconductor devices, methods, and structures with embedded dielectric layers containing permanent charges | |
EP3758379A3 (en) | Coding concept allowing efficient multi-view/layer coding | |
TW201614840A (en) | Semiconductor device and method for fabricating the same | |
WO2014204748A8 (en) | Optoelectronic integrated circuit | |
TW201612964A (en) | Semiconductor device and semiconductor device manufacturing method | |
IN2013DN02549A (enrdf_load_stackoverflow) | ||
WO2014051728A3 (en) | Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates | |
WO2012143784A3 (en) | Semiconductor device and manufacturing method thereof | |
IN2014CN02550A (enrdf_load_stackoverflow) | ||
SG194478A1 (en) | Out-of-plane spacer defined electrode | |
WO2012005851A3 (en) | Electrically conductive laminate structures, electrical interconnects, and method of forming electrical interconnects | |
GB201204670D0 (en) | Optoelectronic device | |
TW201613099A (en) | Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and method for designing silicon carbide semiconductor device | |
TW201612985A (en) | Semiconductor device structure and method for forming the same | |
TW201612958A (en) | Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers | |
IN2014MN01952A (enrdf_load_stackoverflow) | ||
WO2015050615A3 (en) | Enhanced gate dielectric for a field effect device with a trenched gate |