IN2013CH05121A - - Google Patents
Info
- Publication number
- IN2013CH05121A IN2013CH05121A IN5121CH2013A IN2013CH05121A IN 2013CH05121 A IN2013CH05121 A IN 2013CH05121A IN 5121CH2013 A IN5121CH2013 A IN 5121CH2013A IN 2013CH05121 A IN2013CH05121 A IN 2013CH05121A
- Authority
- IN
- India
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/105—Aspects related to pads, pins or terminals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN5121CH2013 IN2013CH05121A (de) | 2013-11-12 | 2013-11-12 | |
US14/191,097 US9684474B2 (en) | 2013-11-12 | 2014-02-26 | Single input/output cell with multiple bond pads and/or transmitters |
PCT/US2014/064064 WO2015073276A1 (en) | 2013-11-12 | 2014-11-05 | Memory controller selectively transmitting signals to memory dies via selected bond pads |
TW103139293A TWI613586B (zh) | 2013-11-12 | 2014-11-12 | 具有多個接合墊及/或發射器的單一輸入/輸出單元 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IN5121CH2013 IN2013CH05121A (de) | 2013-11-12 | 2013-11-12 |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2013CH05121A true IN2013CH05121A (de) | 2015-05-29 |
Family
ID=53044839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN5121CH2013 IN2013CH05121A (de) | 2013-11-12 | 2013-11-12 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9684474B2 (de) |
IN (1) | IN2013CH05121A (de) |
TW (1) | TWI613586B (de) |
WO (1) | WO2015073276A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9846192B2 (en) * | 2015-02-25 | 2017-12-19 | Nxp B.V. | Switched probe contact |
CN112655088A (zh) * | 2018-09-12 | 2021-04-13 | 华为技术有限公司 | 使用错误校正码和数据路径交织的ic晶粒到ic晶粒互连 |
US20220102333A1 (en) * | 2020-09-29 | 2022-03-31 | Alibaba Group Holding Limited | Configurable computer memory architecture |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5506499A (en) | 1995-06-05 | 1996-04-09 | Neomagic Corp. | Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad |
JP3588529B2 (ja) | 1997-01-28 | 2004-11-10 | 株式会社東芝 | 半導体装置およびその応用システム装置 |
JP3737333B2 (ja) | 2000-03-17 | 2006-01-18 | 沖電気工業株式会社 | 半導体装置 |
US6320757B1 (en) | 2000-07-12 | 2001-11-20 | Advanced Semiconductor Engineering, Inc. | Electronic package |
US6812726B1 (en) | 2002-11-27 | 2004-11-02 | Inapac Technology, Inc. | Entering test mode and accessing of a packaged semiconductor device |
US6472747B2 (en) | 2001-03-02 | 2002-10-29 | Qualcomm Incorporated | Mixed analog and digital integrated circuits |
JP2003059288A (ja) | 2001-08-09 | 2003-02-28 | Mitsubishi Electric Corp | 半導体装置 |
JP2003060151A (ja) | 2001-08-10 | 2003-02-28 | Fujitsu Ltd | 半導体装置 |
US6807109B2 (en) | 2001-12-05 | 2004-10-19 | Renesas Technology Corp. | Semiconductor device suitable for system in package |
JP2003319412A (ja) | 2002-04-19 | 2003-11-07 | Matsushita Electric Ind Co Ltd | 画像処理支援システム、画像処理装置及び画像表示装置 |
US6891275B2 (en) | 2002-07-26 | 2005-05-10 | Qualcomm Incorporated | Method for accommodating small minimum die in wire bonded area array packages |
US6960836B2 (en) * | 2003-09-30 | 2005-11-01 | Agere Systems, Inc. | Reinforced bond pad |
US7680966B1 (en) | 2004-06-29 | 2010-03-16 | National Semiconductor Corporation | Memory interface including generation of timing signals for memory operation |
US7598606B2 (en) | 2005-02-22 | 2009-10-06 | Stats Chippac Ltd. | Integrated circuit package system with die and package combination |
DE102005009163B4 (de) | 2005-02-25 | 2013-08-14 | Infineon Technologies Ag | Halbleiterbauteil mit einem Halbleiterchip, der Signalkontaktflächen und Versorgungskontaktflächen aufweist, sowie Verfahren zur Herstellung des Halbleiterbauteils |
JP4703300B2 (ja) | 2005-07-20 | 2011-06-15 | 富士通セミコンダクター株式会社 | 中継基板及び当該中継基板を備えた半導体装置 |
JP4595730B2 (ja) | 2005-07-28 | 2010-12-08 | セイコーエプソン株式会社 | 半導体装置及び電子機器 |
KR100690922B1 (ko) | 2005-08-26 | 2007-03-09 | 삼성전자주식회사 | 반도체 소자 패키지 |
US7643371B2 (en) | 2006-12-28 | 2010-01-05 | Spansion Llc | Address/data multiplexed device |
WO2010029480A2 (en) | 2008-09-09 | 2010-03-18 | Nxp B.V. | Memory controller |
US9142262B2 (en) * | 2009-10-23 | 2015-09-22 | Rambus Inc. | Stacked semiconductor device |
US8681546B2 (en) | 2011-02-22 | 2014-03-25 | Apple Inc. | Variable impedance control for memory devices |
KR20130036555A (ko) | 2011-10-04 | 2013-04-12 | 에스케이하이닉스 주식회사 | 전압 공급 회로, 반도체 메모리 장치 및 그것의 동작 방법 |
US8873282B2 (en) * | 2011-10-18 | 2014-10-28 | Micron Technology, Inc. | Interfaces and die packages, and appartuses including the same |
US8780600B2 (en) * | 2011-12-07 | 2014-07-15 | Apple Inc. | Systems and methods for stacked semiconductor memory devices |
JP2013187594A (ja) | 2012-03-06 | 2013-09-19 | Toshiba Corp | インターフェース回路 |
-
2013
- 2013-11-12 IN IN5121CH2013 patent/IN2013CH05121A/en unknown
-
2014
- 2014-02-26 US US14/191,097 patent/US9684474B2/en active Active
- 2014-11-05 WO PCT/US2014/064064 patent/WO2015073276A1/en active Application Filing
- 2014-11-12 TW TW103139293A patent/TWI613586B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US20150134918A1 (en) | 2015-05-14 |
TWI613586B (zh) | 2018-02-01 |
TW201531928A (zh) | 2015-08-16 |
US9684474B2 (en) | 2017-06-20 |
WO2015073276A1 (en) | 2015-05-21 |