IN2012DN03050A - - Google Patents

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Publication number
IN2012DN03050A
IN2012DN03050A IN3050DEN2012A IN2012DN03050A IN 2012DN03050 A IN2012DN03050 A IN 2012DN03050A IN 3050DEN2012 A IN3050DEN2012 A IN 3050DEN2012A IN 2012DN03050 A IN2012DN03050 A IN 2012DN03050A
Authority
IN
India
Prior art keywords
transaction
requests
barrier
request
interconnect
Prior art date
Application number
Inventor
Andrew Riocreux Peter
James Mathewson Bruce
William Laycock Christopher
Roy Grisenth Waite Richard
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IN2012DN03050A publication Critical patent/IN2012DN03050A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Information Transfer Systems (AREA)
  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Circuit For Audible Band Transducer (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Small-Scale Networks (AREA)
  • Computer And Data Communications (AREA)
  • Measuring Volume Flow (AREA)
  • Logic Circuits (AREA)

Abstract

An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request query­ing progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a hairier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronous request.
IN3050DEN2012 2009-10-13 2010-10-12 IN2012DN03050A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
GB0917946A GB2474446A (en) 2009-10-13 2009-10-13 Barrier requests to maintain transaction order in an interconnect with multiple paths
GB1007363A GB2474533A (en) 2009-10-13 2010-04-30 Barrier requests to maintain transaction order in an interconnect with multiple paths
GB201007342A GB2474532B8 (en) 2009-10-13 2010-04-30 Barrier transactions in interconnects
GB1016482A GB2474552A (en) 2009-10-13 2010-10-01 Interconnect that uses barrier requests to maintain the order of requests with respect to data store management requests
PCT/GB2010/051715 WO2011045595A1 (en) 2009-10-13 2010-10-12 Synchronising activities of various components in a distributed system

Publications (1)

Publication Number Publication Date
IN2012DN03050A true IN2012DN03050A (en) 2015-07-31

Family

ID=41402983

Family Applications (3)

Application Number Title Priority Date Filing Date
IN2853DEN2012 IN2012DN02853A (en) 2009-10-13 2010-09-28
IN2792DEN2012 IN2012DN02792A (en) 2009-10-13 2010-09-28
IN3050DEN2012 IN2012DN03050A (en) 2009-10-13 2010-10-12

Family Applications Before (2)

Application Number Title Priority Date Filing Date
IN2853DEN2012 IN2012DN02853A (en) 2009-10-13 2010-09-28
IN2792DEN2012 IN2012DN02792A (en) 2009-10-13 2010-09-28

Country Status (11)

Country Link
US (6) US8856408B2 (en)
EP (3) EP2488952B1 (en)
JP (6) JP5650749B2 (en)
KR (3) KR20120095876A (en)
CN (4) CN102713874A (en)
GB (4) GB2474446A (en)
IL (3) IL218703A0 (en)
IN (3) IN2012DN02853A (en)
MY (2) MY155614A (en)
TW (3) TW201120638A (en)
WO (3) WO2011045555A1 (en)

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Also Published As

Publication number Publication date
JP2013507709A (en) 2013-03-04
JP5650749B2 (en) 2015-01-07
GB201016482D0 (en) 2010-11-17
KR20120095876A (en) 2012-08-29
JP6141905B2 (en) 2017-06-07
JP2013507708A (en) 2013-03-04
EP2488951B1 (en) 2015-01-07
JP2015057701A (en) 2015-03-26
CN102576341B (en) 2015-05-27
US8856408B2 (en) 2014-10-07
US20110087809A1 (en) 2011-04-14
JP2013507710A (en) 2013-03-04
GB2474446A (en) 2011-04-20
EP2488951A1 (en) 2012-08-22
GB2474552A (en) 2011-04-20
US8607006B2 (en) 2013-12-10
GB201007342D0 (en) 2010-06-16
TWI533133B (en) 2016-05-11
MY155614A (en) 2015-11-13
IN2012DN02792A (en) 2015-07-24
JP5865976B2 (en) 2016-02-17
US20110087819A1 (en) 2011-04-14
CN102713874A (en) 2012-10-03
KR20120095872A (en) 2012-08-29
GB2474533A (en) 2011-04-20
KR101734045B1 (en) 2017-05-24
GB2474532B (en) 2014-06-11
CN102576341A (en) 2012-07-11
US8732400B2 (en) 2014-05-20
US8601167B2 (en) 2013-12-03
GB2474532A8 (en) 2014-08-20
CN102063391A (en) 2011-05-18
WO2011045595A1 (en) 2011-04-21
MY154614A (en) 2015-07-15
IL218704A0 (en) 2012-05-31
WO2011045555A1 (en) 2011-04-21
IL218703A0 (en) 2012-05-31
EP2488954B1 (en) 2015-11-25
CN102792290A (en) 2012-11-21
IL218704A (en) 2016-03-31
US20110125944A1 (en) 2011-05-26
JP2011138481A (en) 2011-07-14
JP2015167036A (en) 2015-09-24
US9477623B2 (en) 2016-10-25
WO2011045556A2 (en) 2011-04-21
US20110119448A1 (en) 2011-05-19
WO2011045556A3 (en) 2011-06-16
EP2488952B1 (en) 2015-05-06
US20110093557A1 (en) 2011-04-21
TW201120638A (en) 2011-06-16
GB2474532A (en) 2011-04-20
CN102792290B (en) 2015-08-05
TW201128398A (en) 2011-08-16
US20140040516A1 (en) 2014-02-06
IL218887A (en) 2015-10-29
GB2474532B8 (en) 2014-08-20
IN2012DN02853A (en) 2015-07-24
GB0917946D0 (en) 2009-11-25
US8463966B2 (en) 2013-06-11
IL218887A0 (en) 2012-06-28
GB201007363D0 (en) 2010-06-16
EP2488952A2 (en) 2012-08-22
KR20120093276A (en) 2012-08-22
KR101734044B1 (en) 2017-05-11
TWI474193B (en) 2015-02-21
TW201120656A (en) 2011-06-16
EP2488954A1 (en) 2012-08-22

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