IN2012DN03050A - - Google Patents
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- Publication number
- IN2012DN03050A IN2012DN03050A IN3050DEN2012A IN2012DN03050A IN 2012DN03050 A IN2012DN03050 A IN 2012DN03050A IN 3050DEN2012 A IN3050DEN2012 A IN 3050DEN2012A IN 2012DN03050 A IN2012DN03050 A IN 2012DN03050A
- Authority
- IN
- India
- Prior art keywords
- transaction
- requests
- barrier
- request
- interconnect
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9084—Reactions to storage capacity overflow
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
- Information Transfer Systems (AREA)
- Storage Device Security (AREA)
- Debugging And Monitoring (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Circuit For Audible Band Transducer (AREA)
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
- Small-Scale Networks (AREA)
- Computer And Data Communications (AREA)
- Measuring Volume Flow (AREA)
- Logic Circuits (AREA)
Abstract
An initiator device for issuing transaction requests to a recipient device via an interconnect is disclosed. The initiator device comprises: at least one port for receiving requests from and issuing requests to said interconnect; a barrier generator for generating barrier transaction requests, the barrier transaction requests indicating to the interconnect that an ordering of at least some transaction requests within a stream of transaction requests passing through the interconnect should be maintained by not allowing reordering of at least some of the transaction requests that occur before the barrier transaction request in the stream of transaction requests with respect to the barrier transaction request; wherein in response to receipt of a synchronise request querying progress of at least a subset of transaction requests, the initiator device is responsive to action any pending transaction requests within the at least a subset of transaction request and to generate a hairier transaction request at the barrier generator and to issue the barrier transaction request to the interconnect via the at least one port, and in response to receiving a response to the barrier transaction request to issue an acknowledge signal as a response to the synchronous request.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0917946A GB2474446A (en) | 2009-10-13 | 2009-10-13 | Barrier requests to maintain transaction order in an interconnect with multiple paths |
GB1007363A GB2474533A (en) | 2009-10-13 | 2010-04-30 | Barrier requests to maintain transaction order in an interconnect with multiple paths |
GB201007342A GB2474532B8 (en) | 2009-10-13 | 2010-04-30 | Barrier transactions in interconnects |
GB1016482A GB2474552A (en) | 2009-10-13 | 2010-10-01 | Interconnect that uses barrier requests to maintain the order of requests with respect to data store management requests |
PCT/GB2010/051715 WO2011045595A1 (en) | 2009-10-13 | 2010-10-12 | Synchronising activities of various components in a distributed system |
Publications (1)
Publication Number | Publication Date |
---|---|
IN2012DN03050A true IN2012DN03050A (en) | 2015-07-31 |
Family
ID=41402983
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN2853DEN2012 IN2012DN02853A (en) | 2009-10-13 | 2010-09-28 | |
IN2792DEN2012 IN2012DN02792A (en) | 2009-10-13 | 2010-09-28 | |
IN3050DEN2012 IN2012DN03050A (en) | 2009-10-13 | 2010-10-12 |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IN2853DEN2012 IN2012DN02853A (en) | 2009-10-13 | 2010-09-28 | |
IN2792DEN2012 IN2012DN02792A (en) | 2009-10-13 | 2010-09-28 |
Country Status (11)
Country | Link |
---|---|
US (6) | US8856408B2 (en) |
EP (3) | EP2488952B1 (en) |
JP (6) | JP5650749B2 (en) |
KR (3) | KR20120095876A (en) |
CN (4) | CN102713874A (en) |
GB (4) | GB2474446A (en) |
IL (3) | IL218703A0 (en) |
IN (3) | IN2012DN02853A (en) |
MY (2) | MY155614A (en) |
TW (3) | TW201120638A (en) |
WO (3) | WO2011045555A1 (en) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2474446A (en) * | 2009-10-13 | 2011-04-20 | Advanced Risc Mach Ltd | Barrier requests to maintain transaction order in an interconnect with multiple paths |
KR101699781B1 (en) * | 2010-10-19 | 2017-01-26 | 삼성전자주식회사 | System-on-chip and data arbitration method thereof |
US8589638B2 (en) * | 2011-07-19 | 2013-11-19 | Arm Limited | Terminating barriers in streams of access requests to a data store while maintaining data consistency |
GB2493405B (en) * | 2011-08-03 | 2017-04-05 | Advanced Risc Mach Ltd | Debug barrier transactions |
US8463960B2 (en) * | 2011-08-08 | 2013-06-11 | Arm Limited | Synchronisation of data processing systems |
US9473424B2 (en) * | 2011-09-19 | 2016-10-18 | Fujitsu Limited | Address table flushing in distributed switching systems |
US20130339680A1 (en) | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Nontransactional store instruction |
US10437602B2 (en) | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
US8682877B2 (en) | 2012-06-15 | 2014-03-25 | International Business Machines Corporation | Constrained transaction execution |
US9436477B2 (en) | 2012-06-15 | 2016-09-06 | International Business Machines Corporation | Transaction abort instruction |
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US8688661B2 (en) | 2012-06-15 | 2014-04-01 | International Business Machines Corporation | Transactional processing |
US9772854B2 (en) | 2012-06-15 | 2017-09-26 | International Business Machines Corporation | Selectively controlling instruction execution in transactional processing |
US9361115B2 (en) | 2012-06-15 | 2016-06-07 | International Business Machines Corporation | Saving/restoring selected registers in transactional processing |
US9336046B2 (en) | 2012-06-15 | 2016-05-10 | International Business Machines Corporation | Transaction abort processing |
US9317460B2 (en) | 2012-06-15 | 2016-04-19 | International Business Machines Corporation | Program event recording within a transactional environment |
US9367323B2 (en) | 2012-06-15 | 2016-06-14 | International Business Machines Corporation | Processor assist facility |
US9448796B2 (en) | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
US9442737B2 (en) | 2012-06-15 | 2016-09-13 | International Business Machines Corporation | Restricting processing within a processor to facilitate transaction completion |
US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US20140032854A1 (en) * | 2012-07-30 | 2014-01-30 | Futurewei Technologies, Inc. | Coherence Management Using a Coherent Domain Table |
US9304954B2 (en) * | 2012-10-24 | 2016-04-05 | Texas Instruments Incorporated | Multi processor bridge with mixed Endian mode support |
WO2015008251A2 (en) * | 2013-07-18 | 2015-01-22 | Synaptic Laboratories Limited | Computing architecture with peripherals |
GB2522057B (en) * | 2014-01-13 | 2021-02-24 | Advanced Risc Mach Ltd | A data processing system and method for handling multiple transactions |
US20150317158A1 (en) | 2014-04-03 | 2015-11-05 | Applied Micro Circuits Corporation | Implementation of load acquire/store release instructions using load/store operation with dmb operation |
GB2533972B (en) * | 2015-01-12 | 2021-08-18 | Advanced Risc Mach Ltd | An interconnect and method of operation of an interconnect |
US20160246721A1 (en) * | 2015-02-19 | 2016-08-25 | Qualcomm Incorporated | Role based cache coherence bus traffic control |
US10078589B2 (en) * | 2015-04-30 | 2018-09-18 | Arm Limited | Enforcing data protection in an interconnect |
US9946492B2 (en) | 2015-10-30 | 2018-04-17 | Arm Limited | Controlling persistent writes to non-volatile memory based on persist buffer data and a persist barrier within a sequence of program instructions |
US10067713B2 (en) | 2015-11-05 | 2018-09-04 | International Business Machines Corporation | Efficient enforcement of barriers with respect to memory move sequences |
US10152322B2 (en) | 2015-11-05 | 2018-12-11 | International Business Machines Corporation | Memory move instruction sequence including a stream of copy-type and paste-type instructions |
US10241945B2 (en) | 2015-11-05 | 2019-03-26 | International Business Machines Corporation | Memory move supporting speculative acquisition of source and destination data granules including copy-type and paste-type instructions |
US10346164B2 (en) | 2015-11-05 | 2019-07-09 | International Business Machines Corporation | Memory move instruction sequence targeting an accelerator switchboard |
US10140052B2 (en) * | 2015-11-05 | 2018-11-27 | International Business Machines Corporation | Memory access in a data processing system utilizing copy and paste instructions |
US10126952B2 (en) * | 2015-11-05 | 2018-11-13 | International Business Machines Corporation | Memory move instruction sequence targeting a memory-mapped device |
US9996298B2 (en) | 2015-11-05 | 2018-06-12 | International Business Machines Corporation | Memory move instruction sequence enabling software control |
US10042580B2 (en) | 2015-11-05 | 2018-08-07 | International Business Machines Corporation | Speculatively performing memory move requests with respect to a barrier |
GB2548387B (en) * | 2016-03-17 | 2020-04-01 | Advanced Risc Mach Ltd | An apparatus and method for filtering transactions |
US10956205B2 (en) * | 2017-01-03 | 2021-03-23 | Arm Limited | Data processing |
JP6944107B2 (en) * | 2017-07-11 | 2021-10-06 | 富士通株式会社 | Information processing equipment, information processing systems and programs |
KR102262209B1 (en) * | 2018-02-09 | 2021-06-09 | 한양대학교 산학협력단 | Method and apparatus for sending barrier command using dummy io request |
JP7207133B2 (en) * | 2019-04-23 | 2023-01-18 | 富士通株式会社 | Information processing device, synchronization device, and control method for information processing device |
US11593281B2 (en) * | 2019-05-08 | 2023-02-28 | Hewlett Packard Enterprise Development Lp | Device supporting ordered and unordered transaction classes |
GB2585914B (en) * | 2019-07-23 | 2022-08-10 | Advanced Risc Mach Ltd | Epoch-based determination of completion of barrier termination command |
US11055130B2 (en) | 2019-09-15 | 2021-07-06 | Mellanox Technologies, Ltd. | Task completion system |
US11822973B2 (en) | 2019-09-16 | 2023-11-21 | Mellanox Technologies, Ltd. | Operation fencing system |
US11372585B2 (en) | 2020-05-05 | 2022-06-28 | Micron Technology, Inc. | Asynchronous process topology in a memory device |
CN114155709B (en) * | 2021-11-23 | 2022-09-23 | 北京安融畅信息技术有限公司 | Identification method for sharp-bent road section and potential safety hazard investigation method |
US11876713B1 (en) * | 2023-03-13 | 2024-01-16 | Intuit Inc. | Client side backoff filter for rate limiting |
US20250258778A1 (en) * | 2024-02-08 | 2025-08-14 | Nvidia Corporation | Ordered store operations in a multiprocessor system |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55147744A (en) * | 1979-05-07 | 1980-11-17 | Hitachi Ltd | Memory controlling unit |
US4833468A (en) * | 1987-10-14 | 1989-05-23 | Unisys Corporation | Layered network |
US5224214A (en) * | 1990-04-12 | 1993-06-29 | Digital Equipment Corp. | BuIffet for gathering write requests and resolving read conflicts by matching read and write requests |
US5274782A (en) * | 1990-08-27 | 1993-12-28 | International Business Machines Corporation | Method and apparatus for dynamic detection and routing of non-uniform traffic in parallel buffered multistage interconnection networks |
US5459842A (en) * | 1992-06-26 | 1995-10-17 | International Business Machines Corporation | System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory |
US5608870A (en) * | 1992-11-06 | 1997-03-04 | The President And Fellows Of Harvard College | System for combining a plurality of requests referencing a common target address into a single combined request having a single reference to the target address |
US5689689A (en) * | 1992-12-17 | 1997-11-18 | Tandem Computers Incorporated | Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal |
US5893165A (en) * | 1996-07-01 | 1999-04-06 | Sun Microsystems, Inc. | System and method for parallel execution of memory transactions using multiple memory models, including SSO, TSO, PSO and RMO |
JP3636871B2 (en) * | 1997-09-16 | 2005-04-06 | 株式会社日立製作所 | Parallel processor system |
US6038646A (en) * | 1998-01-23 | 2000-03-14 | Sun Microsystems, Inc. | Method and apparatus for enforcing ordered execution of reads and writes across a memory interface |
JP3858492B2 (en) * | 1998-12-28 | 2006-12-13 | 株式会社日立製作所 | Multiprocessor system |
JP3889195B2 (en) * | 1999-02-03 | 2007-03-07 | 株式会社東芝 | Image processing apparatus, image processing system, and image processing method |
US6430646B1 (en) * | 1999-08-18 | 2002-08-06 | Ati International Srl | Method and apparatus for interfacing a processor with a bus |
US6748518B1 (en) * | 2000-06-06 | 2004-06-08 | International Business Machines Corporation | Multi-level multiprocessor speculation mechanism |
US6647453B1 (en) * | 2000-08-31 | 2003-11-11 | Hewlett-Packard Development Company, L.P. | System and method for providing forward progress and avoiding starvation and livelock in a multiprocessor computer system |
US6795878B2 (en) * | 2000-12-11 | 2004-09-21 | International Business Machines Corporation | Verifying cumulative ordering of memory instructions |
US6967926B1 (en) * | 2000-12-31 | 2005-11-22 | Cisco Technology, Inc. | Method and apparatus for using barrier phases to limit packet disorder in a packet switching system |
US7031338B2 (en) * | 2001-08-27 | 2006-04-18 | Hewlett-Packard Development Company, L.P. | System and method for the consolidation of data packets |
US7051145B2 (en) * | 2001-12-10 | 2006-05-23 | Emulex Design & Manufacturing Corporation | Tracking deferred data transfers on a system-interconnect bus |
US20040133769A1 (en) * | 2002-12-24 | 2004-07-08 | Shailender Chaudhry | Generating prefetches by speculatively executing code through hardware scout threading |
TW200502805A (en) * | 2003-05-09 | 2005-01-16 | Incentia Design Systems Corp | Timing based scan chain implementation in an IC design |
US7552317B2 (en) * | 2004-05-04 | 2009-06-23 | Sun Microsystems, Inc. | Methods and systems for grouping instructions using memory barrier instructions |
US20050289306A1 (en) * | 2004-06-28 | 2005-12-29 | Sridhar Muthrasanallur | Memory read requests passing memory writes |
JP4463097B2 (en) * | 2004-12-24 | 2010-05-12 | エヌイーシーコンピュータテクノ株式会社 | Data transfer system, data transfer method, and crossbar LSI |
US7631130B2 (en) * | 2005-02-04 | 2009-12-08 | Mips Technologies, Inc | Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor |
US7500045B2 (en) * | 2005-03-23 | 2009-03-03 | Qualcomm Incorporated | Minimizing memory barriers when enforcing strongly-ordered requests in a weakly-ordered processing system |
US9026744B2 (en) * | 2005-03-23 | 2015-05-05 | Qualcomm Incorporated | Enforcing strongly-ordered requests in a weakly-ordered processing |
CN100524266C (en) * | 2005-07-11 | 2009-08-05 | 辉达公司 | Method and equipment for transmitting data transmission request by packets in a bus |
US7500039B2 (en) * | 2005-08-19 | 2009-03-03 | International Business Machines Corporation | Method for communicating with a processor event facility |
US7917676B2 (en) * | 2006-03-10 | 2011-03-29 | Qualcomm, Incorporated | Efficient execution of memory barrier bus commands with order constrained memory accesses |
US7610458B2 (en) * | 2006-04-25 | 2009-10-27 | International Business Machines Corporation | Data processing system, processor and method of data processing that support memory access according to diverse memory models |
US7657680B2 (en) * | 2006-06-21 | 2010-02-02 | Finisar Corporation | Multiple bus interface control using a single controller |
US7908406B2 (en) * | 2006-06-21 | 2011-03-15 | Finisar Corporation | Interface architecture for facilitating communication regardless of protocol |
US7783817B2 (en) * | 2006-08-31 | 2010-08-24 | Qualcomm Incorporated | Method and apparatus for conditional broadcast of barrier operations |
US7603490B2 (en) * | 2007-01-10 | 2009-10-13 | International Business Machines Corporation | Barrier and interrupt mechanism for high latency and out of order DMA device |
US7581201B2 (en) * | 2007-02-28 | 2009-08-25 | International Business Machines Corporation | System and method for sign-off timing closure of a VLSI chip |
US7984202B2 (en) * | 2007-06-01 | 2011-07-19 | Qualcomm Incorporated | Device directed memory barriers |
US8006047B2 (en) * | 2007-06-27 | 2011-08-23 | Hitachi Global Storage Technologies Netherlands B.V. | Storage device with write barrier sensitive write commands and write barrier insensitive commands |
JP5146454B2 (en) | 2007-08-22 | 2013-02-20 | 日本電気株式会社 | Information processing apparatus and information processing method |
US8612950B2 (en) * | 2008-06-19 | 2013-12-17 | Intel Corporation | Dynamic optimization for removal of strong atomicity barriers |
US8352682B2 (en) * | 2009-05-26 | 2013-01-08 | Qualcomm Incorporated | Methods and apparatus for issuing memory barrier commands in a weakly ordered storage system |
GB2474446A (en) * | 2009-10-13 | 2011-04-20 | Advanced Risc Mach Ltd | Barrier requests to maintain transaction order in an interconnect with multiple paths |
US8589638B2 (en) * | 2011-07-19 | 2013-11-19 | Arm Limited | Terminating barriers in streams of access requests to a data store while maintaining data consistency |
-
2009
- 2009-10-13 GB GB0917946A patent/GB2474446A/en not_active Withdrawn
-
2010
- 2010-04-30 GB GB1007363A patent/GB2474533A/en not_active Withdrawn
- 2010-04-30 GB GB201007342A patent/GB2474532B8/en active Active
- 2010-09-28 EP EP10782345.2A patent/EP2488952B1/en active Active
- 2010-09-28 WO PCT/GB2010/001819 patent/WO2011045555A1/en active Application Filing
- 2010-09-28 KR KR1020127010025A patent/KR20120095876A/en not_active Withdrawn
- 2010-09-28 MY MYPI2012001273A patent/MY155614A/en unknown
- 2010-09-28 JP JP2012533685A patent/JP5650749B2/en active Active
- 2010-09-28 IN IN2853DEN2012 patent/IN2012DN02853A/en unknown
- 2010-09-28 IN IN2792DEN2012 patent/IN2012DN02792A/en unknown
- 2010-09-28 CN CN2010800469669A patent/CN102713874A/en active Pending
- 2010-09-28 WO PCT/GB2010/001822 patent/WO2011045556A2/en active Application Filing
- 2010-09-28 EP EP10763398.4A patent/EP2488951B1/en not_active Not-in-force
- 2010-09-28 CN CN201080046421.8A patent/CN102792290B/en active Active
- 2010-09-28 JP JP2012533684A patent/JP2013507708A/en active Pending
- 2010-09-28 KR KR1020127009810A patent/KR101734045B1/en active Active
- 2010-10-01 TW TW099133594A patent/TW201120638A/en unknown
- 2010-10-01 GB GB1016482A patent/GB2474552A/en not_active Withdrawn
- 2010-10-01 TW TW99133596A patent/TWI474193B/en active
- 2010-10-05 US US12/923,723 patent/US8856408B2/en active Active
- 2010-10-05 US US12/923,725 patent/US8732400B2/en active Active
- 2010-10-05 US US12/923,727 patent/US8607006B2/en active Active
- 2010-10-12 JP JP2012533691A patent/JP2013507710A/en active Pending
- 2010-10-12 IN IN3050DEN2012 patent/IN2012DN03050A/en unknown
- 2010-10-12 KR KR1020127011968A patent/KR101734044B1/en active Active
- 2010-10-12 MY MYPI2012001398A patent/MY154614A/en unknown
- 2010-10-12 WO PCT/GB2010/051715 patent/WO2011045595A1/en active Application Filing
- 2010-10-12 CN CN201080046965.4A patent/CN102576341B/en active Active
- 2010-10-12 EP EP10775868.2A patent/EP2488954B1/en active Active
- 2010-10-12 JP JP2010229679A patent/JP2011138481A/en active Pending
- 2010-10-13 CN CN2010106093158A patent/CN102063391A/en active Pending
- 2010-10-13 US US12/923,907 patent/US8601167B2/en not_active Expired - Fee Related
- 2010-10-13 US US12/923,906 patent/US8463966B2/en active Active
- 2010-10-13 TW TW099134937A patent/TWI533133B/en active
-
2012
- 2012-03-18 IL IL218703A patent/IL218703A0/en unknown
- 2012-03-18 IL IL218704A patent/IL218704A/en active IP Right Grant
- 2012-03-27 IL IL218887A patent/IL218887A/en active IP Right Grant
-
2013
- 2013-08-06 US US13/960,128 patent/US9477623B2/en active Active
-
2014
- 2014-09-12 JP JP2014186541A patent/JP5865976B2/en not_active Expired - Fee Related
-
2015
- 2015-05-12 JP JP2015097254A patent/JP6141905B2/en active Active
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