IN2012DN02792A - - Google Patents

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Publication number
IN2012DN02792A
IN2012DN02792A IN2792DEN2012A IN2012DN02792A IN 2012DN02792 A IN2012DN02792 A IN 2012DN02792A IN 2792DEN2012 A IN2792DEN2012 A IN 2792DEN2012A IN 2012DN02792 A IN2012DN02792 A IN 2012DN02792A
Authority
IN
India
Prior art keywords
transaction requests
transaction
requests
barrier
stream
Prior art date
Application number
Inventor
Andrew Riocreux Peter
James Mathewson Bruce
William Laycock Christopher
Roy Grisenthwaite Richard
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IN2012DN02792A publication Critical patent/IN2012DN02792A/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9084—Reactions to storage capacity overflow

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Circuit For Audible Band Transducer (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Storage Device Security (AREA)
  • Measuring Volume Flow (AREA)
  • Small-Scale Networks (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Logic Circuits (AREA)
  • Computer And Data Communications (AREA)

Abstract

Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for out-putting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests be¬tween said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said barrier transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.
IN2792DEN2012 2009-10-13 2010-09-28 IN2012DN02792A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0917946A GB2474446A (en) 2009-10-13 2009-10-13 Barrier requests to maintain transaction order in an interconnect with multiple paths
GB201007342A GB2474532B8 (en) 2009-10-13 2010-04-30 Barrier transactions in interconnects
PCT/GB2010/001822 WO2011045556A2 (en) 2009-10-13 2010-09-28 Barrier transactions in interconnects

Publications (1)

Publication Number Publication Date
IN2012DN02792A true IN2012DN02792A (en) 2015-07-24

Family

ID=41402983

Family Applications (3)

Application Number Title Priority Date Filing Date
IN2853DEN2012 IN2012DN02853A (en) 2009-10-13 2010-09-28
IN2792DEN2012 IN2012DN02792A (en) 2009-10-13 2010-09-28
IN3050DEN2012 IN2012DN03050A (en) 2009-10-13 2010-10-12

Family Applications Before (1)

Application Number Title Priority Date Filing Date
IN2853DEN2012 IN2012DN02853A (en) 2009-10-13 2010-09-28

Family Applications After (1)

Application Number Title Priority Date Filing Date
IN3050DEN2012 IN2012DN03050A (en) 2009-10-13 2010-10-12

Country Status (11)

Country Link
US (6) US8607006B2 (en)
EP (3) EP2488951B1 (en)
JP (6) JP2013507708A (en)
KR (3) KR101734045B1 (en)
CN (4) CN102792290B (en)
GB (4) GB2474446A (en)
IL (3) IL218703A0 (en)
IN (3) IN2012DN02853A (en)
MY (2) MY155614A (en)
TW (3) TW201120638A (en)
WO (3) WO2011045555A1 (en)

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Also Published As

Publication number Publication date
GB0917946D0 (en) 2009-11-25
US20110093557A1 (en) 2011-04-21
US8463966B2 (en) 2013-06-11
IN2012DN03050A (en) 2015-07-31
GB201007342D0 (en) 2010-06-16
EP2488952A2 (en) 2012-08-22
JP2015167036A (en) 2015-09-24
EP2488952B1 (en) 2015-05-06
CN102792290B (en) 2015-08-05
TWI533133B (en) 2016-05-11
TW201128398A (en) 2011-08-16
GB2474446A (en) 2011-04-20
JP5650749B2 (en) 2015-01-07
CN102063391A (en) 2011-05-18
GB2474552A (en) 2011-04-20
KR20120095876A (en) 2012-08-29
JP2013507709A (en) 2013-03-04
US8601167B2 (en) 2013-12-03
GB2474532B8 (en) 2014-08-20
JP2011138481A (en) 2011-07-14
US20140040516A1 (en) 2014-02-06
WO2011045595A1 (en) 2011-04-21
JP2015057701A (en) 2015-03-26
GB201007363D0 (en) 2010-06-16
CN102576341A (en) 2012-07-11
KR20120095872A (en) 2012-08-29
JP6141905B2 (en) 2017-06-07
IN2012DN02853A (en) 2015-07-24
GB2474532A (en) 2011-04-20
GB201016482D0 (en) 2010-11-17
KR20120093276A (en) 2012-08-22
IL218704A (en) 2016-03-31
US8856408B2 (en) 2014-10-07
CN102792290A (en) 2012-11-21
EP2488951A1 (en) 2012-08-22
US20110087819A1 (en) 2011-04-14
JP2013507710A (en) 2013-03-04
KR101734044B1 (en) 2017-05-11
TW201120656A (en) 2011-06-16
US20110087809A1 (en) 2011-04-14
EP2488954B1 (en) 2015-11-25
CN102576341B (en) 2015-05-27
IL218887A0 (en) 2012-06-28
IL218703A0 (en) 2012-05-31
WO2011045556A3 (en) 2011-06-16
GB2474533A (en) 2011-04-20
US20110125944A1 (en) 2011-05-26
EP2488954A1 (en) 2012-08-22
IL218704A0 (en) 2012-05-31
WO2011045555A1 (en) 2011-04-21
WO2011045556A2 (en) 2011-04-21
JP5865976B2 (en) 2016-02-17
KR101734045B1 (en) 2017-05-24
US8607006B2 (en) 2013-12-10
JP2013507708A (en) 2013-03-04
US20110119448A1 (en) 2011-05-19
CN102713874A (en) 2012-10-03
MY154614A (en) 2015-07-15
IL218887A (en) 2015-10-29
US9477623B2 (en) 2016-10-25
TWI474193B (en) 2015-02-21
US8732400B2 (en) 2014-05-20
EP2488951B1 (en) 2015-01-07
GB2474532B (en) 2014-06-11
GB2474532A8 (en) 2014-08-20
MY155614A (en) 2015-11-13
TW201120638A (en) 2011-06-16

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