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WO2011045556A3 - Barrier transactions in interconnects - Google Patents

Barrier transactions in interconnects Download PDF

Info

Publication number
WO2011045556A3
WO2011045556A3 PCT/GB2010/001822 GB2010001822W WO2011045556A3 WO 2011045556 A3 WO2011045556 A3 WO 2011045556A3 GB 2010001822 W GB2010001822 W GB 2010001822W WO 2011045556 A3 WO2011045556 A3 WO 2011045556A3
Authority
WO
WIPO (PCT)
Prior art keywords
transaction requests
transaction
requests
barrier
stream
Prior art date
Application number
PCT/GB2010/001822
Other languages
French (fr)
Other versions
WO2011045556A2 (en
Inventor
Peter Andrew Riocreux
Bruce James Mathewson
Christopher William Laycock
Richard Roy Grisenthwaite
Original Assignee
Arm Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB0917946.6 priority Critical
Priority to GB0917946A priority patent/GB2474446A/en
Priority to GB201007342A priority patent/GB2474532B8/en
Priority to GB1007342.7 priority
Application filed by Arm Limited filed Critical Arm Limited
Publication of WO2011045556A2 publication Critical patent/WO2011045556A2/en
Publication of WO2011045556A3 publication Critical patent/WO2011045556A3/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines

Abstract

Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said barrier transaction request in said stream of transaction requests; wherein said barrier transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.
PCT/GB2010/001822 2009-10-13 2010-09-28 Barrier transactions in interconnects WO2011045556A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0917946.6 2009-10-13
GB0917946A GB2474446A (en) 2009-10-13 2009-10-13 Barrier requests to maintain transaction order in an interconnect with multiple paths
GB201007342A GB2474532B8 (en) 2009-10-13 2010-04-30 Barrier transactions in interconnects
GB1007342.7 2010-04-30

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
KR1020127009810A KR101734045B1 (en) 2009-10-13 2010-09-28 Barrier transactions in interconnects
JP2012533685A JP5650749B2 (en) 2009-10-13 2010-09-28 Barrier transaction in the Interconnect
EP20100782345 EP2488952B1 (en) 2009-10-13 2010-09-28 Barrier transactions in interconnects
CN201080046421.8A CN102792290B (en) 2009-10-13 2010-09-28 Interconnection barrier transaction
IL218704A IL218704A (en) 2009-10-13 2012-03-18 Barrier transactions in interconnects
IN2792/DELNP/2012A IN2012DN02792A (en) 2009-10-13 2012-04-02 "barrier transaction in interconnects"

Publications (2)

Publication Number Publication Date
WO2011045556A2 WO2011045556A2 (en) 2011-04-21
WO2011045556A3 true WO2011045556A3 (en) 2011-06-16

Family

ID=41402983

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/GB2010/001819 WO2011045555A1 (en) 2009-10-13 2010-09-28 Reduced latency barrier transaction requests in interconnects
PCT/GB2010/001822 WO2011045556A2 (en) 2009-10-13 2010-09-28 Barrier transactions in interconnects
PCT/GB2010/051715 WO2011045595A1 (en) 2009-10-13 2010-10-12 Synchronising activities of various components in a distributed system

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/GB2010/001819 WO2011045555A1 (en) 2009-10-13 2010-09-28 Reduced latency barrier transaction requests in interconnects

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/GB2010/051715 WO2011045595A1 (en) 2009-10-13 2010-10-12 Synchronising activities of various components in a distributed system

Country Status (11)

Country Link
US (6) US8732400B2 (en)
EP (3) EP2488952B1 (en)
JP (6) JP2013507708A (en)
KR (3) KR20120095876A (en)
CN (4) CN102713874A (en)
GB (4) GB2474446A (en)
IL (3) IL218703D0 (en)
IN (3) IN2012DN02792A (en)
MY (2) MY155614A (en)
TW (3) TW201120638A (en)
WO (3) WO2011045555A1 (en)

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Also Published As

Publication number Publication date
JP2015057701A (en) 2015-03-26
MY155614A (en) 2015-11-13
KR20120095876A (en) 2012-08-29
IL218704A (en) 2016-03-31
GB0917946D0 (en) 2009-11-25
CN102063391A (en) 2011-05-18
IL218704D0 (en) 2012-05-31
GB2474532B8 (en) 2014-08-20
IN2012DN02792A (en) 2015-07-24
GB201007363D0 (en) 2010-06-16
US20110093557A1 (en) 2011-04-21
KR20120093276A (en) 2012-08-22
GB2474532A8 (en) 2014-08-20
IN2012DN03050A (en) 2015-07-31
GB2474533A (en) 2011-04-20
CN102792290A (en) 2012-11-21
GB2474552A (en) 2011-04-20
CN102576341B (en) 2015-05-27
JP6141905B2 (en) 2017-06-07
EP2488954A1 (en) 2012-08-22
GB201007342D0 (en) 2010-06-16
TW201128398A (en) 2011-08-16
TWI533133B (en) 2016-05-11
IL218887A (en) 2015-10-29
US20110125944A1 (en) 2011-05-26
JP5650749B2 (en) 2015-01-07
EP2488952A2 (en) 2012-08-22
WO2011045555A1 (en) 2011-04-21
EP2488951B1 (en) 2015-01-07
US8732400B2 (en) 2014-05-20
WO2011045556A2 (en) 2011-04-21
EP2488951A1 (en) 2012-08-22
US9477623B2 (en) 2016-10-25
IL218887D0 (en) 2012-06-28
MY154614A (en) 2015-07-15
TW201120638A (en) 2011-06-16
KR101734045B1 (en) 2017-05-24
US8607006B2 (en) 2013-12-10
EP2488954B1 (en) 2015-11-25
JP5865976B2 (en) 2016-02-17
US20110119448A1 (en) 2011-05-19
IN2012DN02853A (en) 2015-07-24
KR101734044B1 (en) 2017-05-11
TW201120656A (en) 2011-06-16
US20110087819A1 (en) 2011-04-14
JP2015167036A (en) 2015-09-24
US20140040516A1 (en) 2014-02-06
US8856408B2 (en) 2014-10-07
GB2474532A (en) 2011-04-20
GB201016482D0 (en) 2010-11-17
JP2013507709A (en) 2013-03-04
GB2474446A (en) 2011-04-20
WO2011045595A1 (en) 2011-04-21
CN102576341A (en) 2012-07-11
US20110087809A1 (en) 2011-04-14
JP2013507710A (en) 2013-03-04
CN102713874A (en) 2012-10-03
KR20120095872A (en) 2012-08-29
JP2013507708A (en) 2013-03-04
EP2488952B1 (en) 2015-05-06
US8601167B2 (en) 2013-12-03
CN102792290B (en) 2015-08-05
GB2474532B (en) 2014-06-11
US8463966B2 (en) 2013-06-11
JP2011138481A (en) 2011-07-14
TWI474193B (en) 2015-02-21
IL218703D0 (en) 2012-05-31

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