IN2012DE00145A - - Google Patents

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Publication number
IN2012DE00145A
IN2012DE00145A IN145DE2012A IN2012DE00145A IN 2012DE00145 A IN2012DE00145 A IN 2012DE00145A IN 145DE2012 A IN145DE2012 A IN 145DE2012A IN 2012DE00145 A IN2012DE00145 A IN 2012DE00145A
Authority
IN
India
Prior art keywords
instruction
loop processing
identification circuit
transition
identifies
Prior art date
Application number
Other languages
English (en)
Inventor
Naoya Ohnishi
Hiroshi Nakatani
Yoshito Sameda
Jun Takehara
Atsushi Inoue
Makoto Toko
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of IN2012DE00145A publication Critical patent/IN2012DE00145A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0715—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a system implementing multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
IN145DE2012 2011-01-19 2012-01-17 IN2012DE00145A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011008983A JP2012150661A (ja) 2011-01-19 2011-01-19 プロセッサ動作検査システム、及びその検査方法

Publications (1)

Publication Number Publication Date
IN2012DE00145A true IN2012DE00145A (fr) 2015-06-05

Family

ID=46491739

Family Applications (1)

Application Number Title Priority Date Filing Date
IN145DE2012 IN2012DE00145A (fr) 2011-01-19 2012-01-17

Country Status (4)

Country Link
US (1) US20120185858A1 (fr)
JP (1) JP2012150661A (fr)
CN (1) CN102693176A (fr)
IN (1) IN2012DE00145A (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012088815A (ja) * 2010-10-15 2012-05-10 Toshiba Corp マイクロプロセッサ動作監視システム
JP6718294B2 (ja) * 2016-04-25 2020-07-08 アズビル株式会社 レジスタ異常検出装置
JP7045293B2 (ja) * 2018-09-19 2022-03-31 日立Astemo株式会社 電子制御装置
CN111651325A (zh) * 2020-06-02 2020-09-11 中电科航空电子有限公司 一种机载设备任务监控系统及方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062684B2 (en) * 2002-12-19 2006-06-13 International Business Machines Corporation Enabling tracing of a repeat instruction
US8577942B2 (en) * 2004-07-07 2013-11-05 Mitsubishi Electric Corporation Electronic device and data processing device for implementing cryptographic algorithms
US20070011300A1 (en) * 2005-07-11 2007-01-11 Hollebeek Robert J Monitoring method and system for monitoring operation of resources
JP4359632B2 (ja) * 2007-06-13 2009-11-04 株式会社トヨタＩｔ開発センター プロセッサ動作検査システム及び動作検査回路
WO2009096519A1 (fr) * 2008-01-31 2009-08-06 Nec Corporation Procédé de précompensation, dispositif de contrôle qualité de fourniture de services, système, programme et support d'enregistrement associé
JP2010009296A (ja) * 2008-06-26 2010-01-14 Fujitsu Ltd ソフトウェア動作監視装置およびソフトウェア動作監視方法
US8583845B2 (en) * 2008-08-07 2013-11-12 Nec Corporation Multi-processor system and controlling method thereof
US20130191681A1 (en) * 2010-10-11 2013-07-25 General Electric Company Systems, methods, and apparatus for signal processing-based fault detection, isolation and remediation
US9135586B2 (en) * 2010-10-28 2015-09-15 Sap Se System for dynamic parallel looping of repetitive tasks during execution of process-flows in process runtime

Also Published As

Publication number Publication date
US20120185858A1 (en) 2012-07-19
JP2012150661A (ja) 2012-08-09
CN102693176A (zh) 2012-09-26

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