IL44285A

IL44285A - Shock falsing inhibitor circuit for a plural tone receive

Info

Publication number: IL44285A
Application number: IL44285A
Authority: IL
Original assignee: Motorola Inc
Priority date: 1973-03-01
Filing date: 1974-02-25
Publication date: 1976-07-30
Also published as: DE2409974B2; IL44285A0; BR7401396D0; ZA741253B; CA981342A; US3806938A; JPS502804A; AU6611174A; FR2220077A1; AR199607A1; AU461470B2; DE2409974A1; GB1436472A

Abstract

In a sequential plural tone receiver, the first tone is detected and differentiated to produce a pulse which begins when the tone is received and continues for a predetermined duration. The differentiated pulse and the detected second tone are applied to an AND gate which, if both signals are simultaneously applied, provides an output that inhibits the operation of the receiver and is applied through a latch to the input of the AND gate to maintain the AND gate in operation until the second tone stops. If the second tone appears at any time after the differentiated pulse is removed the receiver operates in a normal fashion. [US3806938A]

Claims

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1. A shock falsing inhibitor circuit for a plural tone receiver including first detector means adapted to receive a first tone signal and providing a first square pulse approximately equal in duration to the first tone signal in response to the first tone signal, second detector means adapted to receive a second tone signal and providing^ second square pulse approximately- equal in duration, to. the second tone signal in response to the second tone signal, different ating means coupled 10 to said first detector means for providing a. pulse having a predetermined duration in response to the first square pulse gate means coupled to said differentiating means and -said second detector means and providing an output signal in response to the simultaneous application of the pulse from the differentiating means and the second square pulse, and means coupled to said gate means and responsive to the output signal therefrom to inhibit the operation of the plural tone receiver.

2. A shock falsing Inhibitor circuit according 20 to claim 1, including latch means coupled to the gate means for applying an input signal to said gate means in response to an output signal from said gate means for the duration of the second square pulse.

3. A shock falsing inhibitor circuit according to claim 1 or 2, wherein the gate means Is in the form of an AND gate.

4. A shock falsing inhibitor circuit for a plural tone receiver, including first, second and third transistors each having first, second and control elec- trodes, means coupling the first and second terminals of said first transistor between first and second junction points adapted to have opposite terminals of a power supply connected thereto, a resistor-capacitor network connected to the control electrode of said first transistor for biasing said first transistor normally into conduction and adapted to receive- a square pulse generated by a first tone and supply a pulse of predetermined duration to the control electrode of said first transistor to re-duce the conduction for said predetermined duration in response to the square pulse, the first terminal of said second transistor being coupled to the control electrode of said first transistor and the second terminal of said second transistor adapted to receive a second square pulse generated by a second tone, means coupling the control electrode of said second ' transistor to the first electrode of said .first transistor and to the control electrode of said third transistor, and the first electrode of said third transistor being coupled to the first junction point and the second electrode of said third transistor being adapted to supply an inhibit signal in response to the second square pulse applied to the second terminal of said second transistor during the application of the pulse of predetermined duration to the control electrode of said first transistor. -:

5. A shock falsing inhibitor circuit according to claim 4, wherein the means coupling the first and second terminals of said first transistor between first and second junction points include a resistor coupled between the first terminal and the first junction point and a semiconductor diode coupled between the second terminal and the second junction point.

6. A shock falsing inhibitor circuit according to claim 4 or 5J wherein the resistor-capacitor network includes a series capacitor coupled to the control electrode of said first transistor and a resistor coupled between the control electrode of said first transistor and the first junction point.

7. A shock falsing inhibitor circuit according to claim K, wherein the means coupling the control electrode of said second transistor to the first electrode of said first transistor and to the control electrode of said third transistor includes a resistor.

8. A shock falsing inhibitor circuit according to any one of claims 4 to 7, wherein the first, second and third transistors are each the NPN conduction type with the first electrodes being the collectors, and. the second electrodes the emitters and the first junction PQint is adapted to have a positive voltage supply con-nected thereto.

9. A shock flashing inhi itoc.i. ireuit ' constructed substantially as herein described with reference to the accompanying drawings.