IL313221A - Coating dielectric surfaces with a patterned metal layer - Google Patents

Description

– 1 – COATING DIELECTRIC SURFACES WITH PATTERNED METAL LAYER TECHNICAL FIELD The present disclosure, in some embodiments thereof, relates to creating a patterned metal layer on a dielectric wafer and, more particularly, but not exclusively, to creating a patterned metal layer on a quartz wafer surface that is not flat and is not regular. BACKGROUND Several processes are used in the manufacturing of microelectromechanical systems (MEMS). Williams G. L. et al. "The patterning of fine-pitch electrical interconnections on non-planar substrates: a comparison between methods utilising laser ablation and electro-deposited photoresist." Sensors and Actuators A:Physical, Volume 112, Issues 2–3, 2004, Pages 360-367, compares two methods for patterning electrical interconnections onto grossly non-planar surfaces. The first method involves the selective ablation of nickel using a YAG laser. The second method employs an electro-depositable photoresist to pattern a copper seed layer that is then overplated with nickel. Kim, B., Nam, H.K., Watanabe, S. et al. "Selective Laser Ablation of Metal Thin Films Using Ultrashort Pulses." Int. J. of Precis. Eng. and Manuf.-Green Tech. 8, 771 –782 (2021), describes a mechanism of laser ablation that leads to selective removal of a thin metal film. Larry O'Connell, Brice Poirier, Oleksii Bratash, Charlène Plénière, Loïc Leroy, Yoann Roupioz, Pierre R. Marcoux, "Rapid fabrication of interdigitated electrodes by laser ablation with application to electrokinetically enhanced surface plasmon resonance imaging" Optics & Laser Technology, Volume 161, 2023, describes using a commercial printed circuit board prototyper was used to pattern interdigitated electrode (IDE) arrays into the surface of gold-coated slides and off-the-shelf surface plasmon resonance (SPR) prisms. U.S. Patent No. 7,406,756 discusses a method for manufacturing a piezoelectric resonator. 30 – 2 – U.S. Patent No. 7,682,970 discusses systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Acknowledgement of the above references herein is not to be inferred as meaning that these are in any way relevant to the patentability of the presently disclosed subject matter. SUMMARY OF THE INVENTIONAccording to some embodiments there are provided a method of coating a dielectric wafer with a patterned metal layer, a method of preparing a dielectric wafer for laser ablation and piezoelectric MEMS elements manufactured by embodiments of a method of the disclosure. Embodiments disclosed herein are suitable for coating surfaces of dielectric wafers and/or substrates (e.g., crystalline quartz and glass) that are not flat and regular, with a patterned metal layer by means of laser metal ablation. In some embodiments, the patterned metal layer is formed using laser ablation on a metal layer on the surface of a dielectric wafer having areas with different heights. For example, the wafer may have one or more sunken portions, and these sunken portions may be of the same or differing depths. Using laser ablation may enable removing the portions of the metal layer to form patterns on the upper wafer surface, the surface(s) of the sunken portion(s). In some embodiments, the pattern is formed on walls of the sunken portion(s). In some embodiments, these walls are sloped. In some embodiments, the metal pattern formed by laser ablation has closed contours. Some embodiments of the disclosure are particularly suitable for manufacturing MEMS sensors, based dielectrics, to form one or more of: 1) A metal etching mask; 2) Surface electrode(s), 3) Conductor(s) and/or pad(s) for connection to the electrodes of associated electronic circuits. Some embodiments according to the disclosure are used for manufacturing MEMS based on a dielectric material, such as crystalline quartz. Manufacturing MEMS – 3 – on crystalline quartz is well adapted for MEMS sensors, which have a wide application due to the unique piezoelectric properties of quartz. In some embodiments, the dielectric wafer is prepared for laser ablation using two stages of chemical etching. The first stage shapes the wafer into the required three dimensional structure. The second stage removes undercut(s) which may have formed during the first stage. In some further embodiments according to the disclosure, after the second stage the wafer (now having an irregular surface) is coated with a conductive (i.e. metal) layer and laser ablation is performed on the wafer to form the required pattern as described below. The first stage of chemical etching stage may include a single cycle of chemical etching or multiple cycles of chemical etching (for example see Fig. 3B). A respective etching mask is used for each cycle. Optionally, the etching mask is a metal mask. Further optionally, the etching mask is a gold layer over a chromium adhesive layer (Au/Cr) for dielectric materials such as quartz or glass. The etching mask is a material or layer that protects certain areas of a substrate from being etched during the chemical etching process. The mask acts as a barrier, defining the regions on the substrate where material removal is desired and those where it should be preserved. According to some embodiments of the disclosure, at least one of the etching mask(s) is formed on the dielectric material by laser ablation of a metal layer previously deposited on the wafer (for example see Fig. 3C). The etching mask may be formed in this manner, even when the wafer surface is irregular and non-planar. The result of the first chemical etching stage is a wafer with an irregular surface and/or having at least one height difference between different areas of the wafer. After the first chemical etching stage is completed, there may be an undercut surrounding all or part of the sunken portion(s). Chemical etching undercut is a phenomenon in which the etching process removes material from beneath the protective mask, creating a recessed or undercut feature in the substrate. One problem that may be caused by undercuts is that they may block the laser beam, when laser ablation is performed, so that the laser beam is unable to reach areas on the walls and/or the surface of the sunken portion(s). Thus, undercut features may interfere with creating continuous – 4 – uninterrupted conductive lines in the metal layer using a laser. Additionally, unremoved undercuts may cause short circuits. According to some embodiments of the disclosure, a second stage of chemical etching is performed to remove the undercuts. After the undercuts are removed, the wafer may be coated with a metal layer, in preparation for forming the pattern on the wafer surface using laser ablation. Optionally, after the undercuts are removed, a metal coating (e.g. Au/Cr) is applied to the wafer surface and laser ablation is used to remove portions of the metal coating to create elements such as electrodes, conductors, pads on the wafer surface. Reference is now made to Figs. 1A-1D and Fig. 2, which are simplified cross- section view illustrations of the formation and removal of an undercut by chemical etchings performed on a substrate such as a dielectric wafer, in accordance with exemplary embodiments of the disclosure. In Fig. 1A, dielectric wafer 110 is coated with etching mask 120. An area with width d1 is not covered, which leaves it exposed to the chemical etchant. Fig. 1B illustrates dielectric wafer 110 after the first chemical etching stage but etching mask 120 has not yet been removed. As can be seen, the chemical etchant formed sunken portion 130 within the wafer but also removed some of the material directly underneath the etching mask, resulting in an undercut. Fig. 1C illustrates dielectric wafer 110 after it undergone the first chemical etching stage and the etching mask has been removed. As can be seen, wafer 110 has a sunken portion 130 and undercut 140 that was caused by the first chemical etching stage. The second chemical etching stage removes undercut 140 which may block the laser beam during the laser ablation of the metal layer, so that a desired pattern may be formed over the entire wafer surface, including the walls and surface of the sunken portion(s). This may result in a slight expansion of the sunken portion in addition to removing the undercut, however the etching process may be controlled so that the desired size of the sunken portion is obtained after the second chemical etching stage. Reference is now made to Fig. 1D, which is a simplified illustration of the dielectric wafer after the second chemical etching stage. The undercut portions have been removed. In the simplified illustration, the width and depth of the sunken portion increased slightly during the second etching stage (width from d2 to d3 and depth from – 5 – d4 to d5). However as noted above the desired dimensions of the sunken portion may be obtained by appropriate control of the two etching stages. Once the undercut has been removed, a metal coating may be applied to the wafer in preparation for forming a patterned metal layer (e.g. electrodes, conductors, etching mask, etc.) on the wafer surface by laser ablation. Reference is now made to Fig. 2, which is a simplified illustration of the dielectric wafer after being coated with metal layer 150. The patterned metal layer may now be created on the upper surface of wafer 110, and on the walls and bottom of sunken portion 130 by removing areas of metal layer 150 with laser ablation. For clarity, Figs. 1B-1C show a non-limiting example in which an undercut has the same size and shape on both sides of the sunken portion. In practice, it will be found that the undercut may have different sizes and shapes around the perimeter of the sunken portion(s). The second chemical etching stage may be controlled to remove the material as needed in order to eliminate the undercut around the entire perimeter of the sunken portion. In some embodiments, the dielectric substance may be aligned so that the sunken portion formed during the first chemical etching stage has sloped walls. One example of this type of dielectric substance is monocrystalline quartz. In some embodiments of the disclosure: 1) Photolithographic steps such as photoresist application, photoresist wet chemistry processes, and photolithographic mask preparation and alignment are avoided. 2) A metal etching mask may be formed on a non-planar and/or irregular surface of the wafer. 3) No expensive specialized equipment or clean room are required. 4) Less chemical waste is produced than a photolithographic manufacturing of a similar element. 5) Surface electrodes may be manufactured on stepped, sloped and non-flat surfaces, which may result in a more efficient device (e.g., lower voltage requirements). 6) Flexible conductive pattern layout and the possibility of forming closed contours enables manufacturing high performance devices (relative to similar types of devices manufactured using photolithography). For example, the layout the electrodes of a quartz resonator may be designed to optimize the piezoelectric performance of the – 6 – quartz resonator, and in consequence the precision of the quartz sensor which includes the resonator. 7) Electrodes on the piezoelectric material may be electrically connected to the electrical pads, providing further connection to the electronic circuit. Electrodes on sunken surfaces and walls give the option to put the pads on any suitable surfaces, which are not necessarily flat and/or at the same height as the electrodes surface. 8) Electrodes may be very thin but still conductive, due to the accuracy and resolution of laser ablation. This may increase the quality factor and improve the performances of the manufactured element (e.g., quartz resonator). According to a first aspect of some embodiments of the present disclosure there is provided a method of coating a dielectric wafer with a patterned metal layer, the wafer comprising a dielectric surface upon which the patterned metal layer is formed. The method includes: forming at least one sunken portion in a dielectric wafer by performing a first chemical etching stage comprising at least one chemical etching of the dielectric wafer using respective etching masks; removing a final one of the etching masks from the dielectric wafer; performing a second chemical etching stage on the dielectric wafer; depositing a metal layer on the dielectric wafer; and forming a pattern on the metal layer by laser ablation. According to some embodiments of the disclosure, the dielectric wafer consists of a dielectric material. According to some embodiments of the disclosure, dielectric wafer includes a dielectric layer on a substrate, the metal pattern being formed on the dielectric layer. According to some embodiments of the disclosure, the etching rate of the first chemical etching stage is larger than the etching rate of the second chemical etching stage. According to some embodiments of the disclosure, the second chemical etching stage removes an undercut around the at least one sunken portion. According to some embodiments of the disclosure, the second chemical etching stage is performed without a mask. – 7 – According to some embodiments of the disclosure, the metal pattern is formed on a top surface of the dielectric wafer and on a surface of the at least one sunken portion. According to some embodiments of the disclosure, the metal pattern is further formed on at least one wall of the sunken portion, so as to form an electrical connection between the metal pattern on the top surface of the dielectric wafer and the metal pattern on the surface of the at least one sunken portion. According to some embodiments of the disclosure, the metal layer is deposited on the dielectric wafer using a shadow mask. According to some embodiments of the disclosure, the respective etching masks include a gold over chromium layer. According to some embodiments of the disclosure, the metal pattern includes a closed contour. According to some embodiments of the disclosure, the dielectric wafer is quartz. According to some embodiments of the disclosure, the method further includes aligning the etching mask on the dielectric wafer so as to obtain a sunken portion with sloped sides. According to a second aspect of some embodiments of the present disclosure there is provided a piezoelectric element manufactured by any embodiment of the disclosure. According to some embodiments of the disclosure, the piezoelectric element is part of a microelectromechanical system (MEMS). According to a third aspect of some embodiments of the present disclosure there is provided a method of preparing a dielectric wafer for laser ablation. The method includes: forming at least one sunken portion in the dielectric wafer by performing a first chemical etching stage comprising at least one chemical etching of the dielectric wafer using respective etching masks; removing a final one of the etching masks from the dielectric wafer; and removing an undercut around the at least one sunken portion by performing a second chemical etching stage on the dielectric wafer. According to some embodiments of the disclosure, the dielectric wafer consists of a dielectric material. – 8 – According to some embodiments of the disclosure, the dielectric wafer includes a dielectric layer on a substrate. According to some embodiments of the disclosure, the method further includes, for at least one of the etching masks: coating a surface of the wafer with a metal layer; and forming the etching mask by removing a portion of the metal layer by laser ablation. According to some embodiments of the disclosure, the method further includes depositing a metal layer on a surface of the dielectric wafer. According to some embodiments of the disclosure, the metal layer is deposited on the dielectric wafer using a shadow mask. According to some embodiments of the disclosure, the etching rate of the first chemical etching stage is larger than the etching rate of the second chemical etching stage. According to some embodiments of the disclosure, the second chemical etching stage is performed without a mask. Unless otherwise defined, all technical and/or scientific terms used within this document have meaning as commonly understood by one of ordinary skill in the art/s to which the present disclosure pertains. Methods and/or materials similar or equivalent to those described herein can be used in the practice and/or testing of embodiments of the present disclosure, and exemplary methods and/or materials are described below. Regarding exemplary embodiments described below, the materials, methods, and examples are illustrative and are not intended to be necessarily limiting. Some embodiments of the present disclosure are embodied as a method or a semiconductor element. Implementation of the method and/or system of some embodiments of the present disclosure can involve performing and/or completing selected tasks manually, automatically, or a combination thereof. According to actual instrumentation and/or equipment of some embodiments of the method and/or system of the present disclosure, several selected tasks could be implemented by hardware, by software or by firmware and/or by a combination thereof, e.g., using an operating system. For example, hardware for performing selected tasks according to some embodiments of the present disclosure could be implemented as a chip or a circuit. As – 9 – software, selected tasks according to some embodiments of the present disclosure could be implemented as a plurality of software instructions being executed by a computational device e.g., using any suitable operating system. In some embodiments, one or more tasks according to some exemplary embodiments of method and/or system as described herein are performed by a data processor, such as a computing platform for executing a plurality of instructions. Optionally, the data processor includes a volatile memory for storing instructions and/or data and/or a non-volatile storage e.g., for storing instructions and/or data. Optionally, a network connection is provided as well. User interface/s e.g., display/s and/or user input device/s are optionally provided. Some embodiments of the present disclosure may be described below with reference to flowchart illustrations and/or block diagrams. For example illustrating exemplary methods and/or apparatus (systems) and/or and computer program products according to embodiments of the present disclosure. The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of methods and elements manufactured according to various embodiments of the disclosed subject matter. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions. It will be understood that each step of the flowchart illustrations and/or block of the block diagrams, and/or combinations of steps in the flowchart illustrations and/or blocks in the block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, special purpose computer, or other programmable data processing – 10 – apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart steps and/or block diagram block or blocks. These computer program instructions may also be stored in a computer readable medium that can direct a computer (e.g., in a memory, local and/or hosted at the cloud), other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium can be used to produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks. The computer program instructions may also be run by one or more computational device to cause a series of operational steps to be performed e.g., on the computational device, other programmable apparatus and/or other devices to produce a computer implemented process such that the instructions which execute provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

BRIEF DESCRIPTION OF THE DRAWINGS Embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings. Features shown in the drawings are meant to be illustrative of only some embodiments of the disclosure, unless otherwise indicated. In the drawings like reference numerals are used to indicate corresponding parts. In block diagrams and flowcharts, optional elements/components and optional stages may be included within dashed boxes. In the figures: Figs. 1A-1D and Fig. 2 are simplified cross-section view illustrations of the formation and removal of an undercut by chemical etchings performed on a substrate such as a dielectric wafer, in accordance with exemplary embodiments of the disclosure; Fig. 3A is a simplified flowchart of a method of preparing a dielectric wafer for laser ablation, according to some embodiments of the disclosure; – 11 – Fig. 3B is a simplified flowchart of a method of performing the first etching stage, according to some embodiments of the disclosure; Fig. 3C is a simplified flowchart of a method of preparing an etching mask on a wafer surface using laser ablation, according to some embodiments of the disclosure; Fig. 4A is a simplified flowchart of a method of coating a wafer with a patterned metal layer, according to some embodiments of the disclosure; Fig. 4B is a simplified flowchart of a method of manufacturing a dielectric wafer with a patterned metal layer, according to some exemplary embodiments of the disclosure; and Figs. 5A-5C are simplified illustrations of some stages of manufacturing a single-beam quartz resonator in accordance with embodiments of the invention. The various embodiments of the present disclosure are described below with reference to the drawings, which are to be considered in all aspects as illustrative only and not restrictive in any manner. Elements illustrated in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of embodiments of the disclosure. Moreover, two different objects in the same figure may be drawn to different scales.

DETAILED DESCRIPTION OF EMBODIMENTS The present disclosure, in some embodiments thereof, relates to creating a patterned metal layer on a dielectric wafer and, more particularly, but not exclusively, to creating a patterned metal layer on a quartz wafer surface that is not flat and is not regular. The principles, uses and implementations of the teachings herein may be better understood with reference to the accompanying description and figures. Upon perusal of the description and figures present herein, one skilled in the art will be able to implement the teachings herein without undue effort or experimentation. Before explaining at least one embodiment of the disclosure in detail, it is to be understood that the embodiment is not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the – 12 – following description and/or illustrated in the drawings and/or the other embodiments may be practiced or carried out in various ways. I. Method for preparing a dielectric wafer Reference is now made to Fig. 3A, which is a simplified flowchart of a method of preparing a dielectric wafer for laser ablation, according to some embodiments of the disclosure. In some embodiments, laser ablation is used to form a conductive pattern (e.g. a metal pattern) on the dielectric wafer. The metal pattern may form a) an etching mask and/or b) electrodes and/or pads and/or wires and so forth having a desired size, shape and contour. The use of a dielectric wafer is common in MEMS manufacturing. In some cases the dielectric wafer is composed completely of the dielectric substance. In alternate cases, a wafer substrate (usually a semiconductor substrate) is coated with a layer of a dielectric substance. Examples of dielectric substances (also denoted herein dielectric materials) include but are not limited to monocrystalline quartz, fused silica, glass, silicon nitride, polymers, ceramic, low-k dielectric materials and many others. For clarity, some of the embodiments described herein are for a wafer in which a single sunken portion is formed on the wafer by the etching process. As will be understood by a person skilled in the art, multiple sunken portions may be formed on a single wafer, either in a single cycle (in which the sunken portions will typically have the same depth) or in multiple cycles of chemical etching using respective etching masks (which may result in sunken portions with different depths in the wafer). As used herein, according to some embodiments of the disclosure, the term "wafer" means a thin slice of material used for the fabrication of electronic elements such as MEMS. The terms "wafer" and "dielectric wafer" include wafers formed from a dielectric material and wafers formed as a layer of dielectric material over a substrate of a different material (e.g. a semiconductor substrate). As used herein, according to some embodiments of the disclosure, the term "chemical etching" means chemically removing layers from the surface of the dielectric wafer. – 13 – As used herein, according to some embodiments of the disclosure, the term "sunken portion" means a portion of the dielectric wafer whose surface is below the upper surface of the dielectric layer. This creates a height difference between different portions of the dielectric wafer. As used herein, according to some embodiments of the disclosure, the term "metal layer" means a layer of metal deposited on the wafer (either the entire wafer or using a shadow mask). As used herein, according to some embodiments of the disclosure, the term "patterned metal layer" means the metal layer after portions have been removed by laser ablation to form a pattern; As used herein, according to some embodiments of the disclosure, the term "etching rate" means the speed at which material is removed during the process of chemical etching. As used herein, according to some embodiments of the disclosure, the term "etching mask" means a protective layer that selectively prevents or allows the removal of the underlying material by a chemical etchant. The term etching mask includes an etching mask formed by laser ablation of a material deposited on the wafer surface into a desired shape. As used herein, according to some embodiments of the disclosure, the term "shadow mask" is a mask that prevents the deposition of a material on areas of the dielectric wafer. The shadow mask may be used to create patterns of the deposited material on the dielectric wafer. As used herein, according to some embodiments of the disclosure, the term "laser ablation" means removing material from at least the metal layer by irradiating it with a laser beam. In 310 at least one sunken portion is formed on the wafer surface by performing a first chemical etching stage of the dielectric wafer. The first chemical etching stage includes one or more chemical etching cycles performed using respective etching mask(s). A sunken portion (or portions) are formed during the etching in areas of the dielectric material that are not protected by the etching mask. Optionally, at least one of the etching masks is a metal mask. Further optionally, the metal mask is an Au/Cr mask. – 14 – Optionally, the first chemical etching stage includes a single chemical etching cycle using an etching mask. Alternately, the first chemical etching stage includes multiple chemical etching cycles using respective etching masks applied on the planar wafer surface as well as the on sunken wafer surface portions, possibly of different depths. An exemplary first chemical etching stage with one or more cycles of chemical etching is described below with respect to Fig. 3B. Optionally, at least one of the etching mask(s) is formed by laser ablation of a material applied to the wafer surface. An exemplary method of forming an etching mask by laser ablation is described below with respect to Fig. 3C. Optionally, at least one of the etching mask(s) is a 200 nm thick gold layer over nm chromium as the adhesion layer, made by physical vapor deposition (PVD). Optionally, at least one sunken portion formed in the first chemical etching stage has sloped walls. Optionally, the dielectric wafer is a monocrystalline quartz wafer. Optionally, the method includes one or more steps of forming an etching mask(s) by laser ablation on the dielectric wafer surface, so that one or more cycles of the first chemical etching stage create a sunken portion with sloped walls. After the etching cycle(s) in 310 are completed, in 320 the final etching mask is removed from the dielectric wafer. At this point, the dielectric wafer has one or more sunken portions. Typically there is an undercut around parts or all of the perimeter of some or all of the sunken portion(s). In 330 the undercut is removed by performing a second chemical etching stage of the dielectric wafer. In some embodiments, the second etching removes a thin layer of material from all the wafer surface as well as the undercut. Optionally, the second chemical etching stage is performed without an etching mask. Thus, the chemical etchant used in the second etching is active on the entire surface of the dielectric wafer, including the top surface of the dielectric wafer, and the walls and surface(s) of the sunken portion(s). The first and second etching stages may be tailored to perform the two etchings differently. Factors which may be adjusted to control the characteristics of the etching process may include but are not limited to: etchant chemistry, mask material, etching temperature and time, and etching rate. – 15 – Optionally, the etching rate of the first chemical etching stage is greater than the etching rate of the second chemical etching stage. The first chemical etching stage may remove the dielectric material from the wafer at a rate that creates sunken portion(s) with a satisfactory accuracy. The second chemical etching stage removes the dielectric material more slowly, which may enable finer control of the removal of the material so that size and shape of the sunken are not increased too much due to the removal of the undercut. Optionally, in 340 a metal layer is deposited on the surface of the dielectric wafer. In some embodiments, the metal layer is deposited without using a mask so that the metal covers the entire surface. In alternate embodiments, the metal layer is deposited using a shadow mask so that the metal covers some of the surface of the dielectric wafer. The dielectric wafer, chemical etching processes and etchants and masks may be in accordance with any materials and processes known in the art and suitable for the embodiments presented herein. Examples of methods of chemical etching for crystalline quartz include but are not limited to: a) Etching in saturated ammonium bifluoride (ABF, NH4HF2) solution at 87 °C; b) Using etchant mixtures (denoted Buffered Hydrofluoric Acid) of Hydrofluoric Acid (HF) and Ammonium Fluoride (NH4F) diluted in water, with etch temperature ranging from 22 to 80 °C and the concentration varied from pure HF solution to the proportions 1:4 / HF:NH4F. The etched quartz properties, including surface roughness and the side-wall slopes geometry, in fluoride-based etchants vary with etchant type, its concentration and temperatures. Reference is now made to Fig. 3B, which is a simplified flowchart of a method of performing the first etching stage, according to some embodiments of the disclosure. Fig. 3B illustrates an iterative process, which may have a single iteration (i.e. a single etching cycle in the first stage) or multiple iterations (i.e. multiple etching cycles in the first stage). In 350 an etching mask is formed on the surface of a dielectric wafer. Optionally, the etching mask is formed by coating the wafer surface with a metal layer and removing portions of the metal layer to form the etching mask. – 16 – In 351 a chemical etching cycle is performed. Some wafter material that is not protected by the etching mask is thereby removed. In 352 the etching mask is removed from the dielectric wafer. Note that during the final iteration of the first stage the final etching mask is removed from the dielectric wafer (corresponding to 320 in Fig. 3A). In 353, if another cycle of chemical etching is required the method returns to 3to perform another cycle. If not, the wafer is ready for the second etching stage. Reference is now made to Fig. 3C, which is a simplified flowchart of a method of preparing an etching mask on a wafer surface using laser ablation, according to some embodiments of the disclosure. Fig. 3C includes cases in which the wafer surface is not flat and regular. In 360 a metal layer is deposited on the surface of the dielectric wafer. In 361, portions of the metal layer are removed by laser ablation to form the etching mask. II. Method of coating a dielectric wafer with a laser-patterned metal layer Reference is now made to Fig. 4A, which is a simplified flowchart of a method of coating a wafer with a patterned metal layer, according to some embodiments of the disclosure. The patterned metal layer is created on the wafer after the second chemical etching stage is completed. Thus the wafer surface is non-planar due to the sunken portions created by first and second etching stages. In 401, a metal layer is deposited on the dielectric wafer surface. Non-limiting examples of metals which may be used to form a patterned layer are gold, nickel, aluminum, copper, chromium, titanium, tungsten, platinum, and silver. Further optionally, the metal layer is gold over chromium. Optionally, the metal layer is deposited on the dielectric wafer using a shadow mask around the area that will undergo laser ablation. The shadow mask is not produced by the photolithography process. Non-limiting examples of methods for producing a shadow mask include machining, laser cut, and electrical discharge machining. Non-limiting examples of materials for a shadow mask include Kapton or other polymer with low outgassing, as well as glass or thin metal sheets. In 402, a desired pattern is formed on the metal layer by laser ablation. The laser ablation creates the desired pattern by selectively removing portions of the metal layer – 17 – in accordance with a specified pattern. Thus, the patterned metal layer may be formed without using a mask, and particularly without using a photo mask for photolithography. Optionally, the laser ablation is performed by repeated scans. Optionally, the metal pattern is formed on the top surface of the dielectric wafer and on the surface of the sunken portion(s). Further optionally, the metal pattern is formed on at least one wall of some or all of the sunken portion(s), thereby forming an electrical connection between the conductive pattern on the top surface of the dielectric wafer and the conductive pattern on the surface of the sunken portion(s). Optionally, the conductive pattern includes a closed contour. Optionally, a conductive pattern is formed by laser ablation on both sides of the wafer. In one exemplary embodiment, the method includes: 1) Performing a first chemical etching stage using etching masks for the top and/or bottom surfaces of the wafer for each cycle of chemical etching. Optionally, each cycle includes: forming an etching mask on the wafer surface, etching the wafer and removing the etching mask upon completion of the etching process. The first chemical etching stage forms one or more sunken portions on one or both sides of the dielectric wafer. The etching mask may be formed on the wafer surface (which may be non-planar and irregular) by coating the wafer surface with a metal layer and then patterning the metal layer by laser ablation; 2) Performing a second chemical etching stage to remove the undercut from the sunken portions; 3) Depositing a metal layer on both sides of the dielectric wafer, optionally separately for each side; and 4) Forming, with laser ablation, a pattern in the metal layer on both sides of the dielectric wafer. Optionally the metal pattern is formed separately for each side (e.g., forming a pattern on one side of the dielectric wafer, rotating the dielectric wafer and forming a pattern on the second side). Laser ablation is a very precise process, which may create accurate conductive electrodes and wires. The features size and accuracy depend on a number of parameters, such as the laser spot size, wavelength and radiation intensity. For example, using ultraviolet (UV) laser with a Gaussian beam spot size of ~2 µm allows features size as small as 4.5 µm. Laser beam scanner and positioning system accuracy and repeatability – 18 – may define the patterned features accuracy (for example accuracy may be targeted to be ±0.5 µm). Optionally, the laser ablation is performed by short pulse (fsec to nsec) laser. Optionally, the laser uses a UV wavelength (for example 330-360 nm) for fine patterns. Fig. 4B is a simplified flowchart of a method of manufacturing a dielectric wafer coated with a patterned metal layer, according to some exemplary embodiments of the disclosure. In 405, a quartz wafer surface is coated with metal by PVD. In 406, a metal etching mask is formed on the quartz wafer surface by removing portions of the metal coating by laser ablation. In 410, the first chemical etching stage is performed using etching mask(s) to form the required shape(s) and/or sunken portion(s) in the wafer. In 420, the final etching mask is removed from the dielectric wafer. Although 420 is shown explicitly in Fig. 4B, removing the final etching mask may be considered part of the first chemical etching stage as described above. In either case, the result is a wafer with an irregular and/or non-planar shape with no etching mask on it. In 430, a second chemical etching stage is performed on the dielectric wafer to remove the undercut(s). In 440, a metal layer is deposited on the dielectric wafer surface, optionally using a shadow mask. In 450, a conductive metal pattern is formed on the wafer by removing portions of the metal layer deposited in 440 by laser ablation. III. MEMS elements Some embodiments of the method described herein may be utilized to fabricate a variety of devices that require precise patterning of metal layers on dielectric substrates during manufacturing. This method is particularly useful in the fields of microelectromechanical systems (MEMS). The versatility of some of these embodiments, including the ability to create sunken portions with a patterned metal layer not only on the top surface but also on the surface and walls of the sunken portions, opening up possibilities for – 19 – creating two- and three-dimensional structures in advanced device architectures spanning a range of technologies. Examples of technologies that may be suitable for some embodiments of the disclosure include but are not limited to: 1) Piezoelectric (dielectric) elements: In piezoelectric sensors, actuators and other elements in which a conductive layer (e.g. metal layer) needs to be accurately defined on a piezoelectric material such as crystalline quartz. These devices are used in a variety of applications, including but not limited to pressure sensors, accelerometers, and microphones. 2) Dielectric but not piezoelectric elements: For example, High-Q Fused Silica Micro-Shell Resonators for Navigation-Grade MEMS Gyroscopes. IV. Monocrystalline quartz resonators Monocrystalline quartz resonators are a key component of miniature monolithic quartz accelerometers or gyros suitable for various applications, like guidance systems and vehicle dynamic control. Monocrystalline quartz resonators usually comprise a thin quartz crystal with "on surface" metal electrodes that establish an alternating electric field across the crystal, causing the quartz crystal resonant vibrational motion exploring the piezoelectric effect. Resonant sensors are based on the resonance frequency (or relative phase of oscillation) of a vibrating beam, which is highly sensitive on parameters that alter the resonator stiffness or geometry. One type of quartz resonator is a single-beam resonator, which in principle has twice the force sensitivity of a double-beam resonator and less strict requirements for the cross-sectional profiles of the beams. Single-beam quartz resonators are known in the art, for example in US Pat. Appl. No. 6386035, US Pat. Publ. 2006/0096378 A1, US Pat. Appl. No. US5755978, and European Pat. No. 0551152 A1, which are incorporated in their entirety by reference into the specification. However, the restrictions of the photolithographic manufacturing, in particular the inability to pattern closed contours and the requirements for a flat surface, have seriously limited their design options. Reference is now made to Figs. 5A-5C, which are simplified illustrations of some stages of manufacturing a single-beam quartz resonator in accordance with embodiments of the invention. – 20 – Fig. 5A shows a top and cross-section view of a quartz wafer after it has been shaped during the second chemical etching stage. In a first etching stage (not shown), while creating the resonance beam, a sunken portion was formed in the quartz wafer surface. The sunken portion is surrounded by etched profiles (i.e. walls). Sections of the wafer have been cut through the wafer to form the resonator beam (denoted the "etched tie" in Figs. 5A-5C). The undercut was removed by a second etching stage (not shown). Optionally, the etched tie is formed by performing two chemical etching cycles in the first chemical etching stage using respective etching masks. The first chemical etching cycle forms the sunken profile and the second chemical etching cycle creates the through-cut trenches. Optionally, etching masks are laser-patterned etching masks. Fig. 5B shows a top and cross-section view of the quartz wafer after being partially coated with a chromium/gold coating that was deposited using a shadow mask. Fig. 5C shows a top and cross-section view of the quartz wafer after a pattern has been formed on the wafer by using laser ablation to remove unwanted parts of the chromium/gold coating. The laser ablation formed patterned pads and patterned conductors on the top surface of the quartz wafer, patterned conductors on two profiles of the sunken portion, and patterned electrodes on the tie. General It is expected that during the life of a patent maturing from this application many relevant chemical etching techniques, masks, lasers, laser ablation techniques, piezoelectric elements, MEMS, resonators, and dielectric substances will be developed and the scope of the terms chemical etching, mask, laser ablation, piezoelectric element, MEMS, resonator, and dielectric substance is intended to include all such new technologies a priori. The terms "comprises", "comprising", "includes", "including", "having" and their conjugates mean "including but not limited to". The term "consisting of" means "including and limited to". As used herein, singular forms, for example, "a", "an" and "the" include plural references unless the context clearly dictates otherwise. Within this application, various quantifications and/or expressions may include use of ranges. Range format should not be construed as an inflexible limitation on the – 21 – scope of the present disclosure. Accordingly, descriptions including ranges should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within the stated range and/or subrange, for example, 1, 2, 3, 4, 5, and 6. Whenever a numerical range is indicated within this document, it is meant to include any cited numeral (fractional or integral) within the indicated range. It is appreciated that certain features which are (e.g., for clarity) described in the context of separate embodiments, may also be provided in combination in a single embodiment. Where various features of the present disclosure, which are (e.g., for brevity) described in a context of a single embodiment, may also be provided separately or in any suitable sub-combination or may be suitable for use with any other described embodiment. Features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements. Although the present disclosure has been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. Accordingly, this application intends to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims. All references (e.g., publications, patents, patent applications) mentioned in this specification are herein incorporated in their entirety by reference into the specification, e.g., as if each individual publication, patent, or patent application was individually indicated to be incorporated herein by reference. Citation or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the present disclosure. In addition, any priority document(s) and/or document(s) related to this application (e.g., co-filed) are hereby incorporated herein by reference in its/their entirety. Where section headings are used in this document, they should not be interpreted as necessarily limiting.

Claims (23)

– 22 – CLAIMS:

1. A method of coating a dielectric wafer with a patterned metal layer, said wafer comprising a dielectric surface upon which said patterned metal layer is formed, comprising: forming at least one sunken portion in a dielectric wafer by performing a first chemical etching stage comprising at least one chemical etching of said dielectric wafer using respective etching masks; removing a final one of said etching masks from said dielectric wafer; performing a second chemical etching stage on said dielectric wafer; depositing a metal layer on said dielectric wafer; and forming a pattern on said metal layer by laser ablation.

2. The method of claim 1, wherein said dielectric wafer consists of a dielectric material.

3. The method of claim 1, wherein said dielectric wafer comprises a dielectric layer on a substrate, said metal pattern being formed on said dielectric layer.

4. The method of any one of claims 1-3, wherein an etching rate of said first chemical etching stage is larger than an etching rate of said second chemical etching stage.

5. The method of any one of claims 1-4, wherein said second chemical etching stage removes an undercut around said at least one sunken portion.

6. The method of any one of claims 1-5, wherein said second chemical etching stage is performed without a mask.

7. The method of any one of claims 1-6, wherein said metal pattern is formed on a top surface of said dielectric wafer and on a surface of said at least one sunken portion. – 23 –

8. The method of claim 7, wherein said metal pattern is further formed on at least one wall of said sunken portion, so as to form an electrical connection between said metal pattern on said top surface of said dielectric wafer and said metal pattern on said surface of said at least one sunken portion.

9. The method of any one of claims 1-8, wherein said metal layer is deposited on said dielectric wafer using a shadow mask.

10. The method of any one of claims 1-9, wherein said respective etching masks comprise a gold over chromium layer.

11. The method of any one of claims 1-10, wherein said metal pattern comprises a closed contour.

12. The method of any one of claims 1-11, wherein said dielectric wafer comprises quartz.

13. The method of any one of claims 1-12, further comprising aligning said etching mask on said dielectric wafer so as to obtain a sunken portion with sloped sides.

14. A piezoelectric element manufactured by the method of any one of claims 1-13.

15. A piezoelectric element according to claim 14, wherein said piezoelectric element is part of a microelectromechanical system (MEMS).

16. A method of preparing a dielectric wafer for laser ablation, comprising: forming at least one sunken portion in said dielectric wafer by performing a first chemical etching stage comprising at least one chemical etching of said dielectric wafer using respective etching masks; removing a final one of said etching masks from said dielectric wafer; and removing an undercut around said at least one sunken portion by performing a second chemical etching stage on said dielectric wafer. – 24 –

17. The method of claim 16, wherein said dielectric wafer consists of a dielectric material.

18. The method of claim 16, wherein said dielectric wafer comprises a dielectric layer on a substrate.

19. The method of any one of claims 16-18, further comprising, for at least one of said etching masks: coating a surface of said wafer with a metal layer; and forming said etching mask by removing a portion of said metal layer by laser ablation.

20. The method of one of claims 16-19, further comprising depositing a metal layer on a surface of said dielectric wafer.

21. The method of claim 20, wherein said metal layer is deposited on said dielectric wafer using a shadow mask.

22. The method of any one of claims 16-21, wherein an etching rate of said first chemical etching stage is larger than an etching rate of said second chemical etching stage.

23. The method of any one of claims 16-22, wherein said second chemical etching stage is performed without a mask. For the Applicants, REINHOLD COHN AND PARTNERS By: