IL156469A - Multi-channel reset integrator a/d converter - Google Patents

Description

156469 ,7-ji 1 453338 rn* A MULTI-CHANNEL RESET INTEGRATOR A/D CONVERTER FIELD AND BACKGROUND OF THE INVENTION The present invention relates to A/D converters in general and in Different types of integral A/D converters are available depending on the application on hand. One type of integral A/D converter employed for applications, for example, inertial navigation strapdown equipment, which require high accuracy, due to truncation effects, and no dead-zone is the V F converter. The main disadvantage of using V/F converters for such applications in view of each input channel requiring a dedicated A/D converter.

Therefore, there is a widely recognized need for, and it would be highly advantageous to have, an integral A/D converter for use in a multi- channel architecture which overcomes the above-mentioned deficiencies.

SUMMARY OF THE INVENTION The object of the present invention is for an integral A/D converter for use in multi-channel architectures, for example, inertial navigation strapdown equipment and the like.

Hence, according to the first aspect of the present invention, there is provided a reset integrator A/D converter comprising: (a) integrating means for integrating an input analog signal to provide an integrated analog output; (b) A/D conversion means for converting said integrated analog output to a digital signal; and (c) resetting means for resetting said integrating means after an integration of said input analog signal by providing a reset signal associated with said digital signal.

According to further features of the present invention, the reset integrator A/D further comprising a multiplexer for sampling a plurality of integrating means.

According to still further features, the resetting means provides a pulse width modulated reset signal and includes a one-shot mode timer. — b^ ■ There is also provided according to a second aspect of the present invention, a multi-channel reset integrator A/D converter, the A/D converter comprising: (a) a plurality of integrating means, each of said plurality of integrating means dedicated to an input channel of said A/D converter, each of said plurality of integrating means integrating an input analog signal to provide an integrated analog output; (b) multiplexing means for sampling said plurality of integrating means to provide a sampled integrated analog output of one of said plurality of integrating means; (c) A/D conversion means for converting said sampled integrated analog output to a digital signal; and (d) resetting means for resetting said one of said plurality of integrating means after being sampled by providing a reset signal associated with said digital signal.

According to still further features of the present invention, the resetting means provides pulse width modulated reset signals and includes a one-shot mode timer.

BRIEF DESCRIPTION OF THE DRAWINGS The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein: FIG. 1 shows a block diagram of the preferred embodiment of the multi-channel reset integrator A/D converter constructed and operative according to the teachings of the present invention; and FIG. 2 shows a schematic illustration of inertial navigation strapdown equipment employing the multi-channel reset integrator A/D converter of Figure 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is of a multi-channel reset integrator A/D converter for use in multi-channel architectures, for example, inertial navigation strapdown equipment and the like. In particular, the A/D converter is adapted for applications which require high accuracy,, no accumulated The principles and operation of the multi-channel reset integrator A/D converter according to the present invention may be better understood with reference to the drawings and the accompanying description.

Referring now to the drawings, Figure 1 shows the block diagram r ■ of the preferred embodiment of a multi-channel reset integrator A/D converter, generally designated 100, constructed and operative according to the teachings of the present invention. For the sake of clarity, multichannel reset integrator A/D converter 100 has been realized for a single input channel. However, multi-channel reset integrator A/D converter 100 0 can be implemented for any number of channels depending on factors including available hardware components, the rate of pulses along channels, and the like, as will described hereinbelow.

Multi-channel reset integrator A/D converter 100 includes an integrator 102 for integrating an input analog signal received along an input channel. Input analog signal can be a single continuous signal or a train of discrete signals. Integrator 102 is preferably a low offset^ integrator for example, the OP07A amplifier commercially available from PMI, USA. The OP07A amplifier has an offset change with temperature in the order of 0.6 μν/°Π such that it has an error of 3-5 μν, after temperature model compensation, which is equivalent to less than 0.5 ppm over 10V during operation. The input analog signal is typically converted from an input voltage to an input current by an input resistor 104. An input buffer 106 can be employed if a high impedance input is required.

The integrated analog signal is outputted by integrator 102 to an A/D converter 108 for conversion to a digital signal equivalent thereof. A/D converter 108 can be a 8 bit converter, a 12 bit converter, and the like depending on the required resolution of multi-channel reset integrator A/D converter 100. The digital signal is outputted via a microprocessor 110 employed for both translating the digital signal to physical data for transmission as output data and for determining the reset signal required to reset integrator 102 after the integration of the input analog signal. Multichannel reset integrator A/D converter 100 preferably employs an Intel 8086 microprocessor for microprocessor 112.

For multi-channel reset integrator A/D converter 100, the integrated analog signals from different input channels (not shown) are sampled by a multiplexer 112 also under the control of microprocessor 110. Channels can be sampled consecutively or according to any pre-determined sequence as provided by microprocessor 110. Multiplexer 112 includes at least as many input channels as multi-channel reset integrator A/D converter 100 includes input channels such that each input channel of multi-channel reset integrator A/D converter 100 has a dedicated input multiplexer channel. Furthermore, multiplexer 112 includes a temperature sensor 114 for measuring the local temperature of A/D converter 100 for enabling temperature compensation of integrated analog signals. A typical multiplexer for multi-channel reset integrator A/D converter 100 is the H1508A from Harris, USA.

Microprocessor 110 provides a flag to a current source 116 and a pulse time to a timer 118 for actuating current source 116 for providing the reset signal required to reset integrator 102. The pulse time is typically defined in terms of the number of clock cycles of timer 118. Hence, the reset signal is pulse width modulated in the sense that its pulse width is determined by the digital output equivalent of the integrated analog signal provided by integrator 102 since being last sampled by multiplexer 112. Timer 118 preferably operates in an one-shot mode. Alternatively, integrator 102 can be reset by a fixed time variable current pulse from an accurate variable current source actuated for a fixed period of time by microprocessor 112.

Multi-channel reset integrator A/D converter 100 preferably employs an Intel 8254 timer chip for timer 118 while current source 116 typically includes an 10V Analog Devices voltage reference, Vishay type accurate resistors, and a HI201HS high speed analog switch commercially available from Harris, USA. The error of the pulse width modulated reset signal is equivalent to 1 ppm and is due to the timing errors of microprocessor 112 and other components, for example, the analog switch, which are both within nanoseconds.

All in all, utilizing the above-mentioned hardware components, multi-channel reset integrator A/D converter 100 provides a bias drift accuracy of approximately 1 ppm, a non-linearity of approximately 100 ppm and a high conversion rate of approximately 2.5 KHz. Implementing other hardware components will achieve other specifications as well within the purview of those skilled in the art.

With reference now to Figure 2, multi-channel reset integrator A/D converter 100 can be particularly adapted for use with inertial navigation strapdown equipment, generally designated 200, and therefore is described below with respect to this application without in any way limiting the scope of the invention.

Inertial navigation strapdown equipment 200 includes an inertial sensors assembly including the following sub-assemblies: First, an array of Gyro X, Gyro Y and Gyro Z gyros, designated 202a, 202b and 202c, respectively, for providing X, Y and Z rate output. Second, an array of Accl X, Accl Y and Accl Z accelerators, designated 204a, 204b and 204c, respectively, for providing X, Y and Z acceleration output. And third, a temperature sensor 206 for compensating for temperature dependent errors of components 202 and 204.

Multi-channel reset integrator A/D converter 100 includes six integrators 102a-102f for integrating the input analog signals from Gyro X 202a, Gyro Y 202b and Gyro Z 202c and from Accl X 204a, Accl Y 204b and Accl Z 204c, respectively. It should be noted that integrators 102a-102f can possess different specifications in terms of integration time, capacity, and the like according to the different requirements of their input sources. Integrators 102a-102f are connected to channels #l-#6 of multiplexer 112.

Multiplexer 112 samples integrators 102a-102f consecutively or according to a predetermined sequence provided by microprocessor 110 to provide a sampled integrated analog output for conversion by A/D converter 108 to a digital signal. Multiplexer 112 also receives inputs from temperature sensors 114 and 206 for enabling correction of the sampled integrated analog output.

Microprocessor 110 controls current sources 116 and timers 118 to provide Gyro Reset Pulses to reset integrators 102a-102c and Accls Reset Pulses to reset integrators 102d-102f. Current sources 116 and timers 118 are preferably controlled in pairs such that a current source-timer pair is dedicated to reset each one of integrators 102a-102f. The reset pulses are preferably pulse width modulated reset pulses having their pulse widths determined by microprocessor 110. Microprocessor 110 determines the pulse width of each reset pulse as a function of the specifications of the sampled integrator and the digital output equivalent of the sampled integrated analog signal. Alternatively, multi-channel reset integrator A/D converter 100 can include a second multiplexer for providing reset pulses to integrators from a single timer and current source.

While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.

Claims (16)

156469/3

1. A multi-channel reset integrator A/D converter, said multi-channel reset integrator A/D converter comprising: (a) a plurality of integrators, each integrator of said plurality of integrators integrating an input analog signal to provide an integrated analog signal, and (b) exactly one resetter for providing a plurality of reset pulses, each reset pulse of said plurality of reset pulses for resetting a corresponding integrator of said plurality of integrators.

2. The multi-channel reset integrator A/D converter as in claim 1 wherein said resetter is configured to provide a pulse width modulated reset signal.

3. The multi-channel reset integrator A/D converter as in claim 1 wherein said resetter includes a one-shot mode time.

4. The multi-channel reset integrator A/D converter as in claim 1 wherein said resetter includes a current source.

5. The multi-chahnel reset integrator A/D converter of claim 1, further comprising: (c) a multiplexer for providing said plurality of reset pulses to said plurality of integrators, said each reset pulse to a corresponding integrator.

6. The reset integrator A/D converter as in claim 1, wherein said resetter includes exactly one current source configured to provide said each reset pulse.

7. The reset integrator A/D converter as in claim 6, wherein said resetter includes exactly one timer configured to actuate said current source. 156469/3 -11-

8. The reset integrator A/D converter as in claim 7, further comprising: (c) a microprocessor configured to provide: (i) a flag to said current source, and (ii) a pulse time to said timer for actuating said current source.

9. The multi-channel reset integrator A/D converter of claim 1, further comprising: (c) a multiplexer for sequentially sampling a plurality of said integrated analogue signals to provide a sampled integrated analog output of each of said plurality of integrators.

10. The multi-channel reset integrator A/D converter of claim 9, further comprising: (d) an A/D converter for converting said sampled integrated analog output to a digital signal.

11. The multi-channel reset integrator A/D converter of claim 10, wherein said each reset pulse has a product of a reset time multiplied by a reset current said product depending on a corresponding said digital signal.

12. The reset integrator A/D converter as in claim 10, wherein said A/D converter is exactly one A/D converter.

13. The reset integrator A/D converter as in claim 1, wherein said input analogue signal is a continuous signal.

14. The reset integrator A/D converter as in claim 1, wherein said input analogue signal is a train of discrete signals of arbitrary rate of pulses. 156469/3 -12-

15. The reset integrator A/D converter as in claim 1, wherein said each integrator is dedicated to an input channel of said multi-channel reset integrator A/D converter.

16. A multi-channel reset integrator A/D converter, said multi-channel reset integrator A/D converter comprising: (a) a plurality of integrators, each integrator of said plurality of integrators integrating an input analog signal to provide an integrated analog signal; (b) a resetter for providing a plurality of reset pulses, each reset pulse of said plurality of reset pulses for resetting a corresponding integrator of said plurality of integrators, and (c) a multiplexer for providing said each reset pulse to a corresponding integrator of said plurality of integrators. Mark M. Friedman Advocate, Patent Attorney Mo&lre Aviv Tower 54th floor 7 Jabotinsky 52520 Ramat Gan