IL154956A0 - Hardware instruction translation within a processor pipeline - Google Patents

Hardware instruction translation within a processor pipeline

Info

Publication number
IL154956A0
IL154956A0 IL15495601A IL15495601A IL154956A0 IL 154956 A0 IL154956 A0 IL 154956A0 IL 15495601 A IL15495601 A IL 15495601A IL 15495601 A IL15495601 A IL 15495601A IL 154956 A0 IL154956 A0 IL 154956A0
Authority
IL
Israel
Prior art keywords
processor pipeline
hardware instruction
instruction translation
translation
hardware
Prior art date
Application number
IL15495601A
Other languages
English (en)
Original Assignee
Advanced Risc Mach Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Risc Mach Ltd filed Critical Advanced Risc Mach Ltd
Publication of IL154956A0 publication Critical patent/IL154956A0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
IL15495601A 2000-10-05 2001-06-21 Hardware instruction translation within a processor pipeline IL154956A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0024396A GB2367651B (en) 2000-10-05 2000-10-05 Hardware instruction translation within a processor pipeline
PCT/GB2001/002743 WO2002029507A2 (en) 2000-10-05 2001-06-21 Hardware instruction translation within a processor pipeline

Publications (1)

Publication Number Publication Date
IL154956A0 true IL154956A0 (en) 2003-10-31

Family

ID=9900734

Family Applications (1)

Application Number Title Priority Date Filing Date
IL15495601A IL154956A0 (en) 2000-10-05 2001-06-21 Hardware instruction translation within a processor pipeline

Country Status (9)

Country Link
US (1) US20020083302A1 (zh)
EP (1) EP1330691A2 (zh)
JP (1) JP2004522215A (zh)
KR (1) KR20030040515A (zh)
CN (1) CN1484787A (zh)
GB (1) GB2367651B (zh)
IL (1) IL154956A0 (zh)
RU (1) RU2003112679A (zh)
WO (1) WO2002029507A2 (zh)

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US7769983B2 (en) * 2005-05-18 2010-08-03 Qualcomm Incorporated Caching instructions for a multiple-state processor
JP2007122626A (ja) * 2005-10-31 2007-05-17 Matsushita Electric Ind Co Ltd マイクロプロセッサ
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
GB2460280A (en) * 2008-05-23 2009-11-25 Advanced Risc Mach Ltd Using a memory-abort register in the emulation of memory access operations
CN101304312B (zh) * 2008-06-26 2011-07-20 复旦大学 一种适用于精简指令集处理器的加密单元
US8195923B2 (en) * 2009-04-07 2012-06-05 Oracle America, Inc. Methods and mechanisms to support multiple features for a number of opcodes
JP2011209905A (ja) * 2010-03-29 2011-10-20 Sony Corp 命令フェッチ装置、プロセッサ、および、プログラムカウンタ加算制御方法
FR2969787B1 (fr) * 2010-12-24 2013-01-18 Morpho Protection des applets
WO2012103359A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Hardware acceleration components for translating guest instructions to native instructions
WO2012103209A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Guest instruction to native instruction range based mapping using a conversion look aside buffer of a processor
WO2012103245A2 (en) 2011-01-27 2012-08-02 Soft Machines Inc. Guest instruction block with near branching and far branching sequence construction to native instruction block
WO2012103253A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Multilevel conversion table cache for translating guest instructions to native instructions
WO2012103373A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Variable caching structure for managing physical storage
WO2012103367A2 (en) 2011-01-27 2012-08-02 Soft Machines, Inc. Guest to native block address mappings and management of native code storage
WO2013132767A1 (ja) * 2012-03-09 2013-09-12 パナソニック株式会社 プロセッサ、マルチプロセッサシステム、コンパイラ、ソフトウェアシステム、メモリ制御システムおよびコンピュータシステム
EP2972798B1 (en) 2013-03-15 2020-06-17 Intel Corporation Method and apparatus for guest return address stack emulation supporting speculation
WO2014151652A1 (en) 2013-03-15 2014-09-25 Soft Machines Inc Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor
US20140281398A1 (en) * 2013-03-16 2014-09-18 William C. Rash Instruction emulation processors, methods, and systems
US9703562B2 (en) * 2013-03-16 2017-07-11 Intel Corporation Instruction emulation processors, methods, and systems
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems
CN105373414B (zh) * 2014-08-26 2018-11-20 龙芯中科技术有限公司 支持MIPS平台的Java虚拟机实现方法及装置
GB2553102B (en) * 2016-08-19 2020-05-20 Advanced Risc Mach Ltd A memory unit and method of operation of a memory unit to handle operation requests
US10802854B2 (en) 2019-08-30 2020-10-13 Alibaba Group Holding Limited Method and apparatus for interpreting bytecode instruction stream
CN110704108B (zh) * 2019-08-30 2020-08-14 阿里巴巴集团控股有限公司 解释执行字节码指令流的方法及装置

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Also Published As

Publication number Publication date
GB2367651B (en) 2004-12-29
JP2004522215A (ja) 2004-07-22
RU2003112679A (ru) 2004-11-27
EP1330691A2 (en) 2003-07-30
US20020083302A1 (en) 2002-06-27
GB0024396D0 (en) 2000-11-22
WO2002029507A2 (en) 2002-04-11
GB2367651A (en) 2002-04-10
WO2002029507A3 (en) 2003-05-22
KR20030040515A (ko) 2003-05-22
CN1484787A (zh) 2004-03-24

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