AU2001290111A1 - Instruction issue in a processor - Google Patents

Instruction issue in a processor

Info

Publication number
AU2001290111A1
AU2001290111A1 AU2001290111A AU9011101A AU2001290111A1 AU 2001290111 A1 AU2001290111 A1 AU 2001290111A1 AU 2001290111 A AU2001290111 A AU 2001290111A AU 9011101 A AU9011101 A AU 9011101A AU 2001290111 A1 AU2001290111 A1 AU 2001290111A1
Authority
AU
Australia
Prior art keywords
processor
instruction issue
issue
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001290111A
Inventor
Michael David May
Hendrik Lambertus Muller
Nigel Paul Smart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Bristol
Original Assignee
University of Bristol
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Bristol filed Critical University of Bristol
Publication of AU2001290111A1 publication Critical patent/AU2001290111A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/002—Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Advance Control (AREA)
AU2001290111A 2000-09-27 2001-09-26 Instruction issue in a processor Abandoned AU2001290111A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0023698 2000-09-27
GBGB0023698.4A GB0023698D0 (en) 2000-09-27 2000-09-27 Instruction issue in a processor
PCT/GB2001/004298 WO2002027478A1 (en) 2000-09-27 2001-09-26 Instruction issue in a processor

Publications (1)

Publication Number Publication Date
AU2001290111A1 true AU2001290111A1 (en) 2002-04-08

Family

ID=9900250

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001290111A Abandoned AU2001290111A1 (en) 2000-09-27 2001-09-26 Instruction issue in a processor

Country Status (3)

Country Link
AU (1) AU2001290111A1 (en)
GB (1) GB0023698D0 (en)
WO (1) WO2002027478A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2485538B (en) 2010-11-16 2013-12-25 Nds Ltd Obfuscated hardware multi-threading
FR3011354A1 (en) 2013-10-01 2015-04-03 Commissariat Energie Atomique METHOD FOR EXECUTING A MICROPROCESSOR OF A POLYMORPHIC BINARY CODE OF A PREDETERMINED FUNCTION
GB2551574B (en) * 2016-06-24 2019-11-27 Advanced Risc Mach Ltd An apparatus and method for generating and processing a trace stream indicative of instruction execution by processing circuitry
US11403107B2 (en) * 2018-12-05 2022-08-02 Micron Technology, Inc. Protection against timing-based security attacks by randomly adjusting reorder buffer capacity

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5745726A (en) * 1995-03-03 1998-04-28 Fujitsu, Ltd Method and apparatus for selecting the oldest queued instructions without data dependencies
US5710902A (en) * 1995-09-06 1998-01-20 Intel Corporation Instruction dependency chain indentifier
EP1122639A3 (en) * 1998-08-24 2002-02-13 Advanced Micro Devices, Inc. Mechanism for load block on store address generation and universal dependency vector/queue entry

Also Published As

Publication number Publication date
GB0023698D0 (en) 2000-11-08
WO2002027478A1 (en) 2002-04-04

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