IL128352A - שיטה לחילוץ קיבוליות והשראות תלת-מימדיות פרזיטיות בתרשימים של שבבי vlsi תת- מיקרונים - Google Patents

שיטה לחילוץ קיבוליות והשראות תלת-מימדיות פרזיטיות בתרשימים של שבבי vlsi תת- מיקרונים

Info

Publication number
IL128352A
IL128352A IL12835299A IL12835299A IL128352A IL 128352 A IL128352 A IL 128352A IL 12835299 A IL12835299 A IL 12835299A IL 12835299 A IL12835299 A IL 12835299A IL 128352 A IL128352 A IL 128352A
Authority
IL
Israel
Prior art keywords
parasitics
wiring
recited
wire
database
Prior art date
Application number
IL12835299A
Other languages
English (en)
Other versions
IL128352A0 (en
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Ibm filed Critical Ibm
Publication of IL128352A0 publication Critical patent/IL128352A0/xx
Publication of IL128352A publication Critical patent/IL128352A/he

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
IL12835299A 1998-04-20 1999-02-03 שיטה לחילוץ קיבוליות והשראות תלת-מימדיות פרזיטיות בתרשימים של שבבי vlsi תת- מיקרונים IL128352A (he)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/062,853 US6175947B1 (en) 1998-04-20 1998-04-20 Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization

Publications (2)

Publication Number Publication Date
IL128352A0 IL128352A0 (en) 2000-01-31
IL128352A true IL128352A (he) 2002-02-10

Family

ID=22045268

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12835299A IL128352A (he) 1998-04-20 1999-02-03 שיטה לחילוץ קיבוליות והשראות תלת-מימדיות פרזיטיות בתרשימים של שבבי vlsi תת- מיקרונים

Country Status (2)

Country Link
US (1) US6175947B1 (he)
IL (1) IL128352A (he)

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US6330704B1 (en) * 1999-02-09 2001-12-11 Coyote Systems, Inc. Method and apparatus for three dimensional interconnect analysis
US6381730B1 (en) * 1999-07-09 2002-04-30 Sequence Design, Inc. Method and system for extraction of parasitic interconnect impedance including inductance
US6363516B1 (en) * 1999-11-12 2002-03-26 Texas Instruments Incorporated Method for hierarchical parasitic extraction of a CMOS design
US6542834B1 (en) * 1999-11-24 2003-04-01 Lsi Logic Corporation Capacitance estimation
US6845346B1 (en) * 1999-12-09 2005-01-18 Intel Corporation Iterative method of parasitics estimation for integrated circuit designs
US6434724B1 (en) * 2000-03-18 2002-08-13 Hewlett-Packard Company Method for extracting inductance parameters from a circuit design
JP2002164432A (ja) * 2000-11-24 2002-06-07 Mitsubishi Electric Corp 半導体回路抽出装置、自動配置配線装置、およびその方法、ならびにライブラリ流通システム
US6957410B2 (en) * 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US6567966B2 (en) * 2001-02-14 2003-05-20 Agilent Technologies, Inc. Interweaved integrated circuit interconnects
JP2002259485A (ja) * 2001-03-02 2002-09-13 Fujitsu Ltd Ｌｓｉ設計工程におけるｌｃｒ抽出方法及びｌｃｒ抽出を行うコンピュータプログラム
DE10116328A1 (de) * 2001-04-02 2002-10-17 Infineon Technologies Ag Verfahren zur Verifikation eines Layouts einer integrierten Schaltung mit Hilfe eines Rechners sowie dessen Anwendung zur Herstellung einer integrierten Schaltung
US6588002B1 (en) * 2001-08-28 2003-07-01 Conexant Systems, Inc. Method and system for predictive layout generation for inductors with reduced design cycle
US6618846B2 (en) * 2001-08-31 2003-09-09 Synopsys, Inc. Estimating capacitance effects in integrated circuits using congestion estimations
JP2003108622A (ja) * 2001-09-27 2003-04-11 Nec Corp 配線モデル化手法、配線モデル、配線モデルの抽出方法及び配線設計手法
US6763503B1 (en) * 2001-11-20 2004-07-13 Sun Microsystems, Inc. Accurate wire load model
US6931613B2 (en) 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
JP4057928B2 (ja) * 2003-02-12 2008-03-05 株式会社日立ハイテクノロジーズ 半導体パターン評価システム
US7231618B2 (en) * 2004-04-22 2007-06-12 Optimal Corporation Fringe RLGC model for interconnect parasitic extraction
US8095903B2 (en) * 2004-06-01 2012-01-10 Pulsic Limited Automatically routing nets with variable spacing
US7749336B2 (en) * 2005-08-30 2010-07-06 Indium Corporation Of America Technique for increasing the compliance of tin-indium solders
US7712068B2 (en) * 2006-02-17 2010-05-04 Zhuoxiang Ren Computation of electrical properties of an IC layout
US20080028353A1 (en) * 2006-07-18 2008-01-31 Ning Lu Method for treating parasitic resistance, capacitance, and inductance in the design flow of integrated circuit extraction, simulations, and analyses
US7761835B2 (en) * 2006-12-11 2010-07-20 Elpida Memory, Inc. Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters
US7581201B2 (en) * 2007-02-28 2009-08-25 International Business Machines Corporation System and method for sign-off timing closure of a VLSI chip
US7669152B1 (en) 2007-03-13 2010-02-23 Silicon Frontline Technology Inc. Three-dimensional hierarchical coupling extraction
US8826207B2 (en) * 2007-09-17 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of generating technology file for integrated circuit design tools
JP2009217366A (ja) * 2008-03-07 2009-09-24 Nec Electronics Corp 配線モデルライブラリ構築装置及び構築方法、レイアウトパラメータ抽出装置及び抽出方法
JP2010073137A (ja) * 2008-09-22 2010-04-02 Nec Electronics Corp 半導体集積回路設計方法及び設計プログラム
US20100122223A1 (en) * 2008-11-09 2010-05-13 International Business Machines Corporation Techniques for Computing Capacitances in a Medium With Three-Dimensional Conformal Dielectrics
US8146032B2 (en) * 2009-01-30 2012-03-27 Synopsys, Inc. Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs
US9892218B2 (en) * 2016-04-01 2018-02-13 Synopsys, Inc. Parasitic-aware blockage
US10585999B2 (en) 2018-01-12 2020-03-10 Seagate Technology Llc Selection of die and package parasitic for IO power domain
US11250196B2 (en) * 2018-08-31 2022-02-15 Siemens Industry Software Inc. Conductor subdivision in physical integrated circuit layout for parasitic extraction
US11176308B1 (en) * 2020-06-19 2021-11-16 International Business Machines Corporation Extracting parasitic capacitance from circuit designs
US11314916B2 (en) 2020-07-31 2022-04-26 International Business Machines Corporation Capacitance extraction

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US5497334A (en) * 1993-02-19 1996-03-05 International Business Machines Corporation Application generator for use in verifying a hierarchical circuit design
JP2800881B2 (ja) 1995-07-31 1998-09-21 日本電気株式会社 配線寄生負荷算出方法
US5831870A (en) * 1996-10-07 1998-11-03 International Business Machines Corporation Method and system for characterizing interconnect data within an integrated circuit for facilitating parasitic capacitance estimation

Also Published As

Publication number Publication date
US6175947B1 (en) 2001-01-16
IL128352A0 (en) 2000-01-31

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