IL122522A0 - Computer system for the transfer of real time loss sensitive and non-real time data - Google Patents

Computer system for the transfer of real time loss sensitive and non-real time data

Info

Publication number
IL122522A0
IL122522A0 IL12252297A IL12252297A IL122522A0 IL 122522 A0 IL122522 A0 IL 122522A0 IL 12252297 A IL12252297 A IL 12252297A IL 12252297 A IL12252297 A IL 12252297A IL 122522 A0 IL122522 A0 IL 122522A0
Authority
IL
Israel
Prior art keywords
real time
transfer
computer system
time data
loss sensitive
Prior art date
Application number
IL12252297A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IL122522A0 publication Critical patent/IL122522A0/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
IL12252297A 1996-12-06 1997-12-09 Computer system for the transfer of real time loss sensitive and non-real time data IL122522A0 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/760,914 US5901296A (en) 1996-12-06 1996-12-06 Distributed scheduling for the transfer of real time, loss sensitive and non-real time data over a bus

Publications (1)

Publication Number Publication Date
IL122522A0 true IL122522A0 (en) 1998-06-15

Family

ID=25060557

Family Applications (1)

Application Number Title Priority Date Filing Date
IL12252297A IL122522A0 (en) 1996-12-06 1997-12-09 Computer system for the transfer of real time loss sensitive and non-real time data

Country Status (6)

Country Link
US (1) US5901296A (xx)
EP (1) EP0847012A2 (xx)
JP (1) JPH10177546A (xx)
KR (1) KR100261381B1 (xx)
IL (1) IL122522A0 (xx)
TW (1) TW373136B (xx)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6553476B1 (en) * 1997-02-10 2003-04-22 Matsushita Electric Industrial Co., Ltd. Storage management based on predicted I/O execution times
US6012116A (en) * 1997-12-31 2000-01-04 Sun Microsystems, Inc. Apparatus and method for controlling data, address, and enable buses within a microprocessor
US6701397B1 (en) 2000-03-21 2004-03-02 International Business Machines Corporation Pre-arbitration request limiter for an integrated multi-master bus system
JP3535068B2 (ja) * 2000-03-30 2004-06-07 富士通株式会社 マルチチャネル処理の制御装置およびマルチチャネル処理の制御方法
JP2001344153A (ja) * 2000-05-30 2001-12-14 Nec Corp マルチプロセッサシステムのキャッシュメモリ制御装置
JP4186421B2 (ja) * 2001-02-23 2008-11-26 株式会社日立製作所 パケット処理装置
JP2005092780A (ja) * 2003-09-19 2005-04-07 Matsushita Electric Ind Co Ltd リアルタイムプロセッサシステム及び制御方法
WO2005096162A1 (ja) * 2004-03-18 2005-10-13 Matsushita Electric Industrial Co., Ltd. アービトレーション方法及び装置
JP4974508B2 (ja) * 2005-10-28 2012-07-11 キヤノン株式会社 バスマスタ装置、バス調停装置及びバス調停方法
CN101426055B (zh) * 2008-11-03 2012-05-23 陈伟 一种分布式调度通讯装置
CN103870327A (zh) * 2012-12-18 2014-06-18 华为技术有限公司 一种实时多任务调度方法和装置
KR102372488B1 (ko) * 2015-05-29 2022-03-10 삼성전자 주식회사 무선 패킷 네트워크를 위한 스케줄링 방법 및 장치
DE102015116419A1 (de) 2015-09-28 2017-03-30 Bayerische Motoren Werke Aktiengesellschaft Robuste Prioritätsreihenfolge für Nachrichten auf einem Bussystem

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814974A (en) * 1982-07-02 1989-03-21 American Telephone And Telegraph Company, At&T Bell Laboratories Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements
US4924380A (en) * 1988-06-20 1990-05-08 Modular Computer Systems, Inc. (Florida Corporation) Dual rotating priority arbitration method for a multiprocessor memory bus
US5276818A (en) * 1989-04-24 1994-01-04 Hitachi, Ltd. Bus system for information processing system and method of controlling the same

Also Published As

Publication number Publication date
JPH10177546A (ja) 1998-06-30
EP0847012A2 (en) 1998-06-10
KR19980063618A (ko) 1998-10-07
TW373136B (en) 1999-11-01
KR100261381B1 (ko) 2000-07-01
US5901296A (en) 1999-05-04

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