IE990184A1

IE990184A1 - A data acquisition circuit

Info

Publication number: IE990184A1
Application number: IE990184A
Authority: IE
Inventors: Mcgirr Niall; Mcnelis Aaron; Diarmuid Corry; Bonner Fergal
Original assignee: Nabila Ltd
Priority date: 1999-03-05
Filing date: 1999-03-05
Publication date: 2000-09-06
Also published as: GB2347569A; GB9905477D0; GB2347569B

Abstract

Multiple sensor input analog channels have independent signal conditioning (SC) and analog to digital conversion (ADC). A digital filter comprises an FPGA, and thus has a much smaller gate count than usual. Also, it does not suffer from power-on-reset problems. A counter controls a core state machine to achieve cascading of filter stages and selection of a single output. Very fast multiplication is achieved by using fixed coefficients and results in a look-up table in EEPROM. <Figure 4>

Description

A Data Acquisition Circuit Multiple sensor input analog channels have independent signal conditioning (SC) and analog to digital conversion (ADC). A digital filter comprises an FPGA, and thus has a much smaller gate count than usual. Also, it does not suffer from power-on-reset problems. A counter controls a core state machine to achieve cascading of filter stages and selection of a single output. Very fast multiplication is achieved by using fixed coefficients and results in a look-up table in EEPROM. .

Claims

1. A data acquisition circuit comprising: a plurality of input analog channels, each comprising a signal conditioner and each having an independent sample rate and filter cut-off point, a digital filter comprising a state machine controlled by a counter for multiplexing the channels, performing digital filtering in cascaded stages at sampling rates which are successive binary sub-divisions of the preceding stage beginning with a primary sampling rate, and for selecting an output from one of the stages.

2. A circuit as claimed in claim 1, wherein the digital filter comprises an FPGA. 3. A circuit as claimed in claim 1 or 2, wherein there is a set of fixed multiplier coefficients for the digital filter multipliers. 4. A circuit as claimed in claim 3, wherein the coefficients are stored in a separate read only memory. 5. A circuit as claimed in any preceding claim, wherein the read only memory stores a look up table of all possible multiplication results, the table being addressable with an input register value. 6. A circuit as claimed in any preceding claim, wherein the counter comprises means for selecting which cascading filter stage provides the output for each channel. 7. A circuit as claimed in claim 6, wherein the output is written to a register in the digital filter. IE 9901B4 -138. A circuit as claimed in any of claims 4 to 7, wherein the read only memory stores values for linearisation of the analog to digital converters and channel gain settings. 5 9. A circuit as claimed in any preceding claim, wherein the counter controls the state machine via decoders. 10. A circuit as claimed in claim 9, wherein the decoders include a cascading stage decoder, a read pointer decoder, and a write pointer decoder. 11. A circuit as claimed in any preceding claim, wherein all logic blocks of the digital filter are in hardware. 12. A data acquisition circuit substantially as described with reference to the 15 drawings. 13. A data acquisition system comprising a circuit as claimed in any preceding claim mounted in a rugged housing. 25 '

3. /6 CLOCK INPUT ...............—· - ------------------ -........ DIGITAL FILTER Fp ___________________________i _______ OUTPUT 0 Fp/2 DIGITAL FILTER .....- ............................:----------- OUTPUT 1 Fp/4 DIGITAL FILTER ............................. OUTPUT 2 Fp/8 DIGITAL FILTER