IE911059A1

IE911059A1 - Process and apparatus for producing conductive layers or¹structures for circuits integrated on the very largest scale

Info

Publication number: IE911059A1
Application number: IE105991A
Authority: IE
Original assignee: Siemens Ag
Priority date: 1990-03-30
Filing date: 1991-03-28
Publication date: 1991-10-09
Also published as: EP0448763A1; JPH04225223A; JP3200085B2; KR100200911B1

Abstract

In a process for manufacturing conductive layers or structures for highly integrated circuits, at least two process steps are carried out immediately one after the other in different chambers (1 to 6) of a high-vacuum system, without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the process steps yields markedly better layer properties and makes possible, in particular, simple and reliable multistage processes for manufacturing conductive layers which assist multilayer interconnection on the semiconductor substrate. An apparatus used comprises several high-vacuum process chambers (1 to 6), at least one high-vacuum distribution chamber (7) linking the process chambers and at least two high-vacuum storage chambers (8, 9) for semiconductor substrates.

Description

Si emens Aktiengesellschaft Process and apparatus for producing conductive layers or structures for circuits integrated on the very largest scale The invention relates to a multi-stage process 5 for producing conductive layers or structures for circuits integrated on the very largest scale on a semiconductor substrate and an apparatus for carrying out the process.

In order to achieve as high an integration level 10 as possible when producing integrated circuits in microelectronics, it is known to arrange the conductive connections between the individual electrical elements of the integrated circuit in superimposed planes (so-called multi-layer metallisation), and at the same time to reduce the lateral dimensions of structures inside a plane. The technical realisation of this task requires a thoroughgoing planing of the vertical layer sequence, as is explained in detail in the article by A. Saxena and D. Pramanik in Solid State Technology, Oct. 1986, pages 95 to 100. Also described in this article are some processes according to the prior art with which conductive and nonconductive layers and structures can be produced on a semiconductor substrate, normally a silicon substrate, which at least partially planarise the semi25 conductor surface and thus support the multi-layer metallisation.

Common to all methods is that a plurality of different processes have to be carried out sequentially in order to produce conductive connections which support the multi-layer metallisation. This is explained below with reference to an example: For the purpose of producing printed conductors, it is conventional to apply layers of aluminium or an aluminium alloy to the surface of the semiconductor substrate by means of a sputtering process. In the case of narrow structures, for example contact holes, layers produced in such a fashion have a poor edge coverage, as a result of which the height differences occurring on the semiconductor surface are not planed but are even further - 2 enlarged. Consequently, it is either necessary for the sputtered aluminium layer to be subjected to aftertreatment, for example flowing by means of brief heating, or it is necessary to compensate the height difference by a subsequently applied non-conductive layer. In the first case, the exposure of the aluminium layer to air that is required according to the prior art leads to a passivating layer, which contains aluminium oxide and complicates the flowing process; in the second case, a plurality of expensive processes must be used to produce a planarising insulating layer (e.g. deposition of silicon oxide - spinning on an auxiliary layer and baking out - etching back the auxiliary layer and the silicon oxide layer - renewed deposition of silicon oxide).

Furthermore, this second variant has the disadvantage that the printed conductors of the immediately subsequent conductive layer cannot be arbitrarily arranged; in particular, the contact holes respectively connecting two printed conductor planes cannot be stacked above one another.

Both for reasons of the electrical reliability of the printed conductors and for the purpose of supporting the multi-layer metallisation, the aim is therefore a better edge coverage of the deposited conductive layers.

For this purpose, it is known to produce aluminium layers with the aid of chemical deposition from the gas phase (so-called CVD process).

It is possible here to use triisobutylaluminium (TIBA) as starting substance, although the process is attended by substantial disadvantages (see D. Beach, S. Blum, F. LeGoues in Journal of Vacuum Science and Technology, A7 (5), 1989, pages 3117 to 3118): dangerous nature of the starting compound accompanied simultaneously by a low degree of conversion; instability of TIBA at temperatures above 50’C; simple production of an aluminium alloy impossible; low deposition rate, which requires the use of a multi-wafer facility (batch system); need for a seeding of the surface to be coated, the uniformity of which can hardly be guaranteed on - 3 structured surfaces. In sum, it is a matter of a technically very difficult process, which to the [sic] delivers aluminium layers having a high defect density and a deficient electromigration resistance. For this reason, the use of trimethylamine aluminium [sic] as starting substance in a CVD process is recommended in the article cited above. In order to produce coherent aluminium layers therewith, it is likewise necessary, however, to have a preliminary seeding with titanium chloride, and uniformity of the aluminium layer is not guaranteed until starting from a thickness of 200 nm.

It is therefore the object of the invention to specify a process for producing conductive layers and structures for circuits integrated on the very largest scale, which does not have the outlined disadvantages of the known processes. The layers and structures produced in this way are to possess the electrical and mechanical characteristics necessary for circuits integrated on the very largest scale, and are to have a low transition resistance to the underlying conductive layers as well as a good edge coverage. Preferably they are to support the multi-layer metallisation, i.e. there is no need for further expensive processes to planarise the semiconductor surface. Furthermore, an apparatus is to be specified with which such a method can be carried out.

This object is achieved by means of a process in accordance with Patent Claim 1 and an apparatus in accordance with Patent Claim 9. Developments of the invention are the subject of subclaims.

By means of the multi-stage process according to the invention, in which a plurality of process stages relevant to the metallisation are carried out in direct sequence while the high-vacuum conditions are maintained, it is possible to produce conductive layers and struc35 tures which possess clearly better electrical and mechanical characteristics and, moreover, give particularly effective support to the multi-layer metallisation. Due to the permanent residence of the semiconductor substrate in the high vacuum and to the most - 4 thoroughgoing exclusion, bound up therewith, of environmental influences such as traces of oxygen or water vapour between the process stages as well, it happens inter alia that: - the reoxidation of freshly cleaned surfaces is prevented, as a result of which reproducibly low transition resistances are achieved and seeding problems are avoided, the defect density is reduced in the deposited 10 layers, the adhesion of the individual layers is improved and their mechanical stress is diminished, the prevention of a natural oxide makes it possible for an alloying component to be applied immediately afterwards on a deposited aluminium layer and to diffuse, the particular seeding is substantially facilitated due to the suppressed formation of natural oxide skins on the layers.

These improved layer characteristics lead, in turn, to the fact that further processes can be integrated, i.e. can be carried out directly in advance or following, likewise in the same high-vacuum facility without interrupting the high-vacuum conditions for the semiconductor substrate. As a result, the required process times, the danger of contamination of the semiconductor substrates to be treated and other defects due to external influences are minimised.

The invention is represented in more detail below with reference to exemplary embodiments.

FIG. 1 shows an exemplary embodiment of the apparatus according to the invention in a diagrammatic representation.

The multi-stage process according to the inven35 tion is carried out in a high-vacuum facility represented in FIG. 1, which consists of at least two high-vacuum process chambers 1-6, at least one high-vacuum distribution chamber 7 and at least two high-vacuum supply chambers 8, 9. All supply and process chambers have a - 5 high-vacuum-capable connection to the distribution chamber 7, which is arranged centrally in this exemplary embodiment, and are isolated from and independent of one another in high-vacuum terms. In the case of the maximum leak rates specified below (unit: mbar x 1 x sec'1), it is possible to achieve at least the base pressures (unit: mbar) specified as the second quantity, in the individual chambers: supply chambers (5 x 106/l x 106); distribution chamber (5 x 10'7/l x 10'7); process chambers (5 x 10'7/l x 10'7). The individual process chambers 1-6 are designed specifically for individual processes and can be small in terms of volume. The generally wafershaped silicon substrates, which are to be treated and are provided with partly finished integrated circuits, individually, sequentially and smoothly traverse the various process chambers 1-6, or reside in an intermediate store of the distribution chamber 7 for the purpose of determining the traverse times or process parameters. The course and sequence of the individual process steps in the various process chambers are controlled by a process computer (not represented).

The individual process chambers 1 to 6 can be arranged, for example, in the following way: 1: plasma etching chamber, 2: chamber for sputtering a metallic contact layer, 3: chamber for CVD processes, for example for depositing a layer acting as a barrier, 4: chamber for CVD deposition of a layer acting as a printed conductor, 5: chamber for sputtering a covering layer, 6: chamber for a temperature step (RTP), possibly with optical support (ROA). In this process, the chambers are fitted with the devices that are known to be necessary for the particular processes, such as, for example, gas inlets, electrodes for plasma etching processes or plasma-supported deposition processes, metal targets, heating devices, etc.

The apparatus according to the invention is also suitable for multi-stage processes for producing nonconductive layers, for example planarising insulating layers between the printed conductor planes. The process - 6 chambers 1-6 are then to be constructed in accordance with the requirements, (e.g. for plasma-supported CVD processes, sputter etching processes, plasma etching processes, heat treatments). A substantial advantage then consists in the avoidance of the taking up of moisture in the insulating layers between the process stages, as a result of which, for example, there is no need to bake out the layers, as is otherwise required.

Small transfer times between two process chambers 10 via the central distribution chamber 7, of approximately 20 sec facilitate high traverse times without human influences or errors. During treatment of the silicon substrates from one supply chamber 8, the other supply chamber 9 can be loaded from outside with new silicon substrates. Due to this and to the use of a multi-chamber facility with a central distribution chamber, a permanent, continuous processing is possible in conjunction with a sequential succession of different processes. Important economic and production aspects bound up therewith are the reduction of the multiplicity of facilities, savings in the area required in a clean room and the guaranteeing of short traverse times.

Exemplary embodiments for the process according to the invention: 1. Production of aluminium printed conductors This multi-stage process consists, in an advantageous way, of the following process stages al-a6: (aj Cleaning of the surface to be coated The natural oxide of the free silicon surfaces is removed by means of a plasma-supported etching process in the first process chamber using known processes, for example by means of CF4 as etching gas. (a2) Applying a contact layer In order to improve the electrical contact with the underlying silicon areas, a titanium layer of approximately 10 to 100 nm thickness is applied as contact layer, for example. This can be carried out by means of known sputtering processes or CVD processes; process chamber 2 is constructed accordingly depending upon the desired production process. When a CVD process is used, a suitable titanium-containing starting compound is introduced into the process chamber 2 by means of a carrier gas or by suction, and, thermally excited at a process pressure of 0.1 to 100 mbar and a temperature of approximately 200 to 450 °C. In addition, an excitation can be performed by a plasma. (a3) Application of a barrier layer In order to prevent interdiffusion of aluminium and silicon, a titanium nitride layer acting as a barrier is advantageously applied in a further process chamber 3. The underlying titanium layer serves simultaneously as an adhesion layer for the barrier layer consisting of titanium nitride. According to the invention, in order to produce the titanium nitride layer use is made of a CVD process which employs as starting substance a nitrogencontaining organic titanium compound, which is excited thermally, optically and or [sic] by a plasma, and envisages the addition of a reducing agent in the case of purely thermal excitation. At process temperatures in the range from 200 to 550°C, this process already delivers titanium nitride layers having particularly advantageous characteristics, such as conformity, low stress, very good edge coverage, high barrier effect, good conductivity, etc. (aA) Application of a CVD aluminium layer The application of the aluminium layer by means of CVD is performed in the temperature range from 200 to 450 eC at a pressure of 0.1 to 100 mbar. An organic aluminium compound is used as the starting substance, for example dimethylaluminium hydride HA1(CH3)2, trimethylamine aluminium hydride (A1H3*N(CH3)3 or triethylaluminium Al(Et)3, or the like. These compounds possess evaporation temperatures in the range from 5 to 100°C, and are - 8 introduced into the process chamber 4 by means of a carrier gas or by suction. The characteristics of the aluminium, such as grain size or surface roughness can be influenced both by suitable choice of the starting components and by variation of the process parameters. (a5) Application of a layer delivering alloying components In order to form an aluminium alloy, a layer con10 taining copper, titanium, palladium or silicon is sputtered or deposited by means of CVD. Its thickness is determined by the desired alloying ratio.

The application of the layer can also be performed before the application of the aluminium layer. (a6) Alloying the aluminium layer The desired aluminium alloy is formed by means of a thermal step, for example by means of Rapid Thermal Processing (RTP). The diffusion of the alloying component is preferably performed in this regard at temperatures below 500eC by briefly heating the semiconductor substrates (10 to 80 sec) in an inert gas atmosphere such as helium or hydrogen. The thermal step can also be performed with optical support (Rapid Optical Annealing, ROA) at tempera25 tures up to 450°C for 10 to 120 sec.

This exemplary embodiment of the process according to the invention enables layers to be deposited uniformly and with very good edge coverage even in the narrowest structures. This is made possible by the choice of suitable CVD or sputtering processes and by means of deposition parameters in the range of the surfacecontrolled reaction kinetics, and of the [sic] fact that the layer components to be deposited in the case of the CVD process are already present in a single starting molecule. As a result, such a metallisation process is preferably suitable for multi-layer metallisation.

The use of a CVD process for the deposition of the titanium nitride barrier layer of nitrogen-containing organic titanium compounds delivers a particularly good - 9 barrier layer, so that the otherwise necessary saturation of the grain boundaries with oxygen can be eliminated, and the integration with the subsequent aluminium deposition is made possible. The production process for the aluminium layer does not employ dangerous or highly reactive starting substances. The particular advantage resides in the combination of the titanium nitride deposition with an immediately following aluminium deposition without interruption of the high vacuum, since thereby a seeding layer for the aluminium deposition is, contrary to expectation, not required. Aluminium is deposited very uniformly and independently of the underlying material on the non-oxidised titanium nitride surface. As a result, there is a smaller average alu15 minium grain size, smoother layers and a lower defect density of the aluminium layer compared with previously known aluminium deposition processes. The electromigration resistance and the reliability of the metallisation is [sic] also substantially better, and may be even further increased, for example, by applying a titanium nitride covering layer to, or of corresponding interlayers inside the aluminium layer. Copper or titanium as underlying layer, interlayer or covering layer also effect a further improvement of the electrical charac25 teristics of the metallisation, preferably in conjunction with thermal steps. The production of aluminium alloy layers can also be performed in situ by decomposition of suitable starting compounds (for example A1H3*N(CH3)3 + Si2H6) in a CVD process.

A further advantage of the described metallisation process, which is important preferably in the case of multi-layer metallisation, consists in that all the deposition steps can proceed at temperatures below 450°C, that is to say also on semiconductor substrates already having an aluminium layer.

A simplified exemplary embodiment of the process according to the invention is restriction to the process stages (a3) and (a*). Due to the integration of these two process stages in a high-vacuum facility while maintaining - 10 the high-vacuum conditions for the semiconductor substrate, the essential advantages bound up with the invention are already achieved. 2. Production of silicides Silicides are used in silicon technology in order to produce temperature-stable low-resistance printed conductors and contacts, preferably also self-adjusted contacts (so-called salicides); this is explained in more detail, for example, in the book by D. Widmann, H. Mader and H. Friedrich, Technologie hochintegrierter Schaltungen [Technology of Highly Integrated Circuits], Springer Verlag 1988, pages 95 to 98. The production of silicides and salicides is possible in a simple fashion by means of the process according to the invention with the use of the process stages (bx) to (b3); furthermore, by means of a further process stage (b^) it is possible immediately thereafter to undertake a selective metal deposition, for example in order to fill up contact holes : (b^ Pretreatment of the surface in [sic] the first process chamber 1, the surface to be coated is cleaned by bombardment with, for example, low-energy argon ions (approximately 100 eV) ? in this process the natural oxide is removed preferably in the later contact hole area and on the polysilicon of gate contacts. Simultaneously with this cleaning of the surface, an insertion of argon atoms of approximately 1013 atoms per cm3 is performed. The silicon is pre-amorphised.

Consequently, a uniform siliconising of the layers is achieved independently of the doping. (b2) Sputtering of a metal layer In a further or the same chamber of the high-vacuum facility, the metal layer required for the silicide formation is deposited on the freshly cleaned surface by sputtering from a target of ultrapure metal without interruption of the vacuum. The layer thickness is dependent upon the geometrical relationships of the contact hole, the doping profile - 11 and the pretreatment, and is typically between 40 and 80 nm. (b3) Heat treatment The silicide formation is performed by means of 5 Rapid Thermal Processing or Rapid Optical Annealing (RTP or ROA), for example at 650 to 700eC in a nitrogen atmosphere for 30 sec in a chamber of the high-vacuum facility. By maintaining the high-vacuum condition, no oxide layer is formed on the metal layers deposited in accordance with (b2). (bj Selective metal deposition Without interrupting the high vacuum, it is now possible, in turn, by means of a CVD process to carry out a selective metal deposition of, for example, tungsten or aluminium on the freshly siliconised contacts without seeding delays and with excellent selectivity. For this purpose, use is made of a further chamber of the high-vacuum facility and of a selective deposition process corresponding to the prior art. 3. Selective metal deposition The already described process stages (ax) and (b4) can be combined as a further exemplary embodiment of the invention. A selective metal deposition of, for example, tungsten or aluminium on freshly cleaned contacts is carried out by means of this multi-stage process; here, it can be a matter of contacts with underlying silicon or with underlying metallic printed conductors. The planarisation of the surface is achieved by completely filling up the contacts.

Independently of the particular exemplary embodiment, the inventive concept resides in the combination of at least two process stages in conjunction with the maintenance of the high-vacuum conditions for the semi35 conductor substrate; the multi-chamber high-vacuum facility according to the invention is required in order to carry out the process. In this regard, the individual process stages can be carried out according to the prior art, this applies, preferably, to the process stages (ax), ( a2 ) t ( a5 ) · embodiments (a4) is new combination - 12 (a6), (bj- (b4) described in the exemplary . By contrast, the described process stage and the process stage (a3) together with the of (a3) and (a4) is new and inventive.

Claims

1. Patent claims

1. Multi-stage process for producing conductive layers or structures for circuits integrated on the very largest scale on a semiconductor substrate, consisting of 5 at least two process stages, which are carried out in direct sequence in at least two chambers of a high-vacuum facility while maintaining the high-vacuum conditions for the semiconductor substrate.

2. Process according to Claim 1, characterised by 10 the process stages (a 3 ) applying a barrier layer to the surface of the semiconductor substrate, (a 4 ) applying a printed conductor layer to the barrier layer. 15

3. Process according to one of Claims 1 to 2, characterised by the further process stages (a 2 ) applying a contact layer before applying the barrier layer and/or (a x ) cleaning the surface of the semiconductor substrate 20 before applying the barrier layer or the contact layer and/or (a 5 ) applying a layer, which delivers alloying components, before, after or in alternation with the application of the printed conductor layer and/or 25 (a 6 ) heat treatment.

4. Process according to one of Claims 1 to 3, characterised in that the process stages are carried out as follows: (a x ) plasma etching process for removing oxides 30 (a 2 ) applying a titanium layer of 10 to 100 nm thickness by means of a sputtering process, or of chemical deposition from the gas phase (CVD process) at a temperature in the range from 200 to 450’C (a 3 ) applying a titanium nitride layer by means of a CVD 35 process at a temperature of 200 to 450‘C with the use of a nitrogen-containing organic titanium compound, which is excited thermally and/or optically and/or by a plasma, (aj applying an aluminium layer or an aluminium alloy layer by means of a CVD process at a temperature of 200 - 14 to 450’C with the use of an organic aluminium compound, which is excited thermally and/or optically and/or by a plasma (a 5 ) applying a metallic layer, which contains copper, 5 titanium, palladium and/or silicon, by means of a sputtering process or a CVD process with the thickness required for the desired alloy (a 6 ) brief heating of the semiconductor substrate to a temperature of up to 500°C for 10 to 120 sec in an inert 10 gas atmosphere (RTP or ROA process) for the purpose of alloy formation.

5. Process according to Claim 1, characterised by the process stages (b x ) pretreating the surface to be coated, of the semi15 conductor substrate (b 2 ) application of a metallic layer (b 3 ) heat treatment.

6. Process according to Claim 5, characterised by the further process stage 20 (b 4 ) selective metal deposition.

7. Process according to one of Claims 1, 3, 4, 6, characterised by the combination of the process stages (aj and (b 4 ).

8. Process according to one of Claims 5 to 7, charac25 terised in that the process stages are carried out in the following fashion. (b x ) bombardment with argon ions in order to remove oxides and to amorphise the semiconductor substrate (b 2 ) applying a titanium or cobalt layer by means of 30 sputtering from a metal target (b 3 ) brief heating of the semiconductor substrate to up to 700*C in an inert gas atmosphere (RTP or ROA) in order to form a silicide. (b 4 ) Selective deposition of tungsten or aluminium by 35 means of a CVD process, on free-lying silicon, silicide or metal.

9. Apparatus for carrying out a multi-stage process for producing layers or structures for circuits integrated on the very largest scale on a semiconductor - 15 substrate, consisting of a multi-chamber high-vacuum facility consisting of at least two process chambers (1 to 6), at least two supply chambers (8, 9) and at least one distribution chamber (7) connecting the chambers to 5 one another, all the chambers (1-9) and all connections between the chambers being high-vacuum-capable and enabling the combination of a plurality of different process stages without interruption of the high-vacuum conditions for the semiconductor substrate.

10. 10. Apparatus according to Claim 9, characterised by an achievable base pressure of less than 10' 6 mbar in the supply chambers (8, 9) and less than 10' 7 mbar in the distribution and process chambers (1-7).

11. A multi-stage process for producing conductive layers or structures for circuits integrated on the very largest scale on a semiconductor substrate according to any preceding claim substantially as hereinbefore described

12. An apparatus for carrying out a multi-stage process for producing layers or structures for circuits integrated on the very largest scale on a semiconductor substrate, according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.