IE904306A1 - Digital circuit with switching stages of the complementary¹mos circuitry type - Google Patents

Abstract

These switching stages exhibit two switching paths which switchably assume a closed or, respectively, opened state in opposite phase. To each switching stage input, a PMOS field-effect transistor is allocated in a first switching path (P1) and an NMOS field-effect transistor in a second switching path (N1) as switching element. The outputs (A11, A21) of the switching paths (P1, N1) are connected via a component (R) effecting a voltage difference at least during a switching process. The output (A11) of the first switching path (P1) is connected to a first, the output (A21) of the second switching path (N1) is connected to a second signal line (L1; L2) for connection to subsequent switching stages. For reducing a switching current flowing through both switching paths (P2, N2) of a subsequent switching stage during a switching process, the first signal line (L1) is connected to the gate electrode of the PMOS field-effect transistor allocated to the switching stage input of the subsequent switching stage and the second signal line (L2) is connected to the gate electrode of the associated NMOS field-effect transistor (TP, TN). To accelerate the switching process in a subsequent switching stage, the first signal line (L1) is connected to the gate electrode of the NMOS field-effect transistor allocated to the switching stage input of the subsequent switching stage and the second signal line (L2) is connected to the gate electrode of the associated PMOS field-effect transistor (TN, TP).

Description

A digital circuit includes first and second switching stages of the complementary MOS circuitry type having switching stage inputs and switching stage outputs. Each of the switching stages has first and second switching paths with interconnected outputs. The switching paths reversibly assume respective closed and open states in phase opposition and serve for alternative supply of respective first and second voltage potentials to the switching stage outputs. Each of the first switching paths has a switching element in the form of a PMOS field effect transistor with a gate electrode connected to one of the switching stage inputs. Each of the second switching paths has a switching element in the form of an NMOS field effect transistor with a gate electrode connected to another of the switching stage inputs. A component is connected between the outputs of the switching paths of the first switching stage for effecting a voltage difference therebetween at least during a switchover operation. A first signal line is connected between the output of the first switching path of the first switching stage and the gate electrode of either the PMOS field effect transistor of the first switching path or the NMOS field effect transistor of the second switching path of the second switching stage.

A second signal line is connected between the output of the second switching path and the gate electrode of either the NMOS field effect transistor of the second switching path or the PMOS field effect transistor of the first switching path of the second switching stage.

LAG:cdt PATENTS ACT, 1964 DIGITAL CIRCUIT WITH SWITCHING STAGES OF THE COMPLEMENTARY MOS SIEMENS AKTIENGESELLSCHAFT, a company organised according to the laws of Berlin and Munich, Federal Republic of Germany, of Wittelsbacherplatz 2, 8000 Munich, Federal Republic of Germany -1IE 904306 GR 89 P 1983 DIGITAL CIRCUIT WITH SWITCHING STAGES OF THE COMPLEMENTARY MOS CIRCUITRY TYPE Specification: The invention relates to digital circuits with switching stages of the complementary MOS circuitry type, each including first and second switching paths with interconnected outputs, which reversibly assume respective closed and open states in phase opposition and serve for alternative supply of respective first and second voltage potentials to a switching stage output or switching output, and a switching element associated with each switching stage input in the form of one PMOS field effect transistor in the first switching path or switching stage and one NMOS field effect transistor in the second switching path or switching stage, the gate electrodes of the transistors serving as connections for the applicable switching stage input.

Field effect transistors have decisive advantages for largescale integrated circuits, because they require little space or power and are comparatively easy to integrate. In digital technology, simple circuit structure and high immunity to interference can be attained with field effect transistors. The power loss of digital circuits can also be kept extremely low with field effect transistors, which is particularly true for digital circuits based on complementary MOS circuitry.

Complementary MOS circuitry, or CMOS circuitry, is based in principle on an inverter stage which includes a series circuit that joins two voltage potentials and includes a self-blocking p-channel (PMOS) and a self-blocking n-channel (NMOS) field effect transistor, the gate electrodes of which are connected to one another and form a switching stage input for a digital input signal. A center pickup of the series circuit serves as the switching stage output.

In the static state of the digital input signal, precisely one of the two field effect transistors is conductive at a given time, and for this reason no current flow between the two voltage potentials can arise and therefore no power loss occurs.

However, upon a change in level of the digital input signal, both field effect transistors are conducting for a certain switchover time, during which a switchover current can flow through both field effect transistors.

Digital circuits of that generic type are known from German Patent DE-PS 31 48 410 C2 and German Published, Non-Prosecuted Application DE-OS 38 37 080 Al, for instance. The first of those publications has programmable elements as well, which are parallel to or in series with the switching paths of a switching stage. The effect of such elements is that the configuration can be operated as either a NAND gate having two or three operative inputs, or an inverter. Upon -2*E 904306 switchover, the CMOS pairs consume power through the transverse current. The second publication describes a series circuit of conventional switching stages.

By varying the internal resistance of the field effect transistors, the switchover time can be shortened, with a low internal resistance, at the expense of a higher switchover current, or the switchover can be reduced, if there is a high internal resistance, at the expense of a longer switchover time. When dimensioning the field effect transistors, a compromise between the switchover time and the switchover current must accordingly be found. Since the manufacturing process for an integrated circuit sets the dimensioning of the field effect transistors, the compromise between switchover time and switchover current cannot be corrected later.

It is accordingly an object of the invention to provide a digital circuit with switching stages of the complementary MOS circuitry type, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and to do so in such a way that the switching stages have a reducible switchover current, or a shortenable switchover time, as compared with other switching stages having the same transistor dimensions.

With the foregoing and other objects in view there is provided, in accordance with the invention, a digital circuit, -3\£90430b comprising first and second or subsequent switching stages of the complementary MOS circuitry type having switching stage inputs and switching stage outputs or switching outputs; each of the switching stages having first and second switching paths with interconnected outputs, the switching paths reversibly assuming respective closed and open states in phase opposition and serving for alternative supply of respective first and second voltage potentials to the switching outputs or switching stage outputs; each of the first switching paths or the first switching stage having a switching element in the form of a PMOS field effect transistor with a gate electrode connected to one of the switching stage inputs; each of the second switching paths or the second switching stage having a switching element in the form of an NMOS field effect transistor with a gate electrode connected to another of the switching stage inputs; a component connected between the outputs of the switching paths of the first switching stage for effecting a voltage difference between the outputs of the switching paths of the first switching stage at least during a switchover operation; a first signal line connected between the output of the first switching path of the first switching stage and the gate electrode of either the PMOS field effect transistor of the first switching path or the NMOS field effect transistor of the second switching path of the second switching stage; and a second signal line connected between the output of the second switching path and the gate electrode of either the NMOS field effect transistor of the second switching path or -4IE 904306 the PMOS field effect transistor of the first switching path of the second switching stage.

In accordance with another feature of the invention, there is provided a first interruptible conductor element connected between the first signal line and the gate electrode of the NMOS field effect transistor of the second switching path or the PMOS field effect transistor of the first switching path of the second switching stage; and a second interruptible conductor element connected between the second signal line and the gate electrode of the PMOS field effect transistor of the first switching path or the NMOS field effect transistor of the second switching path of the second switching stage, for for selectively connecting the signal lines to the gate electrodes of the PMOS and NMOS field effect transistors of the second switching stage.

If the output of the first switching path is connected to the PMOSFET associated with an applicable switching stage input of a subsequent switching stage, and the output of the second switching path is connected with the correspondingly associated NMOSFET of the subsequent switching stage, then the gate-to-source voltages at the PMOSFET and the NMOSFET of the second switching stage are each reduced by half the amount of the voltage value that arises in the component effecting a voltage difference. The reduction of the gate-to-source voltages thus leads to a reduction in the switchover current -5IE 904306 flowing through the two switching paths of the subsequent switching stage upon a switchover operation.

If the output of the first switching path is connected to the NMOSFET associated with an applicable switching stage input of a subsequent switching stage, and the output of the second switching path is connected with the correspondingly associated PMOSFET of the subsequent switching stage, then the gate-to-source voltages at the PMOSFET and the NMOSFET of the second switching stage are each increased by half the amount of the voltage value that arises in the component effecting a voltage difference. The increase of the gate-to-source voltages thus leads to a reduction in the switchover current flowing through the two switching paths of the subsequent switching stage upon a switchover operation, and thus to an acceleration of the switchover operation of the subsequent switching stage.

An essential advantage of a digital circuit constructed according to the invention is that the switchover current or the switchover time can be varied within wide limits by the characteristic value of a single component, without having to redimension transistors for that purpose.

In accordance with a concomitant feature of the invention, the component effecting the voltage difference is a resistor or a diode polarized in the flow direction. -6IE 904306 Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a digital circuit with switching stages of the complementary MOS circuitry type, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

Fig. 1 is a schematic and block circuit diagram of a digital circuit including two switching stages that are joined into a logical OR linking circuit, with reduced switchover current; and Fig. 2 is a view similar to Fig. 1 of a circuit diagram of a digital circuit including two switching stages that are joined into a logical OR linking circuit, with reduced switchover time. -7IE 904306 Referring now in detail to Figs. 1 and 2 of the drawing as a whole, there is seen a current diagram for a logical OR linking circuit that is essentially constructed according to the principles of complementary MOS circuitry (which is also referred to simply as CMOS circuitry below).

The OR linking circuit includes a first switching stage (on the left-hand side of the figures), which effects a NOT-OR link, and a second switching stage being connected to the output side thereof and forming a negator (on the right in the drawings).

Each of the two switching stages include respective first and second switching paths Pl, Nl; P2, N2 having PMOS and NMOS field effect transistors (referred to below as PMOSFETs and NMOSFETs) as switch elements.

The first switching path Pl of the first switching stage includes two series-connected PMOSFETs Pa, Pb. The second switching path Nl of the first switching stage includes two parallel-connected NMOSFETs Na, Nb. The two switching paths Pl, Nl have outputs All, A21 that are connected to one another through a resistor R and inputs Ell, E21 that are connected to respective first and second voltage potential Vdd, Vss. The first voltage potential is at a more-positive voltage potential than the second voltage potential Vss. -8IE 904306 The switching path P2 of the second switching stage has a single PMOSFET TP and the switching path N2 of the second switching stage has a single NMOSFET TN. Inputs E12, E22 of the switching paths P2, N2 are also connected to the respective first and second voltage potentials Vdd, Vss. Outputs A12, A22 of the switching paths Pl, N2 are connected directly to one another, as is usual in CMOS technology, to form a switching stage output of the second switching stage and thus to simultaneously form an output AOR of the OR linking circuit.

In all of the field effect transistors in the switching paths, only the drain-to-source paths thereof participate in the formation of the switching paths. The drain electrodes of the field effect transistors are always oriented toward the output of the applicable switching path.

The gate electrodes of the PMOSFETs Pa, Pb and of the NMOSFETs Nb, Na belonging to the first switching stage serve as inputs Ea, Eb of the first switching stage and thus of the OR linking circuit. As is usual in CMOS technology, precisely one NMOSFET Na, Nb is logically associated with each of the PMOSFETs Pa, Pb, and the gate electrodes of the FETs that are associated with one another are connected to one another and each form one input Ea, Eb for a digital input signal a, b. -9IE 904306 The digital input signals a, b can assume the two binary values 0, ”1 which are represented by the voltage values of the two voltage potentials Vdd, Vss. With positive logic, the voltage value of the first voltage potential is associated with the binary 1” value, and the voltage value of the second voltage potential Vss is associated with the binary •’0 value.

In the second switching stage, the gate electrodes of the PMOSFET TP and of the NMOSFET TN that are logically associated with one another are not connected to one another but instead they are each connected, separately from one another, to a respective one of the switching path outputs All, A21 of the first switching stage, through a respective signal line LI, L2.

As is shown in the circuit diagram of the OR linking circuit of Fig. 1, the output All of the first switching path Pl of the first switching stage is connected through a signal line LI to the gate electrode of the PMOSFET TP of the second switching stage. Similarly, the output A21 of the second switching path Nl is analogously connected through the signal line L2 to the gate electrode of the NMOSFET TN.

In contrast to this, in the OR linking circuit of Fig. 1, the output All of the first switching path Pl is connected to the gate electrode of the NMOSFET TN, and the output A21 of the -10IE 904306 second switching path Nl is connected to the gate electrode of the PMOSFET TP.

In the stationary state (that is, when no change in values at the inputs Ea, Eb that leads to a switchover operation of the switching paths occurs during the period of observation), the two OR linking circuits of Fig. 1 and Fig. 2 behave in the same way.

In the stationary state, no current flows through the resistor R of the first switching stage, because only one of the switching paths Pl, Nl is conductive at a time. Thus no voltage drop occurs across the resistor R either, and the voltage values at the two switching path outputs All, A21 and thus at the two gate electrodes of the FETs TP, TN connected thereto in the second switching stage are identical to one another. The voltage values correspond to either the value of the first or the value of the second voltage potential Vdd, Vss, depending on the switching state of the first switching stage.

Correspondingly, in the stationary state, digital circuits of this kind, which are constructed in accordance with the invention, behave like equivalent circuits made according to conventional CMOS technology.

The essential difference, and therefore the advantages of digital circuits constructed according to the invention over -llIE 904306 conventional CMOS circuits, become apparent only upon observation of the dynamic behavior, or in other words during a switchover operation.

The most interesting instant for explanation purposes during a switchover process is the instant at which the digital input signal a, b tripping a switchover operation assumes an average voltage value during a value change that is located precisely in the middle between the first and second voltage potentials Vdd, Vss.

In the present example of the OR linking circuit of Figs. 1 and 2, the result of this mean voltage value, for instance at the first input Ea (wherein for simplification purposes, the second input Eb is assumed to be acted upon by the second voltage potential Vss, or in other words with a binary 0 value), is that the gate-to-source voltages at the FET Pa and the NMOSFET Na of the first switching stage associated with the first input Ea match the amount of the mean voltage value. The internal resistance of an FET is known to become lower as its gate-to-source voltage becomes higher.

Since the PMOSFET Pb associated with the second input EB is furthermore conducting and the associated NMOSFET Nb is blocking, two switching paths Pl, Nl of the first switching stage have the same resistance. A switchover current flows across the resistor R from the first to the second voltage potential Vdd, Vss. -12IE 904306 Thus the output All of the first switching path Pl has a more-positive voltage value than the output A21 of the second switching path Nl. The difference between these two voltage values is equivalent to the voltage drop across the resistor R.

In the OR linking circuit of Fig. 1, the gate-to-source voltage at the PMOSFET TP and the gate-to-source voltage at the NMOSFET TN of the second switching stage are thus lower than the mean voltage value that would be established by conventional CMOS technology.

In the digital circuit constructed in accordance with the invention, the internal resistances of both FETs TP, TN of the second switching stage are therefore higher, and consequently the switchover current in the second switchover stage is lower.

However, in the OR linking circuit of Fig. 2, the gate-tosource voltages at both FETs TP, TN of the second switching stage are higher than the mean voltage value, and as a result the switchover current in the second switching stage is increased, which speeds up the switchover operation.

The ohmic resistor R in the first switching stage can also be replaced with a diode polarized in the flow direction. In an integrated circuit, it may also be advantageous either to carry each of the two outputs All, A21 of the two switching -13IE 904306 paths Pl, Nl of the first switching stage to both FETs TP, TN of the second switching stage through a separate signal line, so that a change from this state can be made later, if needed (the circuit is then equivalent to conventional CMOS technology) / °r to reduce the switchover current, or shorten the switchover time, by interrupting these signal lines. The interruption of different lines connected to the signal lines LI, L2 is seen in Figs. 1 and 2 which shows interruptible conductor elements » for selective connection of the signal lines LI and L2 to the gate electrode of the PMOS field effect transistor or the gate electrode of the NMOS field effect transistor. This makes it possible to avoid different transistor dimensions on an integrated circuit. -14IE 904306

Claims (9)

Claims:

1. Digital circuit, comprising first and second switching stages of the complementary MOS circuitry type having switching stage inputs and switching stage outputs; each of said switching stages having first and second switching paths with interconnected outputs, said switching paths reversibly assuming respective closed and open states in phase opposition and serving for alternative supply of respective first and second voltage potentials to said switching stage outputs ; each of said first switching paths having a switching element in the form of a PMOS field effect transistor with a gate electrode connected to one of said switching stage inputs; each of said second switching paths having a switching element in the form of an NMOS field effect transistor with a gate electrode connected to another of said switching stage inputs; a component connected between said outputs of said switching paths of said first switching stage for effecting a voltage difference between said outputs of said switching paths of said first switching stage at least during a switchover operation; a first signal line connected between said output of said first switching path of said first switching stage and the -15IE 904306 gate electrode of said PMOS field effect transistor of said first switching path of said second switching stage; and a second signal line connected between said output of said second switching path and the gate electrode of said NMOS field effect transistor of said second switching path of said second switching stage.

2. Digital circuit, comprising first and second switching stages of the complementary MOS circuitry type having switching stage inputs and switching outputs; each of said switching stages having first and second switching paths with interconnected outputs, said switching paths reversibly assuming respective closed and open states in phase opposition and serving for alternative supply of respective first and second voltage potentials to said switching outputs; said first switching stage having a switching element in the form of a PMOS field effect transistor with a gate electrode connected to one of said switching stage inputs; said second switching stage having a switching element in the form of an NMOS field effect transistor with a gate electrode connected to another of said switching stage inputs; a component connected between said outputs of said switching paths of said first switching stage for effecting a voltage difference between said outputs of said switching paths of -16IE 904306 said first switching stage at least during a switchover operation; a first signal line connected between said output of said first switching path of said first switching stage and the gate electrode of said NMOS field effect transistor of said second switching path of said second switching stage; and a second signal line connected between said output of said second switching path and the gate electrode of said PMOS field effect transistor of said first switching path of said second switching stage.

3. Digital circuit according to claim 1, including a first interruptible conductor element connected between said first signal line and the gate electrode of said NMOS field effect transistor of said second switching path of said second switching stage; and a second interruptible conductor element connected between said second signal line and the gate electrode of said PMOS field effect transistor of said first switching path of said second switching stage, for for selectively connecting said signal lines to the gate electrodes of said PMOS and NMOS field effect transistors of said second switching stage.

4. Digital circuit according to claim 2, including a first interruptible conductor element connected between said first signal line and the gate electrode of said PMOS field effect -17IE 904306 transistor of said first switching path of said second switching stage; and a second interruptible conductor element connected between said second signal line and the gate electrode of said NMOS field effect transistor of said second switching path of said second switching stage, for for selectively connecting said signal lines to the gate electrodes of said PMOS and NMOS field effect transistors of said second switching stage.

5. Digital circuit according to claim 1, wherein said component effecting the voltage difference is a resistor.

6. Digital circuit according to claim 2, wherein said component effecting the voltage difference is a resistor.

7. Digital circuit according to claim 1, wherein said component effecting the voltage difference is a diode polarized in the flow direction.

8. Digital circuit according to claim 2, wherein said component effecting the voltage difference is a diode polarized in the flow direction. -18IE 904306

9. A digital circuit according to any preceding claim substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings. Dated this the 29th day of November, 1990 F. R. KELLY & CO. BY _EXECUT I VE ' Clyde 27 ClYde Road,^Ββΐΐsbridge, Dublin 4. AGENTS FOR THE APPLICANTS -19SIEMENS AKTIENGESELLSCHAFT One Sheet Only TRUE COPY