IE84091B1 - Circuit security - Google Patents
Circuit security Download PDFInfo
- Publication number
- IE84091B1 IE84091B1 IE2004/0708A IE20040708A IE84091B1 IE 84091 B1 IE84091 B1 IE 84091B1 IE 2004/0708 A IE2004/0708 A IE 2004/0708A IE 20040708 A IE20040708 A IE 20040708A IE 84091 B1 IE84091 B1 IE 84091B1
- Authority
- IE
- Ireland
- Prior art keywords
- board
- security
- track
- cover
- circuit
- Prior art date
Links
- 238000007906 compression Methods 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- WYTGDNHDOZPMIW-UHOFOFEASA-O Serpentine Natural products O=C(OC)C=1[C@@H]2[C@@H]([C@@H](C)OC=1)C[n+]1c(c3[nH]c4c(c3cc1)cccc4)C2 WYTGDNHDOZPMIW-UHOFOFEASA-O 0.000 description 8
- 229910001369 Brass Inorganic materials 0.000 description 2
- 239000010951 brass Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000875 corresponding Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000789 fastener Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001681 protective Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/86—Secure or tamper-resistant housings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0275—Security details, e.g. tampering prevention or detection
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/144—Stacked arrangements of planar printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09263—Meander
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/0999—Circuit printed on or in housing, e.g. housing as PCB; Circuit printed on the case of a component; PCB affixed to housing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10151—Sensor
Abstract
ABSTRACT A secure device (1) has a circuit board (2) with various exposed components such as LCD (4) and keys (40). A secure circuit (10) is housed within an enclosure formed between the board (2) and a cover (11). The cover (11) has, on its inside surface, a security track (23) in a dense serpentine pattern. The board (2) has a security track (52), also in a dense serpentine pattern, is an inner layer. The track (52) is linked to covered surface-level tracks (27) by vias (64). The Covers security track (23) is connected to the boards security tracks (52, 27) Via a deformable pad (25) whose conductivity increases with applied compression.
Description
“Circuit Security” INTRODUCTION Field of the Invention The invention relates to security of electronic circuits such as circuits for processing and storing security codes for transactions.
Prior Art Discussion It is known from US63553l6 to provide a secure device comprising an electronic circuit covered by a cover with a security track. If this track is broken an alarm is raised in the secure electronic circuit. The cover is of brittle material so that even the smallest damage causes it to break into a large number of small elements.
The invention is directed towards providing an improved secure circuit in which: there is improved circuit security against tampering; and/or the secure circuit has improved ability to withstand mechanical shock; and/ or the secure circuit can be non-destructively accessed by an authorised engineer for repair or upgrade.
Statements of Invention According to the invention, there is provided a secure circuit device comprising a circuit board, a secure circuit on the circuit board, a cover covering the secure circuit and being secured to the board, and security tracks on the cover and on the board arranged to be electrically connected together when the cover is in placed on the board, wherein a security track is in a dense pattern covering a substantial part of the _ 2 _ area of the cover or the board, and wherein the cover and board security tracks are connected via a seal disposed between the cover and the board, and wherein the board has a multilayer structure and it comprises a security track having a dense pattern in an internal layer.
In one embodiment, the cover comprises a security track with a dense pattern on an inner surface, facing the board.
In another embodiment, said security track has a serpentine pattern of a single continuous track.
In one embodiment, said pattern is a serpentine pattern of a continuous single track.
In another embodiment, the secure circuit is electrically connected to said security track by blind vias in the board.
In a further embodiment, the board comprises through vias linking components on an exposed board surface with the secure circuit.
In one embodiment, said components include a keypad.
In another embodiment, the board comprises blind vias linking parts of the secure circuit.
In a further embodiment, both the cover and the board comprise inter—connecting ground rails.
In one embodiment, said ground rails extend around a periphery of the board area covered by the cover.
In a further embodiment, said seal comprises a deformable conductive material pad.
In one embodiment, conductivity of the pad increases with increased compression of the pad.
In another embodiment, the pad comprises a deformable material with embedded conductors.
In a further embodiment, the conductors comprise threads of metal extending between the surfaces of the pad.
In one embodiment, the keypad comprises a security key linked with a security track.
In another embodiment, said security key comprises a ground guard rail surrounding the key.
In a further embodiment, said security track comprises a track in a serpentine pattern on a surface of the board covered by, and facing towards, the cover.
In one embodiment, said track connects with the security track of the cover.
In another embodiment, said security track is also connected to a security track of an internal layer of the board.
DETAILED DESCRIPTION OF THE INVENTION Brief Description of the Drawings The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which:- Figs. 1(a), l(b), and l(c) are plan, and diagrammatic cross—sectional side and front views respectively of a security device containing a secure circuit; Fig. 2 is a diagrammatic cross—sectional diagram showing how a cover is secured in place on a circuit board of the device; Fig. 3 is a plan view of the board; Fig. 4 is an underneath plan showing a keypad which includes a case switch key surrounded by a copper guard rail which is connected to ground potential; Fig. 5 is a diagrammatic cross-sectional diagram of the main board; Fig. 6 is a view of security tracks embedded in an internal layer of the board; Fig. 7 is a View of a security track and a ground rail on the internal surface of the cover.
Description of the Embodiments Referring to Figs. 1(a), 1(b), and l(c) a secure device 1 comprises a main circuit board 2 having non—seeure components 3 and an LCD 4 on opposed sides of the main board 2 at an exposed end. The device 1 also comprises a secure circuit 10 mounted within an enclosure formed between the main board 2 and a security cover 11. The cover 11 is secured to the main board 2 by bolt fasteners 12. The security cover 11 has sp1ayed—out side walls 13 terminating in a rim 20 contacting the main board 2. The secure circuit 10 is an ARM microprocessor and alarm components, and it is mounted on connectors on the main board 2. The device 1 also comprises keypad keys 40 on the exposed surface of the board 2 opposed to the cover 1 1.
Referring to Fig. 2, each splayed side wall of the cover 1 1 terminates in a rim 20. A cover ground rail 21 extends around the periphery of the hidden surface of the rim , and it contacts a ground rail 22 of the board 2. The ground rails 21 and 22 are mm wide. The cover ll has security tracks 23 in a serpentine pattern on its inside surface. These tracks have terminals 24 at two downwardly—projeeting bosses on the rim 20. The corresponding locations on the board 2 have security track terminals 26.
A security pad 25 lies between the two security track terminals 24 and 26 at these locations. The board security track terminals 26 are also shown in Fig. 3, as is a surface—leVel security track 27 extending around the periphery of the area covered by the cover ll, just inside the ground rail 22. This drawing also shows 80—way connectors 30 and 31 for supporting the secure circuit 10, which in this embodiment is an ARM CPU.
Fig. 4 shows the side of the board 2 opposed to the cover ll. This side includes conventional keys 40 and a case switch 41 key surrounded by protective copper 42 which is connected to ground potential.
Referring to Fig. 5, the internal structure of the main board 2 is shown. There are six layers (two external and four internal), with five insulation layers in—between. The layers are as follows: : On the internal surface. Conductors on the opposed external surface connect to this layer for ground, Vce, keypad, LCD and non-secure signals. This layer connects to the secure circuit 10.
: Routing conductors for secure and non—secure signals. Microvias are used to minimise the number of through holes in the board 2.
: A security track layer with a serpentine pattern, shown in Fig. 6.
: A ground plane.
: Vcc, 3.3Vplane.
: Conductors on the external surface connected to keypad keys 40. This layer also contains some non—sccure signals and the case switch key 41.
The board 2 also has both through hole and blind Vias including, from left to right in Fig. 5: (a) Through hole vias 60 for connecting keys and some non—securc signals to the secure circuit 10. (b) Through hole Vias 61 for connecting the layer 53 ground plane to both the top and bottom layers 50 and 55. (c) Through hole Vias 62 connecting the top and bottom layers 50 and 55 to the V3 conductor plane 54. d Blind Vias 63 for routin sensitive and non-sensitive conductors between the 2% top layer 50 and the second layer 51. (e) Blind Vias connecting the secure circuit 10 to the security tracks of the layer Referring to Fig. 6 the internal security track 52 for conducting the mesh alarm signal and ground signal is illustrated. These signals are connected to the secure circuit 10 via the blind Vias 64.
Referring to Fig. 7 the inside surface of the cover 1 1 has a security mesh track 23 on its surface. The track 23 includes terminals (shown by wide short lines at positions corresponding to those of the terminals 26 in Fig. 3). These are electrically connected to the two terminals 26 on the board 2, which in turn connect to the security tracks 27 and to the secure circuit 10 - thus forming a security cage around the secure circuit 10 and electrically connected to an alarm circuit on the secure circuit 10. The external ground (guard) rail 21 is also shown. This connects to the ground rail 22 of the main board 2. Both the ground rail 22 and the mesh 27 are on the top layer 50 of the main board 2.
The secure circuit 10 is an ARM CPU and alarm components, and it is protected by a combination of the cover 11 on whose surface there is the single mesh track 23 and the board 2 containing an internal single wire mesh track 52.
All of the numeric keys 40 on the keypad are contained within the area opposed to the cover 1 1, including the case switch 41 which will activate the alarm if the keypad is removed from its housing. This alarm would also be activated if the area around the key is flooded with conductive ink to try and short circuit the key due to the presence of a ground potential guard rail 42 around the key. The serpentine mesh 27 of the board 2 is connected such that if this mesh is broken. connected to ground. or drilled then the alarm will be raised on the ARM CPU 10.
All of the electronics requiring security protection are contained on the ARM CPU The cover 11 is made from a very precise engineering plastics material. The walls 13 are splayed at 45° and the rim 20 has two raised land areas which connect the terminals 24 to the two larger terminals 26 on the board 2. The terminals 26 are protected from attack by the internal serpentine alarm track 27. The terminal sizes, the gap between the cover 11 and the board 2 and the track widths and spacing meet ZKA and VISA PED security requirements. The separation between ground and the terminals is 0.5mm. If the ground area shorts to the mesh or either of the terminals then the alarm will be set.
The following summarises some of the main security features: The internal serpentine mesh layer 52 connected to the alarm circuit. This internal mesh is larger than the secure area of the cover 11.
The case switch key 40 which will be a key contact on the back of the board 2. This key is constantly connected to a carbon PIL on the keypad membrane. l f the keypad is removed from the outer plastic then the alarm will trigger.
The ground potential guard rail 42 is present around the case switch key 41.
If conductive ink is introduced to this pad area to try and bypass the key the ink will short the key to ground and raise the alarm condition.
All PED (PIN Entry Device) keys are contained in the secure area (that opposed to the cover 1 l).
The ground rail 22 on the top side of the board 2, which connects to the ground rail 21 of cover 11. If this ground rail is connected to the terminals or mesh then an alarm condition is raised.
The miniature serpentine mesh 27 in the areas under the land area of the cover 1 1. If this mesh is broken the alarm condition is raised.
The blind vias 63 which connect the layers 50 and 51 of the board 2. All secure signals on the board 2 will be routed on these layers. These signals are not visible on the key side of the board 2.
The blind 64 which connects the layer 50 to the layer 52. These vias transfer the alarm mesh signal from the ARM CPU 10 to the layer 52 of board 2.
These signals will not be visible on the key side of the board 2.
All through hole vias enter the secure area of the PCB in the area under the land area of the cover ll. This prevents probes from being inserted into the SCCUFC E1I'€8..
The alarm track 23 on the cover 11 is connected in series to the following: a) alarm track on the internal layer 52 of the board 2. b) alarm track on 27 on the top layer of the board 2. the case switch key 41 on the bottom layer 55 of the board 2.
The alarm signal is normally high. If it is broken (opened) or connected to ground then an alarm is raised on the ARM CPU 10, causing its RAM contents to be deleted.
Referring again to Fig. 2, each pad 25 is very small (only the dimensions of the terminals 26), however it forms an essential link between the security track 23 of the cover 11 and a terminal 26 of the security track 27 of the board 2. Each pad 25 comprises silicone rubber with dispersed brass fibres extending between the pads faces. The surfaces of the pad 25 are gold plated. The arrangement of the brass fibres is such that electrical resistance between the two pad surfaces decreases with compression of the pad. Thus, as the screws are tightened to secure the cover 1 1 onto the board 2, the pads 25 are compressed, thus making them more conductive. This effectively links the cover’s security mesh 23 to the boards security mesh 27 via the terminals 24 and 26. This arrangement provides many advantages. An attempt to tamper with the secure device 1 by separating the cover ll from the board 2 results in an open circuit at the pad 25. However, an authorised engineer may non- destructively separate the cover 1 l from the board 2 for repair or upgrade. The RAM contents are not lost, however the device may be repaired. Also, because the pad 25 is of resilient material it provides a degree of shock absorption, thus reducing risk of a fault if the device is dropped or knocked. Also, during manufacture, the pads 25 provide a large tolerance for tightening torque of the bolt fasteners.
If a hole is drilled through the cover 11 (or between the cover 11 and the board 2) an alarm will be raised on the ARM CPU 10 due to a track being broken. If a hole is drilled between the connection of the board 2 and the cover 11 the drill will cut security tracks on both the cover 11 and the board 2, thus raising an alarm condition.
Similarly if a hole is drilled through the board 2 the same alarm will be raised due to the single wire mesh track being broken or shorted to ground potential, causing the RAM contents on the secure circuit 10 to be deleted.
In an alternative embodiment, pads on the inner surface of the cover ll are electrically connected to the board by a conductive polymer. The box is mechanically connected to the board by using a non-conductive epoxy and screws.
In this embodiment, an attempt to forcibly separate the cover ll from the board 2 would damage the security tracks.
The invention is not limited to the embodiments described but may be Varied in construction and detail.
Claims (2)
1. ). A device as claimed in claim 17, wherein said track (27) connects with the security track (23) of the eover(11). A device as claimed in claim 18, wherein said security track (27) is also connected to a security track (5
2. ) of an internal layer of the board. A secure circuit device substantially as described with reference to the drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IE2004/0708A IE84091B1 (en) | 2004-10-22 | Circuit security |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IEIRELAND24/10/20032003/0801 | |||
IE20030801 | 2003-10-24 | ||
IE2004/0708A IE84091B1 (en) | 2004-10-22 | Circuit security |
Publications (2)
Publication Number | Publication Date |
---|---|
IE20040708A1 IE20040708A1 (en) | 2005-06-15 |
IE84091B1 true IE84091B1 (en) | 2005-12-14 |
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