IE53033B1 - Channel protection switching arrangement - Google Patents

Abstract

An errorless channel protection switching arrangement utilizes a variable delay (29) in the spare channel (21-24, 26-29, 31-33) adjusted to provide data signal alignment with an impaired regular channel before substituting the spare channel for the regular channel. This switching arrangement is able to provide bit error free channel substitution between the spare and any regular channel in a digital radio system by virtue of the data signal alignment capability. Data signal alignment is provided by first aligning clocking signals in fine incremental steps with each clocking signal derived from one of the two channels undergoing the substitution. Data signal alignment is then provided by shifting the spare channel in full bit positions until data alignment is indicated by a detector (119). Data signal alignment is also utilized to restore service to a regular channel so the spare channel may be removed from service.

Description

CHANNEL PROTECTION SWITCHING ARRANGEMENT.

This invention relates to channel protection switching arrangements, and finds application in, for example, radio communication systems where it may be employed to switch between digital radio channels in an error free manner to ensure system reliability.

Due to the occurrence in radio communication systems of frequency selective fading and possible equipment malfunctions, protection switching between a regular channel hampered by a transmission impairment and a standby, or spare, channel is known and used in the art. Each channel signal in such radio systems encounters a transmission delay that includes a constant portion whose value is peculiar to each channel and a time varying portion, because of the variability in atmospheric propagation introduced at each specific channel frequency.

In digital radio communication systems, this variable, or dynamic delay alone renders protection switching between a single standby channel, also known as a protection channel, and any one of a number of regular channels (referred to as 1XN) a difficult task. The precise timing attendant to digital signals is a further requirement such that 1XN protection systems for digital radio communications have heretofore been generally unavailable.

One type of conventional protection switching arrangement for digital transmission systems is a limited Z one-by-one (1X1) arrangement wherein a standby protection channel may only be substituted for a designated one ol' a number of regular channels. Such a protection provision is undesirable iu terms ol' equipment duplication and congestion of the frequency spectrum at the radio frequencies.

The difficulty of this task has been so great that conventional protection switching systems even for one-by-one arrangements have principally been directed to maintaining framing on the digital bit stream rather than attempting the complete elimination of bit errors. Since a frame in a typical transmission format includes a predesignated large number of bits, the loss of framing will produce thousands of bit errors. However, the ultimate objective of any protection switching arrangement should be to provide error free operation when switching to a spare channel since only this is consistent with the intended purpose of sucii a feature.

Because the number of digital bit errors generally increases exponentially when the transmitted information signal experiences fading of a few decibels of attenuation, bit errors tend to grow rapidly. It would therefore be highly desirable for channel protection switching to occur when a transmission impairment is first detected with reliability to provide the best possible error performance by a digital radio transmission system.

A further advantage to error free protection switching is the relaxation of constraints on switching for maintenance purposes since the error penalty of conventional protection switching arrangements restricts such maintenance switching to situations of absolute necessity.

A further requirement is occasioned by desynchronization arrangements used in current digital radio systems. The desynchronizers are used to provide the data signal and a recovered clock signal in the line receivers of such systems. Unfortunately, a pulse stuffing technique used in the desynchronizers produces timing jitter. This timing jitter is higher in frequency than the time varying portion of the variable delay mentioned previously. As a result, this places a further demand on the error free switching capability of a protection switching arrangement in a digital radio communication system.

According to this invention a channel protection switching arrangement includes means for shifting the relative timing between digital signals of an impaired channel and a protection channel, control means for adjusting the shifting means to achieve channel signal alignment by first adjusting the shifting means in fine increments to achieve hit timing alignment of the digital signals, and then adjusting the shifting means in coarse increments to achieve data alignment of the digital signals, and switching means for substituting the protection channel for the impaired channel after channel signal alignment.

The invention may provide error free channel protection switching in the presence of signal timing jitter as a product of the variability in atmospheric propagation and pulse stuffing desynchronization timing jitter. The invention may take the form of a controller of apparatus in a channel protection switching system which expediently adjusts relative signal timing between two digital channels carrying the same digital signal to enable the substitution of a spare channel for a service channel without introducing errors. The relative timing between the two digital channels is shifted in a first direction and then reversed while checking for signal alignment after each step of adjustment. This controller characteristic is highly desirable since the detector may only sense the presence of signal alignment and be unable to indicate the direction of relative timing shift to effect signal alignment.

The controller may adjust a shifter to change relative signal phase from an initial value in a first direction to a first extreme value and then in the opposite direction to the opposite extreme value, these adjustments are in the form of fine steps. The status of bit alignment is checked after each fine step and stopped when the detector indicates alignment. After bit alignment is obtained, data alignment is sought in a similar fashion using coarse adjustment steps equal to the duration of a bit period. After both bit and data alignment are obtained, the controller directs the channel substitution.

The controller may have the ability to make 5 successive processes of adjustment of the relative signal timing when the detector fails to indicate alignment.

The controller also has the ability to keep track of the number of attempts and directs alternative action when a prescribed limit of attempts occurs. The controller recheclcs for hit alignment after each adjustment of data alignment. When bit alignment ceases to be indicated by the detector, the fine step process is used to restore it before the data alignment process is used.

As a further cheek on the operation of the detector, the controller retards adjustment of the shifter one step and uses that adjustment or the previous one to maintain bit alignment.

Restoration of service from the spare channel back to the regular channel previously removed from service is provided by the controller. This only involves fine step adjustment since the channel being shifted is in service which should not he disrupted. The controller also has the ability to provide direct channel switching without timing and data synchronization when an out-of-frame condition occurs or when numerous attempts at such synchronization are not productive.

The invention will now be described by way of example with reference to the accompanying drawings, in which: FIG. 1 depicts an application of the invention in a digital radio communication system; FIG. 2 is a more detailed block diagram showing part of an embodiment of the invention; FIG. 3 is a diagram of a static aligner for 35 varying the signal propagation delay of a digital radio channel signal; FIG. 4 depicts a suitable circuit for dynamically 38 varying channel signal propagation delay; FIG. 5 is a diagram of an alignment detector; FIG. 6 is a flow diagram oi the basic procedure used to establish channel signal alignment; FIG. 7 is a flow diagram of a channel signal alignment subroutine used in FIG. b; FIG 8 illustrates a subroutine utilized in FIG. 7; FIG. 9 is a flow chart of a subroutine used to check clocking signal alignment; FIG.10 is a flow chart of a procedure used to provide data alignment; FIG.11 is a sequence of steps utilized in FIG. 10; FIG. 12 is a flow chart of the general procedure used to adjust signal propagation delay when disconnecting the protection channel; FIGS. 13 and 14, when juxtaposed according to FIG. 15, form a flow chart of the alignment down subroutine used for each active signal rail in a radio channel; and FIG. 16 is a block diagram of the line switch control employed in the system depicted in FIG. 1.

In FIG. 1 the radio transmission system includes a plurality of N transmission channels and a single protection channel which may be substituted for any one of the N channels. Of course, it should be understood that this is a basic configuration of the channel protection arrangement which may be replicated a number of times in accordance with the overall channel capacity of the system.

Each regular channel at the transmit, or head end includes its own transmit line switch (TLS) 11, transmit digital terminal (TDT) 12, and radio transmitter (RT) 13 which energizes radio antenna 14. Typically, each channel is multiplexed on to the radio carrier signal to be transmitted by a single radio antenna so that individual antennae 14 are depicted symbolically.

The receive end of eacli channel includes one of antennae (also symbolically'shown) 15, radio receiver (HR) 16, receive digital terminal (HDT) 17, static aligner (SA) 18, receive line switch (RLS) 19, and violation monitor (VM) 20 which is associated with the output of the channel.

The protection channel includes transmit selector (TS) 21 which receives an input from each one of the transmit line switches 11, transmit digital terminal 22, radio transmitter 23 and antenna 24 all at the head end. The receive end of the protection channel includes antenna 26, radio receiver 27, receive digital terminal 28, dynamic aligner (DA) 29, receive selector (RS) 31, common selector (CS) 32 and violation monitor (common) 33. Line switch control 34 controls the line protection switching function in this arrangement in response to the outputs of violation monitors 20 and activates appropriate head end and receive end switches to maintain the reliability of the transmission channels.

Basically, the overall function for this arrangement is to detect transmission errors using parity bits in each of the regular channels and also the protection channel and then to substitute the protection channel for a regular channel when the latter produces errors. At this point it should be pointed out that each violation monitor provides two functions. One is to determine an error rate by counting the number of digital bits in a specified block and comparing that to the parity bit information associated with that block of information. When errors are detected, a violation monitor will not produce an output until a predesignated limit or threshold is exceeded. The second function of each violation monitor is to indicate an out-of-frame condition which is a failure to lock onto the digital hit stream. Such an indication, albiet uncommon, is a condition that will typically produce several tens of thousands of bit errors and accordingly a violation monitor issues an immediate distinct output upon detection of a loss of frame. Control 34 in response to this distinct output then arranges a direct channel substitution.

A paramount, feature of this arrangement is that channel signal hit alignment, is achieved between an impaired regular channel and the protection channel before channel switching is initiated so as to not produce bit. errors and thereby increases system reliability. Before the system of FIG. 1 is used, static aligners 18 associated with each regular channel are manually adjusted so that the range of the delay of all the regular channels is within the middle of the variable range of dynamic aligner 29 in the protection channel. The electrical length of the protection channel is initially longer due to the extra delay inherent to the internal circuitry of selectors 21 and 31.

FIG. 2 illustrates the receive end switching arrangement in more detail. It should be pointed out at this point that each channel signal consists of two digital hit streams on an A and a B rail. Accordingly, each of the components in FIG. 2 is divided into an A and a B section as required for the dual rail channel signal. The dual rail signal for eacli of the regular channels is applied to static aligner 18 whose output is applied to a pair of input terminals on receive line switch 19. The input for the protection channel is applied to dynamic aligner 29 which feeds receive selector 31· The output of receive selector 31 is applied to common selector 32 and also switch 19. FIG, 2 shows the various inputs and outputs for line switch controller 3¾.

In order to provide an understanding of this arrangement the various switches will be described in terms of completed signal paths during normal operation when the violation monitors in the system are not indicating any error condition. Accordingly, for each regular channel the dual rail channel signals on lines ql and 42 are effectively connected to lines 43 and 44 through signal paths completed in receive line switch 19. Concurrently, the dual rail signal for the protection channel on lines 46 and 47 at the input of receive selector 31 goes straight through to lines 48 and 49 of common selector 32 and then directly to 3 0 3 3 the lines that provide the output signals. It should he understood that when the protection channel is not substituted for a regular channel, the protection channel is used to transmit a regular channel signal so that its error performance may be continuously monitored by violation monitor 33. In the event that the protection channel is generating errors, it is made unavailable for substitution of the regular channels.

At the initiation of the protection mode of the 10 operation, a violation monitor produces an output associated with a channel impairment or channel failure. This output is sent to line switch controller 34 which activates the transmit line switch in the impaired regular channel and transmit selector 21 in the protection channel.

This enables the protection channel to have the same channel signal input as the impaired regular channel. At the receive end, control 34 issues a signal to receive selector 51 to apply the duplicate channel signal input to the receive line switch. Assume, in this case, it to be the one designated in FIG. 2 as 19-1. As will become more apparent later, each receive line switch includes an alignment detector which provides an output signal to control 34 indicative of the difference in the electrical path lengths between the duplicate set of channel signals.

Control 34 issues a control signal to adjust the delay of dynamic aligner 29. Accordingly, these components change the electrical path length of the protection channel so that its total transmission delay corresponds to that produced by the impaired regular channel.

When signal alignment occurs, controller 34 directs receive line switch 19-1 to apply the signal from the protection channel on lines 51 and 52 to output lines 43 and 44. At the same time, the channel signal input from the impaired regular channel on lines 41 and 42 is routed to output lines 5? and 54 for common selector 32. Under the direction of controller 34, common selector 32 opens the signal path provided during the normal mode of operation and establishes a signal path which connects the impaired regular channel signal to violation monitor 33.

This is one instance for which violation monitor 33 is designated by (common) since it may, in fact, be used to monitor any one of the signal channels. Thus while in the protection mode not only is the substitution of the protection channel for the regular channel being violation monitored but also the performance of the impaired regular channel removed from service is being monitored.

When the output of violation monitor 33 indicates 10 that the error performance of the impaired regular channel has been restored, controller 34 initiates a process wherein the impaired regular channel is substituted for the protection channel to restore the normal mode of operation. Again dynamic aligner 29 serves to equalize the electrical path lengths experienced by the channel signals so that the switching operation will not produce any bit errors. Once signal alignment occurs the alignment detector issues a signal to controller 34. Receive line switch 19 reverses its signal path configuration to produce the normal mode of operation.

FIG. 3 illustrates the internal circuitry of Section A of static aligner 18. Section B of aligner 18 is simply shown as a block since its internal circuitry is identical to that in Section A. Line receivers 71 and 72 respectively receive the balanced data input on the A rail and the balanced clock input. It should be noted that balanced signals are used between physically displaced circuits for well known reasons concerning noise immunity. Receiver 71 converts the balanced A rail data to single ended data signals suitable for the internal circuitry therein. Similarly, receiver 72 provides a single ended clock signal which is used to strobe the various components.

Initially the proper relationship between the data and the clock signal is provided by retiraer 73. The data output from retimer 73 is applied to D flip-flops 74-0 to 74-14 which are serially connected to form a shift register delay line. The input and output of flipii flop 74-0 are respectively applied to the first and second inputs of multiplexer 76. The remaining inputs to multiplexer 76 are provided hy the outputs of flipflop 74-1 and intermediate flip-flops implied by FIG. 3.

The outputs of other implied flip-flops provide all but the final input signal for multiplexer 77. Flip-flop 74-14 provides the final input for multiplexer 77.

Hex rotary switch 7θ controls the selection of one of the possible outputs of multiplexers 76 and 77 for application to retimer 79· The data output of retimer 79 is converted back into complementary or balanced form by line driver 81. Line driver 82 provides the same conversion for the clock signal.

In operation static aligner 18 provides a delayed version of the data signal in accordance with the setting of switch 78. In other words, only one signal path through multiplexers 76 and 77 is completed according to the 3-Bit signal status on lines 84 and enable lines 83. The selected signal is passed on to retimer 79. Available at the inputs of multiplexers 76 and 77 by virtue of the operation of flip-flops 74-0 to 74-14 is a plurality of data signals successively delayed in 1-bit increments.

As previously described, switch 78 is manually adjusted to provide the appropriate delay for its associated regular or service channel signal on the A rail. The B rail signal has Its own delay interval established by Section B of aligner 18.

FIG. 4 illustrates the internal circuitry of dynamic aligner 29 which includes identical A and B sections of which only A is shown in detail. Similar to static aligner 18, dynamic aligner 29 utilizes line receivers 91 and 92 for providing single ended data and clock signals and also line drivers 93 and 94 for providing balanced outputs for the data and clock signals. The output of receiver 91 is applied to serially connected retimers 96-99 while receiver 92 supplies a clock signal for variable delays 101-103 serially connected. Retimer 96 insures that the correct timing relationship exists between the data and the clock signal l'or the remainder of the circuitry in aligner 29. lletimers 97-99 each serve to delay the data signal in accordance with the respective delay provided by variable delays 101-103. An amount of delay less than a bit interval is provided by delays 101103 as a function of the output of latches 106 and 107.

The input to latch 106 and 107 is provided by isolation circuit 108 which is connected to line switch control 34 of FIG. 1.

Retimers 97-99 each provide an amount of delay in accordance with the controlled setting of their respective delayed clock signal. Variable delays 101-103 are tapped delay lines with adjacent taps providing a small increment in delay for the clock signal which corresponds to a small portion of a bit interval in the data signal. A bit interval also corresponds to the delay interval present between adjacent or successive clock signals. It should be understood that this portion of aligner 29 will be referred to as the fine portion since it provides delay adjustments in increments less than the duration of a single bit in the data stream.

The data signal from retimer 99 is applied to shift register 109. The clock or strobe signal to shift register 109 Is provided hy the output of variable delay 103. The input to register 109 and various outputs are concurrently applied to multiplexer 111. The operation of register 109 and multiplexer 111 provides the same function as described in connection with flip-flops 74 and multiplexer 76 in aligner 18. In this case, however, latch 107 controls the selection of the output from multiplexer 111 from one of its inputs. Retimer 112 reestablishes the appropriate relationship between the clock and the data signal for the output of aligner 29.

The cooperation of register 109 with multiplexer 111 provides from zero to 7-bits of delay and will be referred to hereinafter as the coarse delay. A strobe signal on line 113 is provided by line switch control 34 of FIG 1 to clock latches 106 and 107.

It should be understood that aligner 29 is adapted for use in the protection channel of FIG. 1, Accordingly, its operation is automatically controlled by line switch controller 74· It is the function of this automatic operation to provide signal channel alignment between a regular channel and a protection channel so that signal channel substitution may he effected without introducing bit errors in the digital bit stream being transmitted over the radio system of FIG. 1.

FIG. 5 depicts an alignment detector suitable for utilization in receive line switch 19 of FIG. 1. Alignment detector 119 receives the data signals from the regular channel and the protection channel at exclusive OR gate 120. Clock signals derived from the respective channels are applied to exclusive OR gate 121. It should be pointed out that the input signals applied to alignment detector 119 are obtained directly from a point in receive line switch 19 in order to insure they are representative of the channel signals at the point of switching. A third exclusive OR gate 124 in detector 119 has a tied together pair of floating inputs with its outputs connected to a resistive network including resistors 123-128 for the purpose of providing reference potentials for comparators 129 and 131.

When the clock signals applied to gate 121 are perfectly in phase then the noninverted output of the gate will produce a steady low state. When the input signals are not in phase then gate 121 produces positive going pulses having a width proportional to the misalignment of the input signals. The pulse output of gate 121 is averaged by an integrator formed by resistor 132 and capacitor 133. The average output is applied to the remaining input of comparator 131 which produces an output for line switch control 34 based upon the reference level provided by gate 122.

Similarly, the state of signal alignment with data signals is provided by the output of gate 120 which feeds an average detector formed by resistor 134 and capacitor 136. Tills average signal is compared to the reference level derived from gate 122. It should be pointed out that the reference levels applied to comparator 131 corresponds to the predetermined value of misalignment of the clock signals. The reference level applied to comparator 129 similarly corresponds to a predetermined value or signal misalignment. Also present in detector 119 is jack 140 which provides a pulse wave form output from the inverting output terminal of gate 121 which may be used to observe pulse widths as an indication of clock misalignment.

Section B is simply shown as a block since its internal circuitry is identical to that of Section A. Both sections of detector 119 provide output signals indicative of the relative alignment of the data and clock signals for each rail of the signal channel so that line switch control 34 may initiate a procedure for channel substitution in accordance with the output of the violation monitors of FIG. 1, In a specific application, the A rail and B rail channel signals carry digital information at the Bell System DS3 rate (44.736 MBPS) with both rails modulating in tandem an IF carrier of 70 MHz, so that one rail falls in the frequency spectrum below the carrier and the other is ln the frequency spectrum above the carrier. The actual signal that this arrangement operates with is the uncoded unipolar data signal although the transmitted signal is coded bipolar three-zero-substitution (B3ZS). In the B3ZS coded data format, correct determination of its uncoded value requires memory of a finite span of prior data.

Accordingly, error free protection of the latter may not be provided by mere alignment of two B3ZS signals which is avoided by working directly with the uncoded unipolar data signals.

In the design of the actual circuitry, each one of static aligners 18 was designed to provide up to 335 NSEC of delay which corresponds roughly to 15 bit periods. Each bit period has a duration of 22.35 NSEC at the DS3 rate. As previously mentioned, the purpose of static aligners 18 is to reduce the static delay between channels to a range corresponding to the capability of dynamic aligner 29 in the protection channel. Dynamic aligner 29, in this case, lias a total range of 9 bits or about 223 NSEC ol' delay. This range is further divided into a fine portion with 21 to 63 NSEC of delay in increments of 2 NSEC and a coarse portion of zero to 156 NSEC of delay in bit increments of 22.55 NSEC each.

The alignment procedure basically combines two operations; first fine clock alignment from clock signals extracted from each channel signal is achieved, then data alignment is provided using course delay shifts of bit periods.

PIG. 6 is a flow chart of the channel signal alignment procedure used by control 34 to substitute the protection channel for a regular channel. Three different symbols are utilized: ovally shaped symbols indicate the beginning and ending of the routine; rectangular symbols, commonly referred to as operational blocks, require the performance of a particular operational step; and diamond shaped symbols, commonly referred to as either conditional branch points or decision blocks, require a test to be performed to determine the course of the following operation. The procedure starts with alignment up (ALNUP) oval 601 when one of violation monitors 20 signals an error condition. Additionally, it should be pointed out that a manual switch by an attendant may be used to start ALUP.

This manual operation is a convenience provided for maintenance purposes. At this point, the head end bridging is completed so both the troublesome regular channel and the protection channel are carrying the same digital bitstream.

At conditional branch point 603, a check is made for an out-of-frame condition from the violation monitor for the troublesome regular channel. If framing is out, block 60% is the next step. Since an out-of-frame condition is an extreme error condition, set switch operate (SWOP/A&B) for the A and B rails are indicated in block 6()/(. Simply slated, this is a direct substitution of the protection channel for tiic regular channel without the benefit of signal channel alignment. in block 60b, u set no alignment flag (N A KL(j) is used to indicate this operational status liefore proceeding Lo oval 60?. These two simple operations of block 60% and 606 effectively bypass the alignment procedure, when its attempt would be futile.

If framing is maintained, as is the more normal course of operation, the next event is branch point 608.

At conditional branch point 608, the status of a switch is checked to ascertain if the A rail is actually being utilized to carry information. If not, the procedure advances to block 609 aiidset switch operate for the A rail (SWOP/α) is done to produce a dii’ect substitution for the A rail portion hy the A rail portion of the protection channel. This bypasses block 611 which calls alignment up subroutine for the A rail (CAUS/A) which will be described in connection with PIG. 7. The same type of operation is now done for the B rail using the operations specified by blocks 512 and 613. Also, if the B rail is not being used, the procedure is to bypass block 613 via block 614 which directs the setting of switch operate for the B rail (SWOP/B), FIG, 7 is a flow chart of the alignment procedure which ia utilized for either rail of the channel signal.

At the beginning of the procedure in block 711, the alignment clock flag is assigned a zero value and the loop point (LPT) is assigned a value of four. Next, at conditional branch point 712 clock alignment is checked.

If clock signal alignment is present the procedure advances to conditional branch point 713. If, however, clock signal alignment is not present, the next operation is call alignment clock check (CACCK) 714, which is another subroutine to he described hereinafter, to provide the alignment before advancing to branch 713. At branch point 713 call alignment data check (CADCK) is still another subroutine.for providing data alignment after clock signal alignment. 11' both clock and data alignment, are obtained then the procedure advances to block 715 wherein the fine position value of the dynamic aligner 29 in FIG. 4 is recorded and tiie next step is return 716.

If neither data nor clock alignment is completed at conditional brandies 713 and 714, the next operation is to increment tiie fine position number in block 717.

Block 718 is used to reset the alignment clock flag when data alignment is not obtained before arriving at block 717. With the new incremented value of the fine position number, the next operation is to call the fineout subroutine (CFTS) indicated in block 719. This subroutine is described in connection with FIG. 8.

Next in the procedure is conditional branch point 721. Therein the final position number is checked for the value of 17. If the fine position number has not been incremented up to value 17, the flow loops back to conditional branch point 714. If the value is 17, the next operation is to call alignment clock check (CACCIi) at branch point 722. Now clock alignment is checked and if alignment is ascertained, the next operation is to call alignment data check (CADCK) at conditional branch point 723. If the two conditions of clock and data alignment are verified, the procedure advances to block 715.

If not, the flow is directed to block 724 wherein the position number is decremented. Block 726 resets the alignment clock flag back to zero. This means that since data alignment could not be obtained the original status of clock alignment was in error and the clock alignment has to be redone. After the fine position number is decremented, the next operation is block 727 wherein the subroutine of FIG. 8 is used.

The next step in the procedure is the test of 10 conditional branch point 728 wherein an initial value of the fine position number is checked. If the initial value is not obtained, then the flow loops back to conditional branch point 722. When the initial value is obtained, the flow advances to conditional branch point 729 wherein the status of the loop point is checked for zero. If not, the procedure loops back to conditional branch point 714 via block 731 wherein the loop point number is decremented.

Should the loop point number reach zero at conditional branch point 729, it signifies that the operations that occur in the procedure from conditional branch point 714 through to 729 have been performed four times without obtaining data or clock alignment. The error condition of the regular channel has thus been present too long, andthe procedure advances to block 732 which directs the setting or completion of the switch operate A rail signal path. The next step is block 733. In block 733, an Initialization of alarm (ITAM) operation serves to indicate the status of the alignment operation on a control panel at the equipment site for maintenance purposes.

FIG 8 is simply a direct sequence of operations for applying the new number value of FINE to dynamic aligner 29 of FIG. 4. First, block 801 specifies writing the new FINE value out of control 34 of FIG. 1. Then, in block 802, start strobe pulse (SSP) directs the beginning of the strobe pulse for lead 113 which duration corresponds to an amount in accordance with block 803. After the new value of FINE is applied to the latches 106 and 107 of aligner 29, block 804 specifies end strobe pulse (ESP).

Block 805 provides another delay before going back to block 721. This enables the integration operation of aligner 29 to stabilize at a new value in accordance with the readjusted channel signal alignment.

FIG. 9 is a flow chart of alignment clock check which is called at conditional branch points (labeled CACCK) 714 and 722 in FIG. 7. At the start of the procedure, conditional branch point 901 requires a verification of the status of the alignment detector. A logical one indicates that clock alignment is present while a logical zero represents the opposite condition. This is obtained simply by logically inverting the output signal produced by the detector of FIG. 5, When signal alignment is out, the procedure advances to decision block 902 which checks the status of the alignment clock (AC) flag which may have been reset at one of block 718 or 726 of FIG. 7.

If not, block 903 is next wherein the fine position number (FP#) is stored before advancing to block 904. In block 904, a bit designated as carry reset and no return is established. This advances the procedure to the next operational block in FIG. 7 which may be either one of block 717 or 724.

If the alignment clock flag is set at conditional branch point 902, the flow advances to block 907 which utilizes the fine position number previously stored in block 903. Next block 908 calls the fine out subroutine (CFTS). This subroutine as previously mentioned is represented by FIG. 8 and is used to change the fine increment setting of dynamic aligner 29 in FIG. 4. Then the procedure advances to block 909 which sets the bit designated as carry set and yes return before advancing to either 713 or 723 as may he appropriate.

The route in the flow chart of FIG. 9 described in the immediately foregoing paragraph serves to double check the performance of the detector of FIG, 5. In other words once clock alignment seems to be established, but a subsequent change in the dynamic aligner setting was not necessary, the previous setting is used. It should be pointed out, however, that this performance characteristic is related to the hardware being used and the choice of magnitude for the fine increment.

At conditional branch point 901, an indication of 5 clock alignment advances the procedure to conditional branch point 912. At branch 912, the status of the alignment clock flag setting is ascertained. If the alignment clock flag is not set, the flow advances to block 913 which calls for setting the alignment clock (AC) flag before advancing to block 903. If at conditional branch point 912, the alignment clock flag has been already set the procedure advances to operational block 909. Advancement from that point forward is as has been previously described.

The latter described path indicates that clock alignment has been established even after a second change in the fine increment setting of dynamic aligner 29. As previously described, this is required due to a certain amount of play in the alignment detector circuit of FIG. 5 in relation to the selection of the magnitude of the fine increments being used. A condition of first obtaining clock alignment is represented by advancing from branch point 912 to block 903 via block 913.

FIG. 10 depicts a flow chart of the procedure for obtaining data alignment. The procedure of FIG. 10 is initially utilized at either conditional branch point 713 or 723 of FIG. 7. Subsequently, this procedure is also used in FIG. 15. In FIG. 7, data alignment occurs after clock alignment is obtained. At the start, the status of the data alignment by alignment detector 91 of FIG. 5 is ascertained. If the data is in alignment for the regular and the protection channels, the alignment data (ALD) bit is set to a logical one value at conditional branch point 1001. Next, operational block 1002 requires either switch operate A or B to be set as appropriate.

Accordingly, an operation commences for substituting the appropriate signal rails of the protection channel for the regular channel. Finally, in operational block 1003 a single bit is set designated as carry and yes return for exiting at the yes output which advances the general procedure, in this case, to operational block 715 of FTO. 7. Conditional branch points 1006 and 1007 also provide entry into block 1002.

Back at conditional branch point 1001, a logical zero value for the ALD bit results in an advancement to operational block 1008 wherein the initial value of the bit position number (BP#) is obtained. It should be pointed out that the implementation of dynamic aligner 29 of FIG. 4 provides a range of 7 bits by virtue of shift register 109. Multiplexer 111 then selects one of the outputs of register 109 in accordance with the input from latch 107 in FIG. 4. In this case an initial value of 3, corresponding to a 3 bit delay, is set in block 1008 before advancing to conditional branch point 1009 which checks to see that the bit position number has not obtained maximum value. If the bit position number is not maximum, the flow advances to block 1011 wherein the bit position number is incremented before advancing to block 1012.

In block 1012, a bitout subroutine is called (CBTS) which is illustrated in FIG. 11.

Accordingly, this changes the value of the bit delay provided by dynamic aligner 29 of FIG. 4 before the output of alignment detector 91 is checked at conditional branch point 1006. Should the increment in block 1011 not produce data bit alignment, the flow advances from conditional branch point 1006 to conditional branch point 1013 wherein the status of clock alignment is checked again. If clock signal alignment is not indicated then the flow advances to operational block 1014 wherein a bit designated as carry reset and no return is set accordingly before exiting at the no output. As a result, the flow in the general procedure of FIG. 7 arrives at the appropriate one of block 718 or 726 back in FIG. 7.

Should clock signal alignment be indicated the flow advances to conditional branch point 1016 wherein the current bit position number is checked to see if it equals the saved value. If so, the flow advances to block 1014.

If not, the flow advances to conditional branch point 1017 wherein the bi (. position number is cheeked again for a maximum value. If not, the flow loops back to block 1011 for incrementing the bit position number again. When the bit position number reaches the maximum, the flow advances to operational block 1018 for decrementing it before advancing to block 1019 which readjusts dynamic aligner 29 before checking the output of detector 91 as required at conditional branch point 1007. Should data alignment not be obtained due to decrementing the bit position number in accordance with block 1018 then, conditional branch point 1021 is next. If, on the other hand, data alignment is obtained upon checking the value of the ALD bit, the flow advances to block 1002.

At conditional branch point 1021 the absence of clock alignment directs the flow to block 1014. If the clock alignment is still indicated, the flow may loop back to operational block 1018 via conditional branch point 1022. When the bit position number has reached zero conditional branch point 1022 loops the flow back to operational block 1011 for incrementing.

FIG.11 is a sequence utilized to reset the value of the data bit delay utilized in dynamic aligner 29 in accordance with the procedure of FIG. 10. It should be pointed out that it is identical to that of FIG. 8 for the fineout subroutine. Both only serve to produce a strobe pulse of fixed duration. Accordingly, reference numerals in FIG. 11 whose last two digits correspond to those of FIG. 8 are used to designate equivalent operational blocks.

FIG. 12 depicts the general procedure for taking down the protection channel. The point of operation for the system of FIG. 1, at this time, is that the protection channel has been substituted for one of the regular channels and violation monitor 33 indicates that transmission quality of the regular channel is restored. Accordingly, the reverse procedure is being implemented so that the protection channel may be removed from service by 3 3 substituting the regular channel back in service. This frees the protection channel for ready availability as a spare for substitution when necessitated by an error condition in any one of the regular channels.

The procedure starts with alignment down (ALNDN) oval 1201. Conditional branch point 1203 is next wherein the framing condition of the protection channel is checked. If the protection channel is out-of-frame (PC OCF), precision alignment is not warranted and is effectively bypassed via operational block 1204 and 1206. In block 1204, switch operate (SWOP) for the A railand Blfrail are reset. As a result, an immediate substitute of the regular channel for the protection channel is initiated.

In block 1206, the no alignment (NA) flag is reset before proceeding to an initial condition as represented by oval 1207.

If, on the other hand, the protection channel has current framing, conditional branch point 1208 is next after branch point 1203. At branch point 1208 utilization of the A rail is checked and if the A rail is not being used, operational block 1209 is next wherein switch operate for the A rail is reset. If at conditional branch point 1208 the Aik rail is being utilized, operational block 1211 is next. Block 1211 calls alignment down subroutine for the A rail (CADS/A). This subroutine is described in the subsequent discussion of FIGS. 13 and 14. Next in the procedure, an equivalent operation is provided by conditional branch point 1212 and operational blocks 1213 and 1214 as conditional branch point 1208 and operational blocks 1209, 1211 except for the B rail.

FIG. 15 which indicates the manner of combining FIGS. 13 and 14 to complete the alignment down subroutine, is utilized for either the A rail or the B rail respectively at operational blocks 1211 and 1213 of FIG. 12. The procedure starts with operational block 1301 wherein the loop point value is initialized to zero and the alignment clock flag is also set to zero before proceeding to conditional branch point 1302. At conditional branch point 1302, the clock alignment and data alignment outputs of alignment detector 119 are both checked to ascertain alignment. When both are in alignment, the procedure for slowly shifting the delay of the channel in service is bypassed by proceeding to operational block 1401 of FIG. 14 to provide an immediate channel substitution. The slow shifts in delay provided by single steps of the fine position number are utilized to prevent a loss of framing synchronization of the system of FIG. 1 while in operation.

Then, operational block 1402 requires the fine position number (FPSfi) and bit position number (BPS^) to both be initialized since the substitution of the regular channel for the protection channel has already occurred in accordance with the operational step of block 1401.

Operational blocks 1402-1405 serve to establish a strobe pulse of a duration corresponding to the value of the delay required by block 1404. Dynamic aligner 29 is thus adjusted to correspond to the Initial values for the fine position number and bit position number designated in block 1402. Oval 1406 which is next represents that the protection channel is now a standby channel with a propagation delay set at initial values available again for substitution of the next regular channel when the need arises.

At conditional branch point 1302 an indication of neither clock alignment nor data alignment provided by alignment detector 91 places conditional branch point 1303 next. Branch point 1303 calls for alignment clock check which is illustrated in FIG. 9. If clock alignment is indicated, conditional branch point 1304 follows. If data alignment is obtained, the procedure advances to block 14Q1. If not, operational block 1306 will follow. Block 1306 requires the alignment clock flag to be reset before advancing to operational block 1307, Block 1307 directs that the fine position number be decremented one position, and then in operational block 1308 the reduced fine position number.is utilized to adjust dynamic aligner 29 in accordance with procedure illustrated by §3033 FIG. 8.

Conditional branch point 1309 requires the status oi the fine position number to be cheeked for a aero value. If this value has not been obtained, the procedure loops back to conditional branch point 1303 so that the fine position number may again be decremented one more step if necessary. Accordingly, this loop back will be utilized until either clock and data alignment are obtained or the fine position number is reduced to zero. When the latter occurs, conditional branch point 1311 is next which again is the alignment clock procedure of FIG. 9.

Associated with conditional branch point 1311 are conditional branch point 1312, 1313 and operational block 1314-1316 which is the same type of procedure as that associated with conditional branch point 1303 except that now the fine position number is increased by incrementing. Again if clock and data alignment are obtained, the procedure advances to operational block 1401. Should neither be obtained before the fine position number reaches a maximum value, conditional branch point 1411 is next.

At this point, associated with branch point 1411 are conditional branch points 1412, 1413 and operational blocks 1414-1416 which provide the same type of procedure wherein the fine position number is again decremented until the initial value is reached. At this point, conditional branch point 1417 follows to check for a loop point value of ten. Until this value occurs, the procedure loops back to conditional branch point 1303 via operational block 1418 which increments the loop point once for each loop back.

If the decrementing and incrementing operations associated v/ith conditional branch points 1303, 1311 and 1411 do not provide both clock and data alignment before the loop point of ten is obtained, the procedure advances to operational block 1419 wherein the alarm status is updated before advancing to operational block 1401 wherein the regular channel is substituted for the protection channel without the benefit of alignment. However, in the vast majority of S3033 cases, it should be pointed out that clock and data alignment will be obtained before reaching a point where the protection channel is simply switched to the regular channel without the benefit of channel signal alignment.

Normally, the occurence of clock and data alignment enable an error free substitution of the regular channel for the protection channel in the alignment down procedure.

It should be pointed out that the procedure of FIG. 15 is used to adjust the signal timing of a channel while actually in service. Accordingly, the individual adjustment steps of dynamic aligner 29 were chosen to be small (e.g,, 2 NSEC). This provides a tolerable transition or jitter between steps for the equipment of the system which maintains framing synchronization. The controller of FIG. 16 is also implemented to provide a tolerable spacing between successive adjustment steps of dynamic aligner 29 to preserve framing integrity in the transmission system.

FIG. 16 is an arrangement for line switch control 34 which follows the various procedures illustrated in FIGS. 6 to 14. The heart of central processor unit (CPU) 1601 is microprocessor 1602 which may be one of any various microprocessors that are commercially available. In one implementation, an Intel 8085 and compatible associated elements were implemented. The 8085 and its operation are described in MCS 85 User's Manual, published by Intel, dated March 1977. Programming of the 8085 is described in the Intel 8080/85 Assembly Language Programming Manual, dated 1977. Associated clock 1603, in this case, was selected to run at a 4 MHz rate. Data memory 1604 stores data from internal operations available from microprocessors 1602 via bus 1606.

Bus 1606 is connected to bus buffer 1607 and extends beyond as bus 1608 to connect the remaining components to help in forming control 34. Memory 1609 provides the stored program for microprocessor 1602. The input/output unit (I/O) 1611 issues control signals for transmit switch 21 of FIG. 1 and receives switch verification signals. Input/output unit (Γ/0) 1612 provides the same function for receive switch 31.

Similarly, I/O 1613 is instrumental in controlling the operation ol common switch 32. Information on channel alignment to be processed in providing error free channel substitution under the direction of CPU 1601 is obtained from interface 1614 which also serves to change the delay in dynamic aligner 29. Also on bus 1608, I/O 1616 directs the input selection used in each of receive line switches 19. Error circuit 1617 provides the error processing from each of violation monitors 20 and violation monitor 33 used as the switch request information for initiating channel substitution.

Claims (17)

1. A channel protection switching arrangement Including means for shifting the relative timing between digital signals of an impaired channel and a 5 protection channel, control means for adjusting the shifting means to achieve channel signal alignment by first adjusting the shifting means in fine increments to achieve bit timing alignment of the digital signals, and then adjusting the shifting means in coarse 10 increments to achieve data alignment of the digital signals, and switching means for substituting the protection channel for the impaired channel after channel signal alignment.

2. An arrangement as claimed in claim 1 including 15 detecting means for indicating data signal alignment and alignment of clock signals derived from the channel signal, and wherein the control means serves to adjust the shifting means, in dependence upon indications of the detecting means, by first aligning the clocking signals 20 by adjusting the shifting means in fine increments to vary the timing of one of the digital signals and its derived clocking signal, and then aligning the bits of the digital signals by adjusting the shifting means in bit increments for one of the digital signals, and to direct the 25 switching means to substitute the protection channel for the impaired channel after channel signal alignment.

3. An arrangement as claimed in claim 2 wherein the shifting means includes delay means for varying the timing by changing the effective propagation delay of 30 one of the digital channels.

4. An arrangement as claimed in claim 3 wherein the delay means includes a plurality of serially connected retiming means and serially connected adjustable delay elements, the adjustable delay elements being for receiving the clocking signal and controllable by the control means for varying the timing of the clocking signal in fine increments, and the plurality of retiming means being for receiving the digital channel signal, 5. Each timing means serving to produce a digital output whose timing is determined by a time varied clocking signal from one of the adjustable delay elements to produce a shifted digital channel output signal.

5. An arrangement as claimed in claim % wherein 10 the delay means includes shift register means for receiving the digital channel signal from the final retiming means and a time varied clocking signal from the final delay elemenl and for producing a plurality of successive digital outputs having successively shifted 15 bit positions, and selector means for receiving the channel signal input to the shift register means and the successive digital outputs from the shift register means, the control means serving to control the selecting means to select one of the inputs thereto to 20 provide full bit increment timing shifts by the shifting means.

6. An arrangement as claimed in any one of claims 2 to 5 wherein the shifting means has an output for the time shifted digital channel signal, and an 25 output for the time shifted clock signal,

7. An arrangement as claimed in any one of claims 2 to 6 wherein the detecting means includes first and second gating means each having two inputs, the first gating means being for receiving both digital signals and the eecond 30 gating means being for receiving clocking signals derived from both digital signals.

8. An arrangement as claimed in claim 7 wherein the detecting means includes first and second averaging means for receiving outputs of the first and 3S second gating means.

9. , An arrangement as claimed in claim 8 wherein the detecting means includes first and second 38 comparators each having its own predetermined reference level lor respectively comparing output from the first and second averaging means 10 provide a signal indicative ol bit alignmenl, and a signal indicative ol clock alignment, respectively. 5 10. An arrangement as claimed in any one of claims 2 to 9 wherein the shilling means is serially connected in the protection channel. 11. An arrangement as claimed in claim 10 including static delay means serially connected in each

10. Regular digital channel to provide a prescribed amount of delay for each channel whereby their total delay is within the adjustable range of the shifting means in the protection channel.

11. 12. An arrangement as claimed in any one of 15 claims 2 to 11 wherein the control means includes first logic means for adjusting the shifting means in fine steps in a first direction from an initial value to a first extreme value and then in the opposite direction from the first extreme value to the opposite extreme value, the first 20 logic means being responsive to an indication of clock signal alignment from the detecting means to stop fine step adjustment of the shifting means, and second logic means for adjusting the shifting means in coarse steps in one direction to an extreme value and coarse steps In 25 the reverse direction to the opposite extreme value, the second logic means being responsive to an Indication of data signal augment from the detecting means to stop coarse step adjustment of the shifting means.

12. 13. An arrangement as claimed in claim 12 30 wherein the control means includes recycling meane for reactivating the first and second logic means if the detecting means fails to indicate alignment after use of the first and second logic means. 1¼ An arrangement as claimed in claim 13 35 wherein the control means includes means for providing a predetermined value before the first logic means is initially used, menus for changing the predetermined 36 value each time the recycling means is used, and means for activating the switching means when the changing of the predetermined value by the changing means reaches a prescribed limit.

13. 15. An arrangement as claimed In claim 12, 13 or 5 14 wherein the control means includes means for checking the detecting means for indication of clock signal alignment after the second logic means adjusts the shifting means each coarse step in a first direction when the detecting means fails to indicate data alignment, 10 and for signalling the first logic means when clock signal alignment is not indicated so that the shifting means will be readjusted to provide clock signal alignment.

14. 16. An arrangement as claimed in claim 15 wherein the control means includes means for checking the 15 detecting means for indication of clock signal alignment after the second logic means adjusts the shifting means each coarse step in a second direction when the detecting means fails to indicate data alignment, and for signalling the first logic means when clock signal 20 alignment is not indicated so that the shifting means will be readjusted Lo provide clock signal alignment.

15. 17. An arrangement as claimed in any one of claims 12 to 16 wherein the control means includes means for retarding the shifting means a fine step reverse 25 to the direction of adjustment once the detecting means indicates clock signal alignment, and for using the first fine steps as the adjustment for the shifting means that produces a reliable clock signal alignment indication from the detecting means. 30

16. 18. An arrangement as claimed in any one of claims 1 to 17 wherein the control means is a microprocessor.

17. 19. A channel protection switching arrangement substantially as herein described with reference to the accompanying drawings.