IE50819B1

IE50819B1 - Semiconductor storage cell

Info

Publication number: IE50819B1
Application number: IE421/81A
Authority: IE
Original assignee: Itt
Priority date: 1980-03-01
Filing date: 1981-02-27
Publication date: 1986-07-23
Also published as: JPS56134776A; EP0035160B1; DE3007892A1; EP0035160A1; DE3160505D1; HK45485A; DE3007892C2; SG38084G; IE810421L

Abstract

1. Floating-gate storage cell consisting of an n-channel field-effect transistor whose potentially floating gate electrode comprises a first electrode part which, for effecting the tunnel injections of electrons into the gate electrode (1), is coupled capacitively to a writing electrode (4), as well as a second electrode part of polycrystalline silicon which, for effecting the tunnel emissions of electrons from said gate electrode (1) during the erasing operation, is coupled capacitively to an erasing electrode (3), characterized in that moreover said gate electrode (1) is coupled capacitively to a programming electrode (2), that said writing electrode (4) is connected directly in a barrier-free contact to the drain zone (5) of the field-effect transistor, and that the coupling capacitance of said programming electrode (2) towards said gate electrode (1) is greater than that of said writing electrode (4) towards said gate electrode (1) and greater than that of said erasing electode (3) towards said gate electrode (1).

Description

Semiconductor storage cell with floating gate with writing and erasing electrodes The invention relates to a non-volatile storage cell containing an n channel floating gate storage transistor capable of being electrically written into or erased, no hot electrons being used either for writing or for erasing. Writing and erasing is in fact effected by tunnel injection or emission of (cold) electrons into or out of the floating-potential gate electrode respectively.

The technical journal Electronics of September 13, 1979, pp. 39 and 40 and of October 11, 1979, pp. Ill to 116, made known such a storage cell containing an n-channel field-effect transistor whose gate electrode contains floating-potential electrode parts of polycrystalline silicon which are coupled capacitively to a writing electrode consisting of polycrystalline silicon and to a programming and erasing electrode.

During the writing and erasing process the electrons tunnel through a thin oxide layer produced on the polysilicon by thermal oxidation, i.e. from the polysilicon into a conductive layer above it.

The known storage cell furthermore contains a flip-flop cell with six field-effect transistors, the contents of which can, if necessary be written into the semiconductor storage cell comprising the floating-potential gate electrode. The known storage cell therefore requires a relatively large 50818 amount of space.

The invention is based on the conventional storage cell and thus relates to a semiconductor storage cell according to the preamble of Claim 1.

It is the object of the invention to provide a semiconductor cell requiring a substantially smaller surface area than the conventional cell.

According to the invention, this object is achieved by the embodiment described in the characterising part of Claim 1.

Preferably, as in the known type of storage cell, the writing electrode is coupled capacitively to the gate electrode via a first insulating layer consisting of an oxide layer grown by thermal oxidation on the writing electrode, and the erasing electrode is coupled capacitively to the gate electrode via a second insulating layer consisting of silicon oxide grown by thermal oxidation on the gate electrode 1. This facilitates tunnelling of the electrons into or out of the gate electrode respectively, with the thicknesses of the insulating layers to be tunnelled and adjoining the gate electrode ranging between 10 nm (100 A.U.) and 80 nm (800 A.U.).

From semiconductor storage cells as hereinafter described it is possible to bufLd up a bitwise erasable or writable storage matrix having a particularly small space requirement. For this purpose, the drain zones and the source zones of one column, as is evident from the examples of embodiment to be described hereinafter, or of one row, are assembled to form in each case a continuous zone strip in the substrate. Transversely in relation thereto and insulated therefrom there SOS 1 0 extend the programming conductor strips to which the programming electrodes are connected, and the gate line conductor strips which are electrically connected to the erasing eletrodes. The active regions of the individual semiconductor storage cells according to the invention, when looked at from the storage cell in question, thus in each case lying within a rectangle formed by the outer edges of a neighbouring pair of zone strips and a programming line together with the neighbouring gate line.

One particular advantage results from the fact that surface portions of the zone strips and of the lines can be utilised for accommodating the active regions of the individual storage cells.

The gate electrode, the writing electrode and the drain zone lying directly below the writing electrode in barrier-free contact therewith are n-doped, and preferably highly n-doped, in the storage cell, according to the invention.

In the following the semiconductor storage cell according to the invention will now be explained in greater detail with reference to examples of embodiment shown in the accompanying drawings, in which: Figure 1 shows a cross-sectional view of the storage cell according to the invention in order to illustrate the design principle, Figure 2 shows the basic circuit diagram of 30 a four-bit storage matrix employing four conductor cells according to the invention, Figure 3 is the plan view of a storage cell according to a first example of embodiment, Figure 4 is the plan view of a storage cell 35 according to a second example of embodiment, 50818 Figure 5 is the plan view of a storage cell according to a third example of embodiment, Figures 6, 7 and 8 are cross-sectional views of the storage cell shown in Figure 5 along the section lines Bhown therein.

Figure 9 is the plan view of a storage cell employing a reading field-effect transistor according to a further embodiment of the storage cell of the invention as a fourth example of embodiment, Figure 10 shows the equivalent circuit diagram relating to the storage cell according to Figure 9, Figure 11 shows schematically and in a sectional view a fifth example of embodiment according to an extension of the storage cell shown in Figure 9, Figure 12 shows a further embodiment of the storage cell shown in Figure 11, and Figure 13, in a plan view, shows a topological layout of the storage cell according to Figure 11.

In the following the design principle and the mode of operation of the storage cell according to the invention will now be explained with reference to Figure 1. For manufacturing such a storage cell, first the source zone 9 and the drain zone 5 are diffused into a p-doped silicon substrate 6 in the conventional way by employing photolithography and a planar diffusion process. Onto the surface side thereof comprising the diffused zones there is deposited a thick oxide 11. Into this, in order to expose substantial surface areas of both the drain zone 5 and the area of the gate oxide 12, there is etched an opening.

Thereafter, by thermal oxidation, the gate oxide 12 ie produced and the drain zone 5 is exposed. Subsequently, n-doped polycrystalline silicon is deposited over the upper surface side of the arrangement, and the part of the gate electrode 1 to be made over the gate oxide 12, as well as the writing electrode 4, are etched out of the continuous polycrystalline silicon layer. This is followed by a thermal oxidation process for producing the first insulating layer 7 within the writing transition area in a thickness ranging between 10 nm (100 A.U.) and 80 nm (800 A.1).). In connection with the gate electrode 1 there are now produced further electrode parts which, at least below the second insulating layer 8 which is still to be produced and which forms the erasing transition area, are produced from n-doped polycrystalline silicon, if use is made of the advantages offered by a transition according to the aforementioned literature passage which can be easily tunnelled by electrons from the gate electrode 1 to the erasing electrode 3.

Accordingly, for manufacturing a semiconductor storage cell according to the invention it is in principle only necessary to carry out one process of deposition of a polycrystalline silicon layer, because merely the writing electrode 4 and the electrode part of the gate electrode 1 located beneath the erasing electrode 3 have to consist of polycrystalline silicon, if it is intended to make use of the well-known advantage of a transition which is produced by thermal oxidation on a polycrystalline silicon, and can be easily tunnelled by electrons. The writing transition surface formed by the first insulating layer 7 can 50818 in fact be arranged next to the erasing transition surface constituted by the second insulating layer 8, unlike in Figure 1, and the erasing electrode 3 as well as the programming electrode 2 can consist of a metal.

Finally, following the deposition of a second insulating layer 8 and of a third insulating layer 10, both the programming electrode 2 and the erasing electrode 3 are produced by evaporation and by employing a photolithographic etching process.

Figure 2 illustrates the use of storage cells according to the invention with a four-bit storage matrix. In this, independently of the size of the matrix, the source zones 9 are assembled in a columnwise manner to form source zone strips 6, and the drain zones 5 are assembled to form drain zone strips D, and diffused into the silicon substrate 6. The programming of the storage matrix according to Figure 2, is carried out e.g. in accordance with the following table referring to one programming example.

FI G1 F2 G2 SI DI S2 D2 Erase Til and Tl2: 0 Up 0 0 0 0 0 0 Write 1 into Til; Up Up 0 0 0 0 Up Up Read Til and T12: Ur Ur 0 0 0 Ur' 0 Ur' Wherein Up ·* Programming voltage, Ur »= Reading voltage A Up; Ur' « Effective reading voltage = Ur - AU and AU - Voltage drop at the load element The topography of a semiconductor storage cell according to the invention which can be used with such a storage matrix is shown in Figure 3. The parts of the zone strips SI and DI which are not 50810 covered by electrode parts, on one hand, and the parts of polycrystalline silicon layers which are not covered by the conductor strips FI and Gl, on the other hand, are indicated by cross-batchings in different directions. The programming conductors F and the erasing conductor strips G can be seen to extend transversely in relation to the source zone strips S and the drain zone strips D respectively. On the writing electrode 4 of polycrystalline silicon deposited directly onto the drain zone strip D, the first insulating layer 7 has been produced within the writing transition surface li by thermal oxidation. Subsequent to the production of the gate oxide 12, and in the course of a second process of depositing polycrystalline silicon, the gate electrode 1 is produced above the second insulating layer 8 with a first electrode part 1' above the writing electrode 4 and a second electrode part 1 below the erasing electrode, still to be manufactured. By employing conventional oxidizing, depositing and photolithographic etching processes, there are produced the third insulating layer 10 and the second insulating layer 8 by thermal oxidation within openings of a thick oxide. Subsequent thereto, by evaporation and by employing a photolithographic etching process, and transversely in relation to the source zone strips S and the drain zone strips D, by employing an evaporating process and a photolithographic etching process, there will be obtained the programming conductor strips F covering the third insulating layers 10, as well as the erasing conductor strips G extending over the erasing transition surfaces E.

Figure 4 shows a further example of embodiment of the semiconductor storage cell 50818 according to the invention. Unlike in the semiconductor storage cell according to Figure 3, Figure 4 shows that the erasing transition surface E as well as the writing transition surfac W are arranged below the erasing conductor Strip Gl. Both the source zone strips S and the drain zone strips D are produced, as in all embodiments, in the conventional way by employing a planar diffusion process. In the course of the further manufacture, use is made of two processes of deposition of polycrystalline silicon. In the course of the first deposition process the writing electrode is produced directly on exposed parts of the drain zone strip D, and the gate electrode 1 is produced with parts which, below the programming conductor strip Fl, together with the third insulating layer 10, form the programming electrode and, within the erasing transition surface E above the second insulating layer 8, together with the erasing conductor strip G, form the erasing electrode. Both the insulating layers and the conductor strips are produced in the conventional way, as already described hereinbefore. The symbol Al on the conductor strips indicates that these conductor strips are made of aluminium, because this material is most frequently used for conductor strips in semiconductor engineering.

Here, too, the zone areas and parts of polycrystalline silicon which are not covered by electrode parts are shown by different cross-hatching, the same also applied to the other figures of the drawings.

Figure 5, in a plan view, shows the topography of a storage cell according to the invention relating to a third example of embodiment 50810 requiring merely one process of depositing polycrystalline silicon. This embodiment as shown in Figures 5 to 8, therefore, can be manufactured by employing a standard n-channel silicon gate technology with only one single additionally inserted photo process and a subsequent thin layer oxidation of the first insulating layer 7, the second insulating layer 8 and the third insulating layer 10. The semiconductor storage cell as shown in Figures 5 to 8 is manufactured as described in the following paragraph.

First there is deposited an oxidation masking layer for preventing the semiconductor surface within the line S-D-G shown in Figure 5 from being subjected to thermal oxidation. Following the thermal oxidation in the course of which the thick oxide is formed, the gate oxide 12 is produced within the gate area between the source zones and the drain zones designed as extensions of the source zone strips S and the drain zone strips D respectively, by thermal oxidation of the semiconductor surface exposed within this area. As a material for the oxidation masking layer it is possible to use silicon nitride, which can be removed by means of hot phosphoric acid when an etching masking of silicon oxide is used, or else by plasma etching in cases where a masking of a photoresist is used. Subsequent thereto, the remaining part of the oxidation masking layer is removed and a polycrystalline n-doped silicon layer is deposited over the oxidised surface area of the arrangement. From this layer there is etched out the gate electrode 1 with its extensions, as well as the writing electrtode 4. There now takes place an n-doping diffusion process preferably with the use of phosphorus as the doping agent, thus forming the source zone strips S and the drain zone strips D and, below the writing electrode 4 acting as the diffusion source, a zone area 15. After the corresponding areas of the polycrystalline silicon have been exposed by employing a photolithographic etching process there is produced, as already mentioned, within the erasing transition surface E the second insulating layer 8, within the writing transition surface W the first insulating layer 7, and the third insulating layer 10. Thereupon, there is now deposited a first foreign oxide layer 13 and, by the photolithographic process, contacting openings to the gate electrodes 1 on the one hand and to the writing electrodes 4 on the other hand are made. Subsequently, over the main surface area of the arrangement there is produced a metallic layer, especially of aluminium, by evaporation, and, by the photolithographic process, there is produced a metal pattern containing the erasing conductor strips G, the programming conductor strips F and the connecting strips 16 between the gate electrodes 1, on the one hand, and the writing electrodes 4, on the other hand. Finally, over the main surface area of the entire arrangement, there is deposited, as a protective layer, the second foreign oxide layer (silox).

Figure 9, in a plan view, and as a further embodiment the storage cell according to the invention, shows the topography of a storage cell which, on the source side of the storage transistor, furthermore contains an enhancement reading field-effect transistor Tr which is arranged in series with the storage transistor and whose gate electrode is connected either to the programming 508X8 conductor strip F or the programming electrode. This reading insulated-gate field-effect transistor Tr makes it possible, during the erase operation, to drive the storage transistor up into depletion operation without any danger of errors during the reading of the storage matrix. The additional reading insulated-gate field-effect transistor Tr also in this case guarantees the interruption of the line between the source zone strip S and the drain zone strip D in all non-addressed storage cells of the addressed column, which is absolutely necessary in order to ensure satisfactory read-out.

The storage matrix with the storage cells according to Figure 9 is manufactured in the same way as has already been described hereinbefore with reference to Figures 6 to 8. The gate electrodes of the reading insulated-gate field effect transistors Tr are made simultaneously with both the gate electrode 1 and the writing electrode 4. Figure 10 shows the equivalent circuit diagram relating to a 2x2-bit matrix comprising four semiconductor storage cells according to Figure 9 and, in view of the aforementioned advantage, represents a preferred type of use of a storage cell according to the invention.

Figures 11 and 12 show, in cross-sectional views, space-saving further embodiments of the semiconductor storage cell according to Figure 9. Space saving is due to the fact that the zone resembling a double-gate field-effect transistor between the control electrode S of the reading insulated-gate field-effect transistor Tr and the gate electrode 1 within the semiconductor body is omitted and that this field-effect transistor Tr has been fused with the storage transistor by means of an overlapping gate electrode. This storage cell shown in Figure 11, and the cross-hatched electrode parts of polycrystalline silicon can of course be produced by employing three successive processes of deposition of polycrystalline silicon; but in order to take advantage of the aforementioend effect oi a facilitated tunnelling of a polycrystalline electrode part through a first insulating layer 7 or a second insulating layer 8 deposited thereon by thermal oxidation it is only necessary to produce the writing electrode 4 and the electrode part of the gate electrode 1 lying beneath the erasing electrode 3 from a polycrystalline silicon, so that also for manufacturing the storage cell according to Figure 11 it is necessary to carry out one process of deposition of n-doped polycrystalline silicon.

In any further reduction of the size of the semiconductor storage cell according to the invention it will, however, be necessary to dispense with the connecting strips 16 between the writing electrode 4 and the gate electrode 1, because the contacting openings which are necessary for this purpose require a certain minimum space. The topography as shown in Figure 13 of a storage cell as shown in Figure 11 having a particularly small space requirement without such connecting strips therefore calls for repeated deposition of polycrystalline silicon. For the purpose of adjusting the channel length, n+-doped zones 17 are diffused, by a planar diffusion process, into the surface of the substrate prior to the application of the nitride masking layer, within the area marked by the line S-D-G in Figure 13. For producing the writing electrode 4 there is carried out a first process of deposition of 9 polycrystalline silicon and for producing the gate electrode 1 there is carried out a second process of deposition of polycrystalline silicon. The programming conductor strip can be made either of a metal or polycrystalline silicon.

The embodiment shown in Figure 12 in the same cross-sectional view as in Figure 11 illustrates how the minimum surface-area requirement makes it possible to adhere to the surface ratios, important for both programming and erasing, between the capacitance of the programming electrode as provided by the third insulating layer 10, the writing transition surface W and the erasing transition surface E.

In this particular embodiment, over electrode parts of the gate electrode 1 on parts of the programming electrode 2, there is arranged an insulating layer 10', and thereupon a conducting layer 2’ which is in contact with the gate electrode 1.

The embodiment shown in Figure 12, therefore, with a minimum surface requirement, makes it possible for the capacitance between the programming electrode 2 and the gate electrode 1 to be made sufficiently large not only with respect to the capacitance between the erasing electrode 3 and the gate electrode 1 but also with respect to the capacitance between the writing electrode 4 and the gate electrode 1. For the coupling capacitance of the programming electrode 2 with the gate electrode 1 should in principle, in the storage cell according to the invention, be at least four times greater than that of the writing electrode 4 with the gate electrode or than that of the erasing electrode 3 with the gate electrode. In the case of a storage cell according to Figure 12 thi6 condition can be complied with, with a small surface requirement, even in the case of substantially larger capacitance ratios.

During the programming operation the programming electrode serves as a kind of bootstrap capacitance towards the gate electrode 1 and in each case determines the potential thereof. The third insulating layer 10 serving as the dielectric of this capacitance, owing to the surface conditions which determine the capacitance relationships, can consist of the same material and be of the same thickness as those of the first insulating layer 7 and those of the second insulating layer 8, because, corresponding to the surface relationships, there is a substantially lower voltage drop across the third insulating layer, thus preventing charge carriers from tunnelling through the third insulating layer 10. An advantage of the storage cell according to the invention lies in the fact that both the programming and the reading voltage can be the same and relatively low, for instance 12 volts.

A favourable effect upon the degradation of the storage cell is achieved through the fact that the tunnel injections take place outside the channel zone.

Claims

1. Floating-gate storage cell consisting of an n-channel field-effect transistor whose potentially floating gate electrode comprises a first electrode part which, for effecting the tunnel injections of electrons 5 into the gate electrode, is coupled capacitively to a writing electrode, as well as a second electrode part of polycrystalline silicon which, for effecting the tunnel emissions of electrons from said gate electrode during the erasing operation, is coupled capacitively to an erasing electrode, wherein said gate electrode is coupled capacitively to a programming 10 electrode, that said writing electrode is connected directly in a barrier-free contact to the drain zone of the field-effect transistor, and that the coupling capacitance of said programming electrode towards said gate electrode is greater than that of said writing electrode towards said gate electrode and greater than that of said erasing electrode 15 towards said gate electrode.

2. A storage cell as claimed in claim 1, wherein said writing electrode, via a first insulating layer of a silicon oxide grown by way of oxidation on said writing electrode, is coupled capacitively to said gate electrode and that said erasing electrode, via a second insulating 20 layer of a silicon oxide grown by way of oxidation on said gate electrode is coupled capacitively to said gate electrode.

3. A storage cell as claimed in claim 2, wherein the thickness of both said first insulating layer and of said second insulating layer ranges between 10 nm (100 8.U) and 80 nm (800 A.U.) respectively. 5081S

4. A storage cell as claimed in any one of claims 1 to 3, comprising a drain zone and a source zone which, together with further drain zones or further source zones of further storage cells of a storage matrix, are designed to have the shape of continuous zone strips extending parallel in relation to one another, for each of said drain zones or each of said source zones.

5. A storage cell as claimed in claim 4, wherein one reading insulated-gate field-effect transistor each is arranged in series between said source zone and said source zone strip, whose gate electrode is in contact with said programming electrode.

6. A storage cell as claimed in claim 5, wherein one programming electrode part extends between said source zone strips and said gate electrode on a portion of the gate oxide, with said part forming the gate electrode of said reading insulated-gate field-effect transistor.

7. A storage cell as claimed in any one of claims 4 to 6, wherein both said erasing electrode and said programming electrode are formed by two conductor strips extending parallel in relation to one another and rectangularly in relation to said drain zones as well as to said source zones, i.e. over the second insulating layer or a third insulating layer.

8. A storage cell as claimed in any one of claims 1 to 7, wherein both said erasing electrode and said programming electrode consist of metal.

9. A storage cell as claimed in claim 8, wherein the erasing transition surface of said erasing electrode is arranged below said erasing electrode, and that the writing transition surface of said writing electrode is arranged in the area between these electrodes not covered by either said writing electrode or said erasing electrode.

10. A storage cell as claimed in any one of claims 1 to 9, wherein said qate electrode as well as said writina electode and the drain zone as disposed directly below said writing electrode, are n-doped at the surface of said mono-crystalline substrate. 5 11. A storage cell as claimed in any one of claims 1 to 10, wherein over electrode parts of said gate electrode on parts of said programming electrode there is arranged an insulating layer and thereupon a conducting layer which is in contact with said gate electrode. 10 12. A storage cell as claimed in any one of claims 1 to 11, wherein the coupled capacitance of said programming electrode towards said gate electrode is at least four times greater than the coupling capacitance of said erasing electrode towards said gate electrode as well as than said writing electrode towards said gate electrode.

11. 15 13. A floating-gate storage cell substantially as described herein with reference to the accompanying drawings.