IE48085B1 - Multiple-access facsimile receiver - Google Patents

Abstract

A multiple-access facsimile signal receiver is connected to a plurality of telephone lines (1, 2 and 3). The receiver includes a single document printer circuit (5), a memory (15) for storing digital facsimile signals as demodulated from the telephone lines by demodulator circuits (12). The facsimile signals are applied to the data input of the memory via a multiplexer (16). The signals are read from the memory by a decoder (20) which applies them in decoded form to the printer via a pair of output buffer registers (21 and 22). A memory read/write control circuit (17) co-ordinates the writing of input data into the memory and the reading of data from the memory. The pooling of memory space between a plurality of lines makes it possible to use less memory than would be required if each line had its own exclusive memory.

Description

MULTIPLE-ACCESS FACSIMILE RECEIVER The present invention relates to the field of facsimile signal transmission. It relates more particularly to a facsimile signal receiver having a plurality of telephone lines assigned thereto, which enable it to receive simultaneously a plurality of facsimile messages each for reproduction as a document.

The present invention provides a multiple-access facsimile signal receiver for connection to n telephone lines assigned thereto, where n is an integer not less than 2, wherein the receiver comprises: document printer means for reproducing documents from facsimile signals received via different ones of the lines; n line circuits each comprising a telephone line connector circuit, a demodulator circuit and a logic control circuit for controlling the connection of the said demodulator circuit to the associated line via the connector circuit to receive facsimile signals from said telephone line; a memory of capacity greater than that required to store the contents of one document to be reproduced; a memory access control circuit having n inputs connected to respective ones of the demodulators and one output connected to an input of the memory, whereby each of the demodulator circuits may be connected to the memory to store facsimile signals from different lines; and a read/write control circuit associated with the memory, the access control circuit and the logic control circuits of the line circuits to define write addresses in the memory for the signals received by the memory from the said lines via the access control circuit, and to define read addresses in the memory for reproducing stored signals corresponding to a single document for application to the printer circuit.

An embodiment o'f the invention is described by way of example with reference to the sole figure of the accompanying drawing which is a block diagram of a multiple access receiver embodying the invention.

The facsimile signal receiver shown in the figure has n telephone lines, referenced 1, 2 and 3 assigned thereto.

In this case, n = 3. The facsimile signal receiver comprises a document printer circuit 5 tor reproducing a document on the basis of facsimile signals received at its input. It further comprises n line circuits i.e. three line circuits referenced 7,8, and 9, where each line circuit connects the circuits of the receiver to one of the telephone lines.

Each line circuit, e.g. the line circuit 7, comprises a line connector circuit 10, a logic control circuit 11 connected to the circuit 10, and a demodulator circuit 12 controlled by the logic circuit 11 and connected to the associated telephone line (in this case 1) via the line connector circuit 10. The line connector circuit 10 matches the DC and impedance characteristics of the facsimile receiver to the telephone line and provides isolation of the metallic path between the telephone line and the circuits of the facsimile receiver. The circuit 10 is of known type and is provided to meet the standards laid down by each country for connecting a facsimile receiver to a telephone line. The logic circuit 11 detects calling signals from the telephone line associated therewith. Before any facsimile signals are received from the telephone line, the logic circuit 11 governs the exchange of signals between the facsimile receiver and the caller necessary for ensuring that the facsimile signals are sent to the receiver while it is in a ready-to-receive condition. The demodulator circuit 12 then receives the signals from the telephone line and demodulates them.

The other line circuits 8 and 9 are analogous to the line circuit 7 described above and are therefore not described themselves.

The output of the demodulator circuit such as 12 of each of the line circuits 7,8 and 9 is connected to a memory 15 via an access control circuit 16. The circuit 16 has n inputs ( in this case n = 3) and a single output connected to the input of the memory 15 . It acts as a multiplexer circuit for the demodulated signals to be written into the memory. The circuit 16 is controlled by a read/write control circuit 17 for supervising the contents of the memory 15.

The control circuit 17 is therefore connected to each of the line circuits 7 to 9. From the line circuits it receives detections of calling signals coming from the associated telephone lines and it either authorizes or refuses the connection of these lines to the receiver as a function of the possibility of storing the received signals. These functions are illustrated by a two-way connection between the control 17 and each of the line circuits 7 to 9. The control circuit 17 further determines the rate at which the signals are input to the memory 15 as a function of the known rate of the signals on each telephone line, e.g. 2400 bits per second, and the number of lines connected to the receiver. It therefore causes the access control circuit 16 to switch its inputs at a rate for suitable multiplexing of the signals received from the lines for writing into the memory. Simultaneously, the control circuit 17 supplies the memory with successive input signal write addresses at its rate of signal input.

The write mode for the signals applied to the input of the memory is defined by the control circuit 17: the signals coming from a single telephone line may be written into a single defined zone by means of a sequence of successive addresses which the control circuit 17 has assigned to signals coming from the line which is connected at that time. Advantageously the facsimile signals will be transmitted on the various telephone lines in compressed form. They will then be stored in the memory 15 in compressed form. The output of the memory 15 is connected to the document printer circuit via a decoder circuit 20 which is associated with two output registers 21 and 22.

The function of the decoder 20 is to transform the signals coming from the memory in compressed form into other signals which are directly applicable to the printer circuit 5. Thus, whether the signals transmitted by each of the telephone lines are compressed by run length encoding of the original document analysis signals and/or a different form of encoding, the decoder performs the inverse transcoding to reproduce signals identical to those which came from the analysis of the original document .

During this process of decoding the signals stored in the memory to reproduce each corresponding document, the decoder requests signals stored in the memory 15 while the control circuit 17, also connected to the decoder, determines the successive addresses for memory reading at the rate of the decoder requests to reproduce stored signals corresponding to a single document. The memory is thus read at a variable rate determined by the decoder and under the control of the circuit 17 which indicates the read addresses.

The two registers 21 and 22 make it possible to deliver the signals coming from the decoder 20 at the document reproduction rate of the printer circuit 5. These two registers are chosen to have a capacity which corresponds to the contents of one line of a document, i.e. which corresponds to the number of points in a scan line of the document. These two registers 20 and 21 are controlled alternately for loading from the decoder. They are also controlled alternately for unloading by a counter 23 each time it passes through predetermined count state corresponding to the number of points in a document scan line. For this purpose, the counter 23 receives clock signals HI at the scan rate of successive points along each document scan line from a clock ( not shown) belonging to the printer circuit. Thus while one of the registers 21 and 22 is being loaded at a variable rate from the output of the decoder, the other is being unloaded at a constant rate given by the printer circuit 5.

This facsimile signal receiver thus enables simultaneous reception of facsimile signals coming from a plurality of callers, with the corresponding documents being reproduced one after the other by a single high-speed printer circuit. The memory 15 thus acts as an intermediate store of the facsimile signals received from the different telephone lines while the associated control circuit 15 supervises the waiting list of documents to be reproduced.

It should be noted that the capacity of the memory 15 should be chosen as a function of the number of accesses to the receiver, however, the capacity need not therefore be proportional to the number of accesses. Thus, supposing the contents of a document in compressed form is in the order of 100 x 103 to 400 x 10 3 bits, a memory with a capacity of about 500 x 103 bits will be chosen for a receiver having only one5 access, where these 500 x 103 bits represent, for example, 400 x 103 bits for receiving a transmitted document and 100 x 103 bits for the beginning of reception of the following document while the previous document is being printed. In contrast, for a multiple access receiver in accordance with the invention, the capacity of the memory can be limited to 750 x 103 bits for a two-access receiver and to 1,000 x 103 bits for a three-access receiver. This possibility of using a memory whose capacity is not proportional to the number of accesses can be explained,firstly by the fact that transmitted documents rarely occupy the maximum amount of store,and secondly by the fact that the time taken to read the stored signals corresponding to a single document, as defined by the printing time (in the order of 20 seconds for a xerographic type of printer circuit) is considerably less than the time take to write the signals corresponding to a transmitted document into the memory. The write time depends on the amount of bits generated from the transmitted document and on the data rate of the telephone line or of the demodulator and is in the order of one minute when using a 4800 bits per second modem.

Claims (4)

1. / A multiple-access facsimile signal receiver for connection to n telephone lines assigned thereto, where n is an integer not less than 2, wherein the receiver comprises: document printer means for reproducing documents from facsimile signals 5 received via different ones of the lines; n line circuits each comprising a telephone line connector circuit, a demodulator circuit and a logic control circuit for controlling the connection of the said demodulator circuit to the associated line via the connector circuit to receive facsimile signals from said 10 telephone line; a memory of capacity greater than that required to store the contents of one document to be reproduced; a memory access control circuit having n inputs connected to respective ones of the demodulators and one output connected to an input of the memory, whereby each of the demodulator 15 circuits may be connected to the memory to store facsimile signals from different lines; and a read/write control circuit associated with the memory, the access control circuit and the logic control circuits of the line circuits to define write addresses in the memory for the signals received by the memory 20 from the said lines via the access control circuit, and to define read addresses in the memory for reproducing stored signals corresponding to a single document for application to the printer circuit.

2. / A multiple access facsimile signal receiver according to 25 claim 1, wherein the said facsimile signals received from the said n lines are in compressed form, and are stored in compressed form and wherein the receiver further comprises a decoder circuit connected to the memory and to the read/write control circuit to receive the said signals stored in the 30 memory from addresses defined by the said read/write control circuit at the variable operation rate of the decoder, and two decoder output registers to apply the said decoded signals to the printer circuit at its constant document reproduction rate.

3. / A multiple-access facsimile signal receiver according to claim 1 or 2, wherein the said memory has a capacity which is less than that needed to store n documents.

4. / A multiple-access facsimile signal receiver substantially 5 as herein described with reference to the accompanying drawing.