ID21939A - Metode permintaan ulang dan deteksi beban dan atau beban - Google Patents
Metode permintaan ulang dan deteksi beban dan atau bebanInfo
- Publication number
- ID21939A ID21939A IDP981693A ID981693A ID21939A ID 21939 A ID21939 A ID 21939A ID P981693 A IDP981693 A ID P981693A ID 981693 A ID981693 A ID 981693A ID 21939 A ID21939 A ID 21939A
- Authority
- ID
- Indonesia
- Prior art keywords
- load
- detection
- method requests
- requests
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3834—Maintaining memory consistency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/021,134 US6148394A (en) | 1998-02-10 | 1998-02-10 | Apparatus and method for tracking out of order load instructions to avoid data coherency violations in a processor |
Publications (1)
Publication Number | Publication Date |
---|---|
ID21939A true ID21939A (id) | 1999-08-12 |
Family
ID=21802532
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IDP981693A ID21939A (id) | 1998-02-10 | 1998-12-28 | Metode permintaan ulang dan deteksi beban dan atau beban |
Country Status (10)
Country | Link |
---|---|
US (1) | US6148394A (id) |
EP (1) | EP0936542A3 (id) |
JP (1) | JP3159435B2 (id) |
KR (1) | KR100335744B1 (id) |
CN (1) | CN1196997C (id) |
CA (1) | CA2260541C (id) |
HK (1) | HK1019799A1 (id) |
ID (1) | ID21939A (id) |
MY (1) | MY122053A (id) |
SG (1) | SG70151A1 (id) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6418514B1 (en) * | 1998-02-17 | 2002-07-09 | Internationl Business Machines Corporation | Removal of posted operations from cache operations queue |
US6704856B1 (en) * | 1999-02-01 | 2004-03-09 | Hewlett-Packard Development Company, L.P. | Method for compacting an instruction queue |
US6738896B1 (en) * | 1999-02-01 | 2004-05-18 | Hewlett-Packard Development Company, L.P. | Method and apparatus for determining availability of a queue which allows random insertion |
US6658554B1 (en) * | 1999-03-09 | 2003-12-02 | Wisconsin Alumni Res Found | Electronic processor providing direct data transfer between linked data consuming instructions |
US6487641B1 (en) * | 1999-04-19 | 2002-11-26 | Oracle Corporation | Dynamic caches with miss tables |
US7089404B1 (en) | 1999-06-14 | 2006-08-08 | Transmeta Corporation | Method and apparatus for enhancing scheduling in an advanced microprocessor |
US7634635B1 (en) | 1999-06-14 | 2009-12-15 | Brian Holscher | Systems and methods for reordering processor instructions |
US6748589B1 (en) | 1999-10-20 | 2004-06-08 | Transmeta Corporation | Method for increasing the speed of speculative execution |
US6678810B1 (en) | 1999-12-30 | 2004-01-13 | Intel Corporation | MFENCE and LFENCE micro-architectural implementation method and system |
DE10121792C2 (de) * | 2000-05-26 | 2003-09-25 | Ibm | Universelle Ladeadresse/Wertevorhersageschema |
JP2003029967A (ja) | 2001-07-17 | 2003-01-31 | Fujitsu Ltd | マイクロプロセッサ |
DE10243446B4 (de) * | 2002-09-19 | 2005-12-15 | Celanese Chemicals Europe Gmbh | Verfahren zur Herstellung von Aldehyden |
JP4327008B2 (ja) * | 2004-04-21 | 2009-09-09 | 富士通株式会社 | 演算処理装置及び演算処理装置の制御方法 |
US7401209B2 (en) * | 2006-06-30 | 2008-07-15 | International Business Machines Corporation | Limiting entries searched in load reorder queue to between two pointers for match with executing load instruction |
US7991979B2 (en) * | 2008-09-23 | 2011-08-02 | International Business Machines Corporation | Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system |
US20120117335A1 (en) * | 2010-11-10 | 2012-05-10 | Advanced Micro Devices, Inc. | Load ordering queue |
US11150836B2 (en) | 2018-06-28 | 2021-10-19 | Seagate Technology Llc | Deterministic optimization via performance tracking in a data storage system |
US10713057B2 (en) | 2018-08-23 | 2020-07-14 | International Business Machines Corporation | Mechanism to stop completions using stop codes in an instruction completion table |
KR20200112435A (ko) * | 2019-03-22 | 2020-10-05 | 에스케이하이닉스 주식회사 | 캐시 메모리, 이를 포함하는 메모리 시스템, 및 그의 동작 방법 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5185871A (en) * | 1989-12-26 | 1993-02-09 | International Business Machines Corporation | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions |
JP2925818B2 (ja) * | 1991-04-05 | 1999-07-28 | 株式会社東芝 | 並列処理制御装置 |
JPH05210586A (ja) * | 1992-01-14 | 1993-08-20 | Nec Corp | キャッシュメモリ制御回路 |
US5467473A (en) * | 1993-01-08 | 1995-11-14 | International Business Machines Corporation | Out of order instruction load and store comparison |
US5420990A (en) * | 1993-06-17 | 1995-05-30 | Digital Equipment Corporation | Mechanism for enforcing the correct order of instruction execution |
US5625835A (en) * | 1995-05-10 | 1997-04-29 | International Business Machines Corporation | Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor |
US5737636A (en) * | 1996-01-18 | 1998-04-07 | International Business Machines Corporation | Method and system for detecting bypass errors in a load/store unit of a superscalar processor |
US5712997A (en) * | 1996-01-31 | 1998-01-27 | Sun Microsystems, Inc | System and method for processing load instruction in accordance with "no-fault " processing facility including arrangement for preserving access fault indicia |
US5809275A (en) * | 1996-03-01 | 1998-09-15 | Hewlett-Packard Company | Store-to-load hazard resolution system and method for a processor that executes instructions out of order |
US5781752A (en) * | 1996-12-26 | 1998-07-14 | Wisconsin Alumni Research Foundation | Table based data speculation circuit for parallel processing computer |
US5898853A (en) * | 1997-06-25 | 1999-04-27 | Sun Microsystems, Inc. | Apparatus for enforcing true dependencies in an out-of-order processor |
-
1998
- 1998-02-10 US US09/021,134 patent/US6148394A/en not_active Expired - Fee Related
- 1998-10-28 MY MYPI98004914A patent/MY122053A/en unknown
- 1998-12-28 ID IDP981693A patent/ID21939A/id unknown
-
1999
- 1999-01-07 CN CNB991010159A patent/CN1196997C/zh not_active Expired - Fee Related
- 1999-01-15 KR KR1019990001066A patent/KR100335744B1/ko not_active IP Right Cessation
- 1999-02-01 CA CA002260541A patent/CA2260541C/en not_active Expired - Fee Related
- 1999-02-03 JP JP02585799A patent/JP3159435B2/ja not_active Expired - Fee Related
- 1999-02-03 EP EP99300779A patent/EP0936542A3/en not_active Withdrawn
- 1999-02-05 SG SG1999000477A patent/SG70151A1/en unknown
- 1999-10-28 HK HK99104881A patent/HK1019799A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN1196997C (zh) | 2005-04-13 |
KR19990072272A (ko) | 1999-09-27 |
CA2260541A1 (en) | 1999-08-10 |
KR100335744B1 (ko) | 2002-05-08 |
JPH11272466A (ja) | 1999-10-08 |
MY122053A (en) | 2006-03-31 |
CN1226023A (zh) | 1999-08-18 |
CA2260541C (en) | 2004-08-10 |
EP0936542A2 (en) | 1999-08-18 |
JP3159435B2 (ja) | 2001-04-23 |
HK1019799A1 (en) | 2000-02-25 |
SG70151A1 (en) | 2000-01-25 |
US6148394A (en) | 2000-11-14 |
EP0936542A3 (en) | 2000-06-07 |
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