HUE039628T2 - Megközelítõ használatmérések elõállítása osztott gyorsítótáras memória rendszerekhez - Google Patents

Megközelítõ használatmérések elõállítása osztott gyorsítótáras memória rendszerekhez

Info

Publication number
HUE039628T2
HUE039628T2 HUE15797233A HUE15797233A HUE039628T2 HU E039628 T2 HUE039628 T2 HU E039628T2 HU E15797233 A HUE15797233 A HU E15797233A HU E15797233 A HUE15797233 A HU E15797233A HU E039628 T2 HUE039628 T2 HU E039628T2
Authority
HU
Hungary
Prior art keywords
cache memory
shared cache
memory systems
usage measurements
approximate usage
Prior art date
Application number
HUE15797233A
Other languages
English (en)
Inventor
Derek Hower
Cain, Iii
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of HUE039628T2 publication Critical patent/HUE039628T2/hu

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/3471Address tracing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/3003Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3037Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3433Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment for load management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846Cache with multiple tag or data arrays being simultaneously accessible
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848Partitioned cache, e.g. separate instruction and operand caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466Performance evaluation by tracing or monitoring
    • G06F11/348Circuit details, i.e. tracer hardware
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893Caches characterised by their organisation or structure
    • G06F12/0895Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88Monitoring involving counting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/885Monitoring specific for caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1041Resource optimization
    • G06F2212/1044Space efficiency improvement
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21Employing a record carrier using a specific recording technology
    • G06F2212/211Optical disk storage
    • G06F2212/2112Optical disk storage with a removable carrier, e.g. DVD
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28Using a specific disk cache architecture
    • G06F2212/282Partitioned cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31Providing disk cache in a specific location of a storage system
    • G06F2212/314In storage network, e.g. network attached cache
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
HUE15797233A 2014-11-25 2015-11-09 Megközelítõ használatmérések elõállítása osztott gyorsítótáras memória rendszerekhez HUE039628T2 (hu)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201462084469P 2014-11-25 2014-11-25
US14/860,993 US9697126B2 (en) 2014-11-25 2015-09-22 Generating approximate usage measurements for shared cache memory systems

Publications (1)

Publication Number Publication Date
HUE039628T2 true HUE039628T2 (hu) 2019-01-28

Family

ID=56010345

Family Applications (1)

Application Number Title Priority Date Filing Date
HUE15797233A HUE039628T2 (hu) 2014-11-25 2015-11-09 Megközelítõ használatmérések elõállítása osztott gyorsítótáras memória rendszerekhez

Country Status (11)

Country Link
US (1) US9697126B2 (hu)
EP (1) EP3224727B1 (hu)
JP (1) JP6262408B1 (hu)
KR (1) KR101847905B1 (hu)
CN (1) CN107003947B (hu)
AU (1) AU2015354704B2 (hu)
BR (1) BR112017010869A2 (hu)
ES (1) ES2692855T3 (hu)
HU (1) HUE039628T2 (hu)
TW (1) TWI612422B (hu)
WO (1) WO2016085642A1 (hu)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10055158B2 (en) * 2016-09-22 2018-08-21 Qualcomm Incorporated Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems
US10936490B2 (en) * 2017-06-27 2021-03-02 Intel Corporation System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms
US10678690B2 (en) * 2017-08-29 2020-06-09 Qualcomm Incorporated Providing fine-grained quality of service (QoS) control using interpolation for partitioned resources in processor-based systems
US11520700B2 (en) 2018-06-29 2022-12-06 Intel Corporation Techniques to support a holistic view of cache class of service for a processor cache
US11693708B2 (en) * 2019-04-24 2023-07-04 Netflix, Inc. Techniques for increasing the isolation of workloads within a multiprocessor instance

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007156821A (ja) * 2005-12-05 2007-06-21 Fujitsu Ltd キャッシュシステム及び共用2次キャッシュ
US7725657B2 (en) * 2007-03-21 2010-05-25 Intel Corporation Dynamic quality of service (QoS) for a shared cache
US8296522B2 (en) * 2007-12-20 2012-10-23 Intel Corporation Method, apparatus, and system for shared cache usage to different partitions in a socket with sub-socket partitioning
US8244982B2 (en) * 2009-08-21 2012-08-14 Empire Technology Development Llc Allocating processor cores with cache memory associativity
US8667493B2 (en) 2010-05-07 2014-03-04 Advanced Micro Devices, Inc. Memory-controller-parallelism-aware scheduling for multiple memory controllers
US8458399B2 (en) 2010-11-17 2013-06-04 Lsi Corporation Methods and structure for determining cache size in a storage system
WO2012137339A1 (ja) * 2011-04-07 2012-10-11 富士通株式会社 情報処理装置、並列計算機システムおよび演算処理装置の制御方法
US8850122B2 (en) 2011-11-30 2014-09-30 International Business Machines Corporation Cache optimization via predictive cache size modification
US8751746B2 (en) 2011-12-15 2014-06-10 Apple Inc. QoS management in the L2 cache
US10554505B2 (en) 2012-09-28 2020-02-04 Intel Corporation Managing data center resources to achieve a quality of service

Also Published As

Publication number Publication date
KR20170087883A (ko) 2017-07-31
US9697126B2 (en) 2017-07-04
TWI612422B (zh) 2018-01-21
TW201633149A (zh) 2016-09-16
JP6262408B1 (ja) 2018-01-17
BR112017010869A2 (pt) 2018-01-09
AU2015354704B2 (en) 2018-03-29
EP3224727B1 (en) 2018-08-15
CN107003947B (zh) 2018-08-03
ES2692855T3 (es) 2018-12-05
CN107003947A (zh) 2017-08-01
EP3224727A1 (en) 2017-10-04
WO2016085642A1 (en) 2016-06-02
JP2018503891A (ja) 2018-02-08
US20160147655A1 (en) 2016-05-26
AU2015354704A1 (en) 2017-05-04
KR101847905B1 (ko) 2018-04-11

Similar Documents

Publication Publication Date Title
GB2546634B (en) Invalidation data area for cache
SG11201702568QA (en) Holder for objects
GB201718125D0 (en) Object memory management unit
GB2525904B (en) Memory unit
GB2539383B (en) Cache coherency
SG11201606516RA (en) Probe unit
GB2540761B (en) Cache usage estimation
GB2537562B (en) Measurement system
GB2515853B (en) Latency mitigation
SG11202000166QA (en) Probe unit
GB201510596D0 (en) Memory watch unit
GB2546245B (en) Cache memory
GB201603590D0 (en) Memory unit
HUE039628T2 (hu) Megközelítõ használatmérések elõállítása osztott gyorsítótáras memória rendszerekhez
GB2539382B (en) Cache coherency
SG11201702178TA (en) Probe unit
GB2565499B (en) Memory unit
GB2525713B (en) Memory subsystem with wrapped-to-continuous read
EP2979193A4 (en) SHARED MEMORY SYSTEM
SG11201606753YA (en) Measurements device
SG11201803277XA (en) Electroentropic memory device
GB201609703D0 (en) Memory unit
GB201621664D0 (en) Measurement system
GB201404524D0 (en) Advanced result cache refill
GB201603589D0 (en) Memory unit