HU197090B - Signal processing circuit controlled with microprocessor for measuring series train of pulses - Google Patents

Abstract

The invention relates to a microprocessor-controlled circuit arrangement for the measurement of series pulse trains. The essence of the invention is that an input gate circuit (1) is included, whose one input (12) to the output of the central RESET circuit of the microprocessor, the other input (13) connected to the fourth output (22) of a shift register (2) the third input (14) is connected to the output of a multiplexer circuit and whose output (10) is connected to the input (24) of the shift register (2) and the one input (30) of a synchronous circuit (3), the second input ( 23) of the shift register (2) is connected to the output (33) of the synchronous circuit (3), while the first output (25) to the input (46, 56, 66) programmable Zaehlketten (4, 5, 6), the second output (20) with the second input (45) of the programmable counting chain (4), the third output (21) with the second input (55) of the programmable counting chain (5) and the fourth output (22) with the second input (65) the programmable Zaehlkette (6) are connected , further connected to the second input (32) of the synchronous circuit (3) and to the first interrupt controlling input of the microprocessor, connecting one output (33) of the synchronous circuit to the second input (23) of the shift register (2) and another output (31) connected to the input (71) of the simple letter time circuit (7), the output (73) of the simple letter time circuit (7) being connected to the second interrupting input of the microprocessor connected is. Fig. 2

Description

BACKGROUND OF THE INVENTION The present invention relates to a microprocessor-controlled signal processing circuit for measuring a series of pulses, in particular level measurement of a plurality of fuel tanks.

The circuit of the invention essentially implements the data, address and control signals of the sensing unit and the microprocessor.

For larger tank fleets, it may be a problem that tanks need to be repeated several times a day. The source of the difficulties may be:

a) the subjective nature of measurements made with a ruler,

(b) inaccuracy of the measuring tape as a measuring instrument.

c) certification and recording of measured levels,

(d) the transmission of certified level values to any data processing system, ie data preparation (perforated tape, magnetic tape, magnetic disk).

SUMMARY OF THE INVENTION It is an object of the present invention to provide a measuring arrangement for the purpose of eliminating the aforementioned imperfections, which in principle and in design, allows fuel tanks to be: - objective, - accurate, - reproducible at any time, transmission of measurement results.

To achieve this goal, a sensor unit and circuit arrangement were required which could generate an electrical signal proportional to the level of the contents of the container. This electrical signal, once it is accessed by a microprocessor-controlled circuit, enters a processable state, whereby all specific electrical parameters can now be measured with high accuracy. The measurement results can then be generated in digital, numeric form, stored in temporary storage, and converted to encoded form for serial data transmission.

Known solutions that allow continuous level measurement do not produce output signals with electrical parameters that enable microprocessor-controlled multiplexer scanning. In the case of mechanical and functional sensing units, this defect is a direct consequence of their construction, whereas sensors operating on an electrical principle generate an electrical signal proportional to the level to be measured in coded form (eg BCD). The signals available in parallel encoded form require significantly more wiring connections and additional repetitive circuits for any further electronic signal processing, which would make the equipment unnecessarily expensive.

The purpose of the signal processing circuit according to the invention is precisely to receive electrical signals provided by the sensing unit and to output binary information signals to the microprocessor, which performs the appropriate computation and control algorithm.

The sensor unit by which the level is measured is a capacitive transducer whose capacity varies as a function of the level, and the sensor unit generates a time function from the variable cylinder capacity C containing pulses of width proportional to the capacity. Thus, the signal processing circuit of the present invention receives a pulse-width modulated signal, i.e., a serial pulse sequence, as a signaling signal. Λ To further increase the accuracy of the level to be measured, two additional sensors are integrated in the ten sensor units. One is the lower reference sensor, which is designed to eliminate errors in the medium being measured due to the constant change in relative dielectric, and the other is the upper reference sensor, which is a suitable material, e.g. it is used to eliminate errors due to changes in airspace capacity when measuring gasoline levels. These two types of compensation are performed according to the algorithm written in the program of the microprocessor connected to the signal processing circuit according to the invention.

Accordingly, the present invention provides a microprocessor-controlled signal processing circuit for measuring a series of pulses, preferably to measure the level of fuel tanks, with a capacitive sensor unit connected between the sensor unit and the microprocessor controller as an interface unit.

The signal processing circuit of the present invention comprises an input gate circuit having a first input for output of a microprocessor central SLOT circuit, a second input for a fourth output of a phase register, and a third input for a multiplexed circuit generating a serial pulse sequence proportional to the measurement signal. connected to the first input of the phase register and to the first input of a synchronous circuit, the second input of the phase register wipe and step enable is connected to the first output of the synchronous circuit, the first output to a first input of programmable counters, the second output to the second input of the second programmable chain, the fourth output to the second input of the third programmable chain, the second input of the synchronous circuit, and the first microprocessor is connected to the interrupt controller input, the first output of the synchronous circuit is connected to the second input of the phase register, the second output is connected to the first input of a single letter timing circuit, and the first output of the single letter timing circuit is connected to the second interrupt controller input of the microprocessor , as an interface unit connected.

A preferred embodiment of the signal processing circuit according to the invention also comprises a dual-letter timing circuit, the input of which is connected to one of the control output of the microprocessor and the output of which is connected to the third interrupt control input of the microprocessor.

In another preferred embodiment, it comprises a display timing circuit having an input connected to a second control output of the microprocessor, an output connected to a fourth interrupt control input of a microprocessor, an input of a multiplexer control circuit to a third control output of a microprocessor and an input channel to a microprocessor. they are connected to the multiplexer.

The signal processing circuit according to the invention will now be exemplified below. Embodiments thereof are illustrated in more detail in the accompanying drawings. The

Figure 1 illustrates a time function of the input signal of the signal processing circuit of the present invention, i.e., the waveform emitted by a sensor unit;

Figure 2 is a block diagram of a signal processing circuit according to the invention, a

Figure 3 shows a more detailed drawing of the input gate circuit 1, a

Fig. 4 shows an exemplary embodiment of the phase register 2 in more detail

Fig. 5 shows an exemplary embodiment of the synchronous circuit 3, a

FIG. 6 illustrates an embodiment of a programmable account chain 4, 5 or 6, a

Figure 7 shows a variant of the single letter timing circuit 7, a

Fig. 8 shows an exemplary embodiment of a double letter timing circuit 8,

9 illustrates an embodiment of the multiplexer control circuit 10 shown in FIG

10 is a view showing the display timing circuit 9;

Figure 11 is a flow chart of a first interrupt microprocessor, a

Figure 12 is a flow chart of a microprocessor for the second interrupt, a

Figure 13 is a microprocessor flowchart for the third interrupt, a

Figure 14 is a flow chart of a microprocessor for the fourth interrupt.

In order that the signal processing circuit of the present invention will be completely transparent, the system itself will be described.

The microprocessor-controlled signal processing circuit of the present invention thus forms an interface between the data, address and control signals of the sensing unit and a microprocessor controller. The complete level meter provides the user operator with a two-digit display of the tank number to be measured, four digits of the level associated with that tank, u an erroneous reading of sixteen tanks, such as automatic, sequential measurement, manual tank selection, alarm, and the ability to connect the measurement results to a photo printer. To accomplish these tasks, the signal processing circuit of the invention generates interrupt control signals and binary digits proportional to the signal to be measured.

Upon interruption, the microprocessor suspends its basic scanner operation and resumes its interruption according to its algorithm.

Connected to the first input of the microprocessor and the interrupt requesting control unit connected thereto are the fourth outputs 22 of the phase register 2 generating a control signal from the block diagram of the signal processing circuit of the present invention as shown in FIG.

The first interrupt the microprocessor performs the following tasks:

- the contents of the programmable account chains 4, 5, 6 are stored in the RAM memory of the microprocessor. The contents of the first programmable chain 4 are proportional to the incoming time T _CRf , the content of the second programmable chain 5 is proportional to the incoming time, - the content of the third programmable chain 6 is proportional to the incoming (T _CR> + ^ CRn) time, , 27, 28, 29 in D storage, - sets a specific byte (meter-flag setting) in the microprocessor's RAM memory to indicate that correct measurement values have been stored in the microprocessor's temporary storage during the measurement cycle, the microprocessor returns the first interrupt from the subroutine to the main program.

The flowchart is shown in Figure 11.

The second interruption, if correctly measured, contains the measurement results in the binary digits of the microprocessor's RAM. Due to the cylindrical arrangement of the sensor unit, a general calculation of the cylinder capacity C may be used, taking into account the fact that a sensor unit consists of three sensors:

- lower reference sensor, - measuring sensor, - upper reference sensor.

Substituting both geometric and physical constants, the following mathematical relationship is available as a result of the calculations:

Im ·

Ke

Km (Tcr „ ^- Tcr, - Tcrb» ·) ~ L »(T _{CR (} Tcríö)

Trn »Ti

CR «(n · where:

lm: a value proportional to the level,

KR / Kn: geometric constant resulting from the cylindrical arrangement,

'* T'cRn duration proportional to the capacity of the measuring sensor, Tcr « ^: duration proportional to the lower reference capacity, TCR ,: duration proportional to the upper reference capacity, T ^A CRmo ' duration of the measuring sensor in proportion to its initial air capacity, · tcrit the duration, in proportion to the initial airborne capacity of the upper reference, TcRafo * the time, in proportion to the initial airborne capacity of the first reference.

The constants are stored in the microprocessor EPROM.

The second interrupt of the microprocessor is initiated by the first output 73 of the memory 81 of FIG. 7, the single letter timing circuit. The second interrupt is the microprocessor interrupt! flowchart of your routine a

Figure 12.

In the illustration:

E: constant value recorded during the execution of the algorithm,

CY: The abbreviation of Carry, the microprocessor during the difference generation, is a prerequisite for repeated subtraction.

The third interruption of the microprocessor is initiated by the output 83 of the memory 8 of the dual-letter timing circuit 8 of FIG. At the third interrupt, the microprocessor interrupts its routine according to the flowchart (Figure 13).

As shown in the flowchart, this microprogramme performs the measurement phase of the measurement process which gives the user of the equipment an appreciable visual result.

1. Decide whether the 10% or 90% limit values calculated from the tank size have reached or are below the measured value.

2. ALARM or error message is sent when limit values are reached.

3. Converts a numeric value in RAM to a decimal value and places it on its channel location for sending.

4. Evaluates the correct or incorrect value of these decimal values and assigns the initials of the words good or bad and writes those letters into memory ls.

5. The decimal values are sent to the display unit of the device.

6. Writes the electrical initial values for the new tank from the device's ROM to the RAM for calculation purposes.

7. Prepare work records for the new reception.

8. Arrange yourself, return the microprocessor to the third interrupt from routine to main program.

The fourth interruption of the microprocessor is initiated by the output 92 of the circuit storage 97 in FIG. When interrupting, the microcomputer interrupts its routine based on the flow chart as follows (Figure 14).

As you can see from the flowchart, this microprogram does:

- cyclic increment of current tank number, - display of tank and associated level selected by the operator in manual mode, - conversion of code switch set to number 16 to 01 and 01, - microprogram and return it to the main program.

The signal processing circuit according to the present invention thus has the function of receiving the serial pulse series and converting it into a microprocessor processable form.

The time course of the incoming electrical signals is the

Figure 1 shows. Thus, Figure 1 shows the time function of the electrical signals of the detector unit, whereby the time T is the pulse width of the synchronous signal, followed by three time pulses of T / 2 with a capacitance-dependent time delay, where the first T / 2 pulse is time to time, i.e. T _C R ₍ duration proportional to upper reference sensor capacity, T _CK , duration proportional to lower reference sensor capacity, T _CRra duration proportional to _meter sensor capacity. This signal sequence is 1 input of the signal processing circuit of the present invention. connected to the third input 14 of the gate circuit as shown in the block diagram of FIG.

The pulse sequence of FIG. 1 is interpreted as follows. Each signal sequence is introduced by a synchronous pulse of T = 100 ps. The T _CR1 time elapsed from the rising edge of this pulse to the arrival of the first pulse of T / 2 to 50 ps is proportional to the capacity of the upper reference value sensor. T _{CR for} the second pulse. the duration of the lower reference value sensor capacity, while the time to TcRm from this to the third pulse will be proportional to the size of the measuring sensor capacity.

This signal sequence is via the gate circuit 15 of the input gate circuit 1 shown in Fig. 3, which is an ES gate arriving at the first input 24 of the phase register 2, which is a clock input. The circuit arrangement of the phase register 2 is shown in Figure 4. The operation of the phase register 2 requires a high voltage level at the "Clear" (Cl) and "Press" (Pr) inputs of the register circuit. Initially, it is assumed that, by default, a high voltage level is found at the "Q" outputs of the D-memories 26-29 of the phase register 2. In this case, at the same time as the rising edge of the synchronous pulse arriving at the first 24 inputs ( _CK ), the voltage level at the output of the D-storage 26 is low

Changed to Ώ. After the synchronous pulse, the start of the next needle pulse, when the rising edge of the next needle pulse appears, the Q output of the register D 27 switches to a low voltage level. _At time T _CRa , low voltage is output at D output 28 of storage D, and at time Tcm, low voltage is output at output Q D of storage 29. Thus, if the first 24 inputs of the phase register 2 are not the first to receive a synchronous pulse, then the voltage level displayed at the inputs Pr (LOW) prevents its full passage.

The signal at the fourth output 22 provides, in addition to the internal control, a break signal to the microprocessor CPU. As a result of INTERRUPT, the CPU reads, among other things, the phase register hold 2 and provides a disable signal to the first 11 inputs of the input gate circuit 1. As a result of this pulse, as shown in FIG. 3, the storage gate 17 of the input gate circuit 1 shuts off the input of the inverter 18, thereby confirming that the signal sequence has been received completely. Here, a central reset signal to the gate circuit input will reset the container after powering on, and a signal at its Q output will prohibit electrical signals from the inverter 19 to the other gate circuit input.

After the timing of the double letter 8 timing circuit has elapsed, it instructs the microprocessor to send a tilt signal to the first 11 inputs of the input gate circuit 1, thus storing 17 and now allowing signals from the third input 14 through the gate circuit 15 to the phase register 2. access.

2 is a block diagram of the signal processing circuit according to the invention. The input of the block diagram of FIG. 2, to which the signal sequence of FIG. 1 is connected, is formed by the first input 14 of the input gate circuit 1, which is connected via its first inputs 11 and 13 to its microprocessors and second input 12, respectively. it is connected to the fourth output 22 of the phase register 2, while its output is connected to the first input 30 of the synchronous circuit 3. The second input 23 of the phase register 2 is coupled to the first outlet 33 of the synchronous circuit 3 which enables the stepping of the synchronous circuit. The second, third and fourth outputs 20, 21 and 22 of the phase register 2 are connected to the second inputs 45, 55, 65 of the first, second and third programmable counters 4, 5, 6, respectively, of the first, second and third 4.5, 6 programmable count chains are connected to the first 25 outputs of the phase register 2 via gateway first inputs 46, 56, and 66. The first, second and third programmable number chains 4, 5 and 6 are further connected via a channel to the microprocessor's address bus, data bus and control signal bus. The input gate circuit 1 and the phase register 2 are thus connected, as mentioned above, to the synchronous circuit 3 having a second input 32 and a data transmission channel 34 with the microprocessor and a second output 31 connected to the first input 71 of the single letter timing circuit. the inputs 72, 74, the first outputs 73 and the inputs 70 of the 7 single letter timing circuits being connected to the input and output channels of the microprocessor. The 8-letter timer circuit is also coupled to the microprocessor.

Figure 3 is a schematic diagram of an exemplary embodiment of the input gate circuit 1, the third input 14 of the input gate circuit 1 receiving a signal proportional to the measured signal and the input 11 of the input 11 timing circuit. For example, the double letter time is 80 msec. The first input 11 via an inverter 18 is a storage 17, preferably. Connected to the CK input of the D-flip-flop while the storage 17 is further coupled to the output of a gate 16 circuit ₅ , preferably an AND gate, which is connected to the microprocessor reset central output via the second input 12 with the fourth output 22 of the phase register 2

1θ is connected to its 13 inputs. The output of the input gate circuit 1 is formed by the output of the gate circuit 15, preferably the AND gate, connected to the output Q of the storage 17 and to the third input 14 via the inverter 19. This signal is routed to Figure 4.

5 to the first input 24 of the phase register 2 and the first input 30 of the synchronous circuit 3 shown in FIG.

Figure 4 thus shows a block diagram of an exemplary embodiment of the phase register 2. The phase register 2 comprises four D-memories 26, 27, 28, and 29 having the same structure, whose CK inputs together form the first 24 inputs of the phase register 2, mapped to the output of the input gate circuit 1, each additional Pr output2g the second inputs 23 are connected to the first output 33 of the synchronous circuit 3. The phase register 2 is incremented by the measurement signal, the second, third and fourth outputs 20, 21, and 22 are incremented by the signals indicated in FIG. The first 25 outputs of the phase register 2 are coupled to the first, second and third programmable counters 4, 5, 6 of gates 46, 56, 66 connected to the outputs 20, 21 and 22, and the first, second and third programmable gears 4, 5, 6 Active account chains are also connected to the microprocessor. The first, second and third programmable number chains 4, 5, 6 are preferably of the same structure, with an exemplary embodiment shown in Figure 6, where the first programmable number chain 4 is illustrated. The first input 46 of the first programmable number chain 4 is led to the G1 input of a programmable counter 48, while the second input 45 of the control signal is connected via the gate circuit 47, preferably an AND gate, to the input C1 of the mobile program number 48. The other input 57 of the gate circuit 47 is coupled to the microprocessor.

In the exemplary embodiments, it is mentioned that a microprocessor of the type INTEL 8085 was used as a microprocessor. For example, each store may be integrated circuits of type 7474, while programmable count circuits may be of type 8283.

Fig. 5 shows an exemplary embodiment of synchronous circuit 3, wherein the first input 30 connected to the input gate circuit 1 is led to the inputs 35 of a programmable circuit 35, a gate 37 and an inverter 38, data channel 34 is connected to the microprocessor and 35 is connected to the input of the clock signal, its second input 32 is also connected to the microprocessor and connected to the CK input of a storage clock 49. The output 01 of the programmable circuit 35 through the inverter 36 and the gate circuit 37 forms the synchronous circuit 3

A second output 31 of the -510, which is even coupled to the Cl input of the storage 49. Data 34 is transmitted. a full channel is also connected via the gate circuit 40 to the Cl input of the D storage tanks 41, 42 and 43. The other input of the gate circuit 40 is coupled to the output Q of a D storage 41. The data transmission channel 34 is further provided to the input of an additional gate circuit 44, which is connected to the other output of the gate circuit 44, the output 0 of the storage tank D and the output of the gate circuit 44 being the first output 33 of the synchronous circuit.

Figure 7 shows a more detailed diagram of a single letter timing circuit 7. The single letter time is preferably 40 msec. The single letter timing circuit 7 receives its control signal from its first input 71 from the synchronous circuit 3, and its other inputs and outputs, i.e. inputs 70, 72, 74 and first output 73, are coupled to the microprocessor. The first input 71 is coupled to the CK input of a storage clock 75, and the input Cl of this storage 75 is connected via a gate circuit 76 to an input 72 and a programmable counter 77 and inverters 78 and 79 to an input 70. The output of inverter 78 is connected to the CK input of an additional storage clock 81 and the Cl input of this storage 81 is also coupled to the inputs 72 and 74. The output of the memory 81 is the first output 73 of the single letter timing circuit 7.

Fig. 8 shows an exemplary embodiment of a dual letter timing circuit 8, where both inputs and outputs are coupled to a microprocessor. The inputs 84 on the programmable accounts 89 and 90 are connected via inverter 91 to the CK inputs of two storage clocks 87 and 88, while the common terminals G of the programmable accounts 89 and 90 are connected to the storage terminals U and D. The other input 85 of the double-letter timing circuit 8 is connected directly to the Cl input of the storage 87 and is connected via the gate 86 to the Cl input of the other storage 88.

Fig. 9 shows a control circuit of the multiplexer 10, which is used to ensure that a signal of a specific measuring channel is transmitted to the input gate circuit 1. Its input is the input channel 102 as a data bus which is connected to a storage 107 and is coupled to the microprocessor. The input 101 of the storage controller 107 is also connected to the microprocessor, while its output is formed by inverters comprising open collector transistors T1, T2, T3 and T4, where the outputs 103-106 are connected to the sensor multiplexer.

Figure 10 shows an exemplary embodiment of the display timing circuit 9. The inputs 94, 95, 93 are connected to the microprocessor, while the outputs 92 also control the display unit via the microprocessor. The inputs 94 and 93 are connected to the CK input 97 of the gate 98, while the input 94 is connected to the 0 input of the storage 96. The output Q of the storage 96 is connected to the terminals G of the programmable count chains 99 and 100.

The operation of the circuit arrangement according to the invention is as follows:

The input from the sensor unit is directed to the first input 14 of the input gate circuit 1. In the event that the microprocessor monitoring 8-part alphabet timing circuit has also issued an enabling command to the first 11 inputs, the

The electrical signals of FIG. 1 are transmitted to both the synchronous circuit 3 and the phase register 2. The function of the synchronous circuit 3 is to find the pulse of duration T within the two-part letter time and to allow the phase register 2 to advance from the beginning of this pulse. Each step of the phase register 2 controls the first, second and third programmable number chains 4, 5 and 6, and contains binary information that is ultimately proportional to the level of the medium to be measured. These are read by the microprocessor, perform arithmetic operations, encode, store and display them as previously described. The 7 single letter timing circuit monitors whether each specific measurement signal has been received within that time period. If so, it instructs the microprocessor to perform arithmetic etc. to perform an operation, if not, it proceeds to a channel, i.e., examines the electrical signals of the sensor units of another container. Of course, in such a case, one of the functions of the microprocessor is to output specific information about the faulty channel.

The function of the 8-part time timing circuit is, inter alia, to instruct the microprocessor, through which the input gate circuit 1 receives electrical signals from the new channel, thereby checking the charge status of another container. The function of the 9 display timing circuit is to control the timing of the display unit associated with the microprocessor. The display duration of a tank's charge status depends on the programmed duration of these 9 display timing circuits. The multiplexer control circuit 10 receives a step command and, for a period of twice the letter period, passes electrical signals from the sensor circuit of a particular channel (container) to the input of the input gate circuit 1.

Figure 4 illustrates the phase 2 register. The function of this circuit is to control the programmable account chains 4, 5, 6 also shown in FIG. The output control signal 25 is provided to the common gateway first inputs 46, 56, 66 of the programmable counters 4, 5, 6, while the outputs 20, 21, 22 provide gating of the clock signals of the three independent programmable counters 4, 5, 6. Thus, the signal of the second output 20, as shown in FIG. 1, at the time, ^, the signal of the third output 21, the signal of the fourth output 22, after the time után ^, + Τθ ^, 6 programmable accounts. A common wipe for input 23 is e.g. it arrives at the phase register 2 if the phase register 2 has not started the step according to a synchronous pulse T, but according to one of the T / 2 periods.

Figure 5 is a detail of the synchronous circuit 3 shown in Figure 2. The quartz clock signal entering the data transmission channel which is the input to the circuit only starts to move the programmable numerical circuit 35 if the signal at its input 30 is high voltage. Otherwise, the programmable number of chain promotion stops and follows up _five construction of a high voltage start again put in the input stage. The pulse killed at the output of the inverter will only pass through the gate circuit 37 if the ₁ θ input signal of the first input 30 at the other input of the gate circuit 37 is still high. The timing of the programmable count chain 35 is determined such that the time period T in FIG. 1 expires by 2/3, so that there is a needle pulse within this time period T. This retraining pulse duration T 1 ₅ 37 yield the gate circuit disables the gate circuit 39 through the storage device 49, which further wrong signals perceived synchronous pulse no longer get through. In case of incorrect synchronization, the gate circuit 39 is open and the gate circuit 43, 42, 41 20 is open

D containers are written. The output of the D-storage 41 opens the gate circuit 44 and, on the next half signal, the signal of the first output 33 resets the phase register 2 to be started. The half-system clock at the output of the gate circuit 40 sets the sys- tems 41, 42,43 to a _2- s clock.

6, the first, second and third 4,

5, 6 programmable account chains have the same structure, so that the functional description is valid for all three circuits. The system clock 30 at input 57 will move the programmable count chain 48 only if the control signal at the second inputs 45 and first 46 is of high voltage. Input 57, as shown in Figure 4, will be high when the electrical signal of the incoming sensor starts, and second input 45, as shown in Figure 4, will be low voltage when the time of the CRF of Figure 1 begins. Thus, in the programmable number chain 48 of FIG. 6, a binary signal proportional ^to T _{CR (} duration proportional) is provided. This microprocessor associated with the circuit arrangement of the present invention can read out the read signal at the fourth output 22 of FIG. and process it according to the appropriate algorithm

The circuit shown in FIG. 7 is a detailed representation of the single letter timer circuit 7 of FIG. 2. The function of the 7 single letter timing circuitry is to, inter alia, start its timing on the basis of a synchronous pulse from the detector and reset it after a set time of 50 specified letters. During this period, all three measuring pulses of T / 2 duration should arrive from the correctly functioning sensing units in addition to the synchronous pulse of duration T. This 55-letter timeout is checked by the microprocessor after the timer expires and sends an error message to the display unit in case of malfunction. The input 72 receives a central GAP control signal and resets the storage 75 and 81. When the control signal of the first input according to g0 in FIG. 5 arrives, indicating the presence of a synchronous pulse, the memory 75 is provided, which provides an enabling signal to the programmable account chain 77. This programmable account chain 77 counts according to the clock rate of the system arriving at the input 70. Once the programmed numeric value has been reached, the output signal of the programmable circuit 77 is reset by the inverters 78, 79 and the gate circuit 76 to reset the function of the programmable account 77. At the same time, the memory 81 is written in, and the first output 73 sends a control signal to the microprocessor. After performing the tasks of the microprocessor, reset the memory 81 with the control signal sent to the 74 inputs

The function of the 8-alpha timing circuit is, among other things, the channel stepping and detailing shown in Figure 8. By default, the stores 87 and 88, by virtue of the central GAP control signal received at the input 85, are in a position to disable the programmable counters 89, 90. The timing is started by the microprocessor with a control signal applied to the 82 inputs. Λ Container 87 tumbles to disable the blocking of the programmable count chains 89 and 90 by the signal displayed at output D. Depending on the timing of the clock input to the 84 inputs, both programmable count chains 89 and 90 count on the basis of a pre-programmed numerical value. At the end of the double letter time, preferably 80 msec, the 0 output of the programmable numerical chain 90 sends a feedback signal to the stores 87 and 88 via the 91 converters. The signal at the output 83 of the storage 88 is directed to the microprocessor and notifies the timer, which then performs its decision functions according to its fired microprogram and, at the end, re-starts the timing with the control signal sent to the input 82.

The timing of display 9 can be considered to be identical to that of FIG. 8 with respect to circuit design and operation, shown in FIG. 10. The difference is in the microgram of the microprocessor associated with the circuit arrangement of the present invention. The circuit timing in this case is much larger, approx. 4 sec like

2 for the 8-part letter timing circuit of FIG. The function of the display timing circuit 9 is, inter alia, to control the timing of the display unit connected to the microprocessor. Therefore, the level value for one container can be read on the display unit for less than a second, although the measurement itself only lasts for a fraction of that time.

The control circuit of the multiplexer 10 is shown in detail in FIG. The function of the multiplexer control circuit 10 is to input control signals of a particular channel into the input gate circuit 1 through a double letter time. Since the sensing units of each container are of the same construction, which container is the particular one is decided by the multiplexer control circuit 10, which receives a control command from the microprocessor via the control signal to the input channel 101 on the input channel 102. This control command is stored by the stores 107 until a new command is received. To the multiplexer of the sensor unit, inverters with open collector transistors T1, T2, T3, T4 with outputs 103, 104, 105, 106 are fed to the control signal.

Claims (2)

; Claims A microprocessor-controlled signal processing circuit for measuring a series of pulses, preferably for measuring the level of fuel tanks, with a capacitive sensor unit connected between the sensor unit and the microprocessor controller as an interface unit comprising a first input gate circuit (1) 11) the output of the microprocessor's central SLOT circuit, the second input (12) is connected to the fourth output (22) of a phase register (2), and the third input (14) is connected to the output of a multiplexer circuit generating a serial pulse series connected to the first input (24) of the phase register (2) and the first input (30) of a synchronous circuit (3), the second input (23) of the phase register (2) wiper and step enable (33). ), while the first output (25) is programmable for a first input (46, 56, 66) of a number chain (4, 5, 6), a second output (20) for a second input (45) of a first programmable number chain (4), a third output (21) for a second programmable number ( 5) connected to a second input (55), a fourth output (22) connected to a second input (65) of a third programmable chain (6), a second input (32) of a synchronous circuit (3) and a first interrupt control input of the microprocessor; a first output (33) of a synchronous circuit (30) connected to a second input (23), a second kx thread (31) of the phase register (2) connected to a first input (71) of a single letter timing circuit (7), a single letter timing circuit the first output (7) (73) is connected to the second input of the microprocessor ₁ megszakftásvezérlő fifth The microprocessor-controlled signal processing circuit of claim 1, further comprising a dual-letter timing circuit (8) having an input (82) with a control output of the micro20 processor and a first input (11) of the input gate circuit (1). ), while its output (83) is connected to the third input of the microprocessor third interrupt controller.