SU1062677A1 - Device for interrogating information channels - Google Patents

Abstract

A device for interrogating information channels containing two switches, a comparison circuit, a frame counter, a control counter, an analysis block, perHCTj commands, a scan counter, a first memory block, two decoders, an adder, an error trigger, an operation register, and the clock input of the device is connected to the clock inputs of the command register, scan counter and one-generation register, the frame counter input is connected to the scan counter installation input, the scan counter output is connected to the command register information input, The first, second and third inputs of the analysis unit are connected respectively to the outputs of the frame counter, the operational register and the first decoder, and the outputs respectively to the control inputs of the command register and the operational register, whose information input is connected to the output of the adder, the first and second inputs of the adder are connected with the outputs of the first decoder and the operational register, the control input of the first switch is connected to the control input of the second switch, the output of the command register is connected to info The first input of the first switch, whose outputs are connected to the input of the second decoder and the first information input of the comparison circuit, the output of the second decoder is connected to the installation input of the control counter, the counting input of which is connected to the input of the frame counter, and the output to the second information input of the comparison circuit, the first input setting the device mode is connected to the control input of the comparison circuit, the output of which is connected to the input of the installation of the error trigger, the synchronization input of which is connected to the input of the counter frame, bus logical O and logical H device and the output of the first memory block are connected respectively to the information inputs of the second switch, the output of which (L is connected to the input of the first decoder, the outputs of the command register and the error trigger are connected to the output of the koi, polling manda and signal output errors of forming the polling command. It is distinguished by the fact that, in order to expand the field of application of the device, a second memory block, four registers and storage, three switches, two frequency dividers, a time counter program menus, write trigger, I element, single pulse generator and start trigger, with the output of the second memory block connected to the information inputs of the storage registers and the program time counter, the first and second information inputs of the third switch are connected respectively to the address input. the control program of the device and the output of the first storage register, and the output to the input of the second memory block. These first and second information inputs of the fourth switch are connected respectively to the outputs of the second storage register and the information code of the device, and

Description

the output is connected to the control input of the first frequency divider, the output of which is connected to the output of the scan counter installation, the first, second and third inputs of the fifth switch are connected respectively to the outputs of the scan counter, the third storage register and the address of the program address of the device interrogation, and mode feature output - respectively to the input of the first memory block and the control input of the second switch; the output of the fourth storage register is connected to the control input of the second frequency divider; orogo connected to the counting input time Amma programmable counter in the first set input

one

trigger write connected to

The output of the program's time counter and the first input of the installation into the start trigger, the second input of the installation to the output of the single pulse generator and the input of the installation to the start trigger, and the output to the resolution enable input of the time counter of the program and the first input of the I element whose output is connected to the setup input to the recording trigger, the recording entry of the time counter, the program and the control inputs of the storage registers, the synchronization input, and the second installation input to the startup trigger O are connected respectively to the output of the sign the end of the operation of the first storage register and the input signal of the device stop, and the output is connected to the enable input of the first frequency divider, the first enable input of the second frequency divider and the control input of the third switch, the device clock input is connected to the second input of the And element, clock inputs of the frequency dividers and the driver a single pulse whose start input is connected to the device start input, the second input of the device mode setting is connected to the second input, enabling the second frequency divider and the control input of the fourth and fifth co1 switches.

The invention relates to computing technology and is intended for use in information-measuring systems (IMS), in particular, in devices for program interrogation of information channels with automatic selection of the order of interrogation,

{a device for polling information channels containing a frame counter connected in series, an analysis unit and a command register, as well as a scan counter whose outputs are connected to other inputs of the command register and the memory device, and the inputs to the first clock bus, respectively. clock bus and the input of the frame counter, the decoder, the adder and the operational register, with the outputs of the memory device through the decoder connected to the inputs of the adder and the second inputs of the analysis unit, the third inputs. It is connected to the inputs of the operational register and to other INPUTS of the adder, while its outputs are centralized with the first ones in the code of the operational register, the second input of which is connected to another input of the analysis unit, and the third input to the first clock bus and clock input of the register of commands.

during operation of the device, for each state of the frame positions, sequential reading of the polling frequency codes of the channels from the memory device and determining, based on the sequence of these codes, a polling command which is the channel number polled at this position of the frame l.

The disadvantages of the known device are the limited possibilities of monitoring the health, since it does not provide for testing the basic elements in the process of dynamic functioning and also low reliability due to the need to restore information in the storage device after any random failure which leads to loss of time and under experimental conditions is invalid.

In addition, a disadvantage is the limitation of the possibility of using the device in an IMS intended for testing technical objects of increased complexity in various modes of operation.  In this case, every time when the test mode changes, it becomes necessary to quickly redistribute the polling frequencies of IIS channels and change its informativity, for which the operator needs to write a new polling program in the memory, change the clock frequency of the frame counter, co. appropriate informativeness and start the device.  This leads to the loss of significant time, which is unacceptable under the experimental conditions, and also reduces the usability of the device and the IMS as a whole.  The closest in technical essence and the achieved result to the invention is with a device for polling information channels, containing a frame counter, an anashiz block, a command register, a scan counter, a memory block, a decoder, an adder, an operational register, and the scan input of the device is connected to the scan inputs command register counter scan and operation register; device frame input is connected to frame frame and scan counter inputs; scan counter outputs — to command register and storage block inputs; first, second and third: the group of analysis block inputs are connected to the frame counter, decoder and the operational register, and the outputs to the control inputs of the command register and the operational register, the inputs of which are connected to the outputs of the adder, and the first and second groups of inputs of the adder are connected respectively with the outputs of the decoder and the operational register, as well as the first and second switches, additional decoder, control counter, comparison circuit and error trigger, the first input of setting the device mode connected to the control input of the first and second switches, the outputs of the command register are connected to the and reverse order respectively to the first and second groups of inputs of the first switch, the outputs of which are connected to the inputs of the additional decoder and the first group of inputs of the circuit, the output of the additional If the inflator is connected to the installation input of the control counter, the second input of which is connected to the frame input of the device, and the outputs to the second group of inputs of the comparison circuit, the second input of the device mode setting is connected to the control input of the comparison circuit whose output is connected to the input of the error trigger setup the second input of which is connected to the input of the device frame, the inputs of the logic and logic device and the output of the storage unit are connected respectively to the first and second groups of inputs of the second switch, the outputs of which are connected enes with inputs of the decoder, the outputs of the instruction register, and the error flip-flop are connected to the device outputs.  During the operation of the known device, for each state of the frame positions the sequential reading of the channel polling frequency from the memory block of the channels and determining, based on their sequence, the channel number polled at the given frame position 2, is performed. .  A disadvantage of the known device is also the limitation of the possibility of its use in the IMS designed for testing technical problems. Objects of increased complexity in various operating modes, arising due to the need for real-time redistribution of polling frequencies between measuring channels, and changes in the information content of the IMS according to the experimental procedure, which requires recording a new polling program in the memory block, changing the clock frequency of the frame counter that corresponds to information IIS and restarting the device.  These preparatory operations require a considerable amount of time, which, in the conditions of the experiment, especially with complex regulations, is unacceptable.  In addition, these operations are carried out directly by the operator serving the IMS, which increases the likelihood of an error during their execution, reduces the usability of the device and, therefore, the IMS as a whole.  The aim of the invention is to expand the scope and increase the convenience of operation by automating the execution of device control operations in accordance with the rules of the experiment.  The goal is achieved in that a device containing two switches, a comparison circuit, a frame counter, a control counter, an analysis unit, a command register, a scan counter, the first memory block, two decoders, an adder, an error trigger, an operational register, and a clock input the device is connected to the clock inputs of the command register, scan counter and operation register, the input of the counter ka, zr is connected to the input of the installation of the scan counter, the output of the scan counter is connected to the information input of the register lp, first, second and third inputs of the analysis unit respectively connected to outputs of the frame counter operatsionnogr first register and decoder, avyhody - respectively to the control inputs of the commands and the operating register. register, whose information input is connected to the output of the adder, the first and second inputs of the adder are connected respectively to the outputs of the first decoder and the operational register, the control input of the first switch is connected to the control input of the second switch, the output of the command register is connected to the information input of the first switch the outputs of which are connected to the input of the second decoder and the first information input of the comparison circuit, the output of the second decoder is connected to the input of the installation of the control counter The count input of which is connected to the input of the frame counter, and the output of the second information1; ion input of the comparison circuit; the first input of the device mode setting is connected to the control input of the comparison circuit whose output is connected to the trigger setup input. errors, the synchronization input is connected to the input of the frame counter.  and logical bus logical ISI i1 device and the output of the first memory block are connected respectively to the information inputs of the second switch, the output of which is connected to the input of the first decoder, goes out of the command register and the error trigger is connected to the output of the device polling command output, A second memory block, four storage registers, three switches, two frequency dividers, a program time counter, a recording trigger, an AND element, a single pulse shaper, and a trigger trigger are entered ska, wherein the output of the second memory block coupled to inputs informadionnymi storage registers and counter time programs, we first and second information inputs of the third switch is connected | us respectively to the input of the first control gschresa ustroyst program. VA and the output of the first storage register, and the output - to the input of the second memory unit, the first and second information inputs of the fourth switch are connected respectively to the outputs of the second storage register and the information code of the device, and the output to the control input of the first frequency division, the output of which is connected to the installation input of the scan counter, first, second. and the Third inputs of the nth switch are connected respectively to the outputs of the scan counter, the third storage register and the address of the device interrogation program, and the information output and the output of the mode indicator correspond to the input of the first memory block and the control input of the second switch, the output of the fourth register storage is connected to the control input of the second frequency divider, the output of which is connected to the counting input of the program's time counter, the first input of the installation in 1 recording trigger is connected to the output of the time counter program and the first input of installation. About the start trigger, the second input of the set to 1 is to the output of the single pulse generator and the input of the set to 1 of the start trigger, and the output to the input of the counting of the program time counter and the first input of the And element, the output of which is connected to the input of the set. About the recording trigger, the recording entry of the program time counter and the control inputs of the storage registers, the synchronization input and the second input of the trigger trigger input IIQII are connected respectively to the output of the first storage register and the stop signal input of the device, and the output is connected to the enable input of the first divider frequency, the first input of the resolution of the second frequency divider and the control V. the third switch, the clock input of the device is connected to the second input of the element I, the clock inputs of the frequency dividers and a single pulse shaper, the start input of which is connected to the start input of the device, the second input of the device mode setting is connected to the second enable input of the second frequency divider and the fourth control inputs and n of that switches.  FIG.  1 shows an block diagram of the device; in fig.  2 - functional block diagram analysis.  The device contains (FIG. 1) a frame counter 1, an analysis block 2, a command register 3, a scan counter 4, a first memory block 5, a first decoder 6, an adder.  7, operational register 8, device input 9, first 10 and second 11 switches, second decoder 12, control counter 13, comparison circuit 14, error trigger 15, second device mode setting input 16, output 17 of the device polling command, error signal output 18 forming a polling command, the second memory block 19, the first 20, second 21, fourth 22 and third 23 storage registers, third 24, fourth 25 and fifth 26 switches, second 27 and first 28 frequency dividers, program time counter 29, trigger 30 records, element 31, shaper 32 single pulse g trigger trigger 33, input 34 of the address of the first control program of the device, input 35 of the informativity code of the device, input 36 of the address of the device polling program, input 37 of the device stop signal, input 38 of the start of the device, second input 39 of the task device mode, information inputs 40 and 41 of the second and first memory blocks 19 and 5.  The analysis unit 2 (FIG. 2) contains a decoder 42 ,.  performed on elements OR 43, adder 44, element AND 45, the second and first outputs 46 and 47, the first input 48 of the analysis unit receives the inverse code of the frame 1 counter, the second input 49 receives the code of the operational register 8, the third input 50 receives the code decoder 6.  The device works as follows. During operation, the device receives clock pulses from input 9, the frequency of which should be M times the maximum informativeness of the IMS (N is the number of IMS measurement channels). Before the experiment, in block 5, the information input 41 is recorded interrogation programs of measuring channels, each of which contains a set of interrogation frequency codes ordered by channel numbers.  The position of the polling program in the block structure is determined by the program address. In block 19, information program 40 records device control programs, each program is a binary word in the format of which contains the address of the polling program with the indication of the polling mode - cyclical or program, informativity code IIS, code.  the operating time of the control program code, time scale and address of the next control program with a sign of the end of the work.  The position of the control program in the structure of block 19 is determined by the address of the program.  The number of polling programs, their content and, therefore, the number and content of control programs are determined by the regulations of a particular experiment.  The main mode of operation of the device is the polling mode with automatic control - it is set in the absence of potential signals Logi I I I I I at the inputs 16 and 39 comb of the device mode.  Before the start of the experiment, the trigger 33 is in the zero state, the logical 0 signal from its output blocks the operation of frequency dividers 27 and 28 and allows the address of the first control program from input 34 to pass through switch 24 to the input of block 19, while at its output The binary word of the first control program, the bits of which are grouped, according to the format, arrive at the information inputs of all the storage registers and counter 29, the positive edge of the signal from input 38 starts the driver 32 and at its output appears the start pulse, which coincides in phase and duration with an alternate clock pulse from input 9, sets the trigger edge 30 to the positive edge of the trigger pulse, the Logic signal, from its output blocks the counting input of the counter 29 and permits the passage of the next clock pulse from input 9 through element 31, At the output of the latter, a write pulse coinciding in phase with the start pulse appears, which, arriving at the control inputs of registers 20-23 and the record input of counter 29, records in registers 20-23 and counters to the 29 data on their information inputs.  At. this in registers 20, 21, 23 and 22 and in counter 29 are recorded respectively the address of the next control program with the sign of the end of work, the information code of IIS, the address of the polling program with the sign of the polling mode, the time scale code and the time code of the specified program.  The negative edge of the write pulse is also reset to the zero state tr. igger 30, the logical O signal, which appears at its output, enables the counter 29 to work at the counting input and prohibits the formation of a write pulse on the And 31 element. Simultaneously with resetting the trigger 30 to the zero state of the negative edge of the trigger from the driver 32 The trigger 33 is set to one and the Logic i signal from its output resolves the operation of the divider 28 even in the absence of the control potential signal Logic i at the input 39 of the frequency divider 27.  In addition, the signal from the trigger 33 switches to another switching direction, the switch 24, as a result of which the output of the register 20 storing the address of the next control program is connected to the input of block 19, and the binary word of the control program appears at the output of the latter which is the next transition.  The frequency divider 28 divides the clock frequency from the input 9 of the device, and the division factor is set to its control input by the switch 25, the output of which, in the absence of a signal at input 33, receives the IIS information code from the output of register 21.  At the output of the divider 28, a sequence of clock pulses is formed whose frequency is equal to the specified information of the IMS.    Counter 4 is set to its original state by the next clock pulse from the output of divider 2B and counts clock pulses from input 9, Accepting the duration of the pulse sequence from the healer 28 output in one position of the pulse sequence 28, sequentially, the values of all channel numbers.  The address of block 5 is formed on the switch 26f, and in the mode in question, as the low-order bits of the address, the state of the switch 26 passes the counter status code 4, and the high-order address is the address of the interrogation program from the register 23 output.  In addition to the output of the switch 26 passes the additional bit of the sign of the polling mode, in the case of equality to which the program polling mode is set to zero, otherwise cyclical.  Thus, during the program interrogation, for each state of counter 4, from block 5, the next channel interrogation frequency code assigned to it in the interrogation program whose address is contained in the selected control program is retrieved.  The device generates a sequence of commands for polling IIS information channels (a polling command is the channel number in binary code).  The frequency of occurrence of polling commands at the output of the device (the frequency of the sequence) is equal to the clock frequency of the measuring system or its information content.  In a software survey, the frequency of the polling team following any. The second channel in the sequence is specified in the program.  Frequency is set as a percentage of the information content of IIS using the formula.  3s (1) where i is the channel polling frequency; tig - information content (system clock frequency); h - takes the value O, 1,2, 3,,. .  ,, determines the long information content allocated to this channel in binary code, is recorded in the program.  Thus, the polling program is a list of values of P, ordered by channel numbers.  The maximum value determines the minimum frequency that can be assigned to a channel, t. e.  the maximum period of his survey.  During this period, iaa, all other channels are polled at least once.  The length of a ko / mand sequence of one maximum period is called a frame.  The time interval during which the next polling command is set at the device output is called the frame position.  This interval is equal to.  period of the system clock frequency.  The device at each position of the frame determines the number of the polled channel.  At the next position of the frame using scan counter 4, channel numbers are sequentially iterated, which correspond to the cell numbers of block 5.  For each state of the counter 4 of block 5, the code of the frequency of the next channel is also unmounted.  The code is decrypted by the decoder 6 and added on the adder 7 with the code contained in the operational register B.  The result of the addition is fed to the information input of the latter.  At the same time in block 2 produced-.  It compares the result of the addition from the previous operation with the state of counter 1.  Moreover, so many bits are compared, which is the value of the frequency code, the rest do not affect the result of the comparison.  If the state of the counter is 1 (t. e.  the number of the next position) is more than the result of the addition, then the last one from the resolution from block 2 is written to the operational register 8, otherwise the record is not made and when the next frequency code arrives, the operation cycle is reversed.  In case of equality, block 2 generates a signal to enable the recording of the channel number from counter 4 to register 3 and the lowest operations at this frame position are terminated. Example.  Let the range of possible frequencies interrogation „„ is equal to 3.  Then the maximum polling period. (frame length) is equal to eight periods of the system clock frequency, and the frame has eight positions.  Let the poll program is given in tab.  one.

T a b l and c. but

Value in

Channel binary code

001 010 011 011

In the initial state, the operational register 8 contains the code 111, the counter 1 Ks1dra - the code 000 (the least significant bit is on the left).

At the zero position of the frame, the following operations are performed.

The operational register code 8 (111) is added to the adder 7 with the positional code (001) of the zero channel (Table 1), which forms the decoder 6

111 4

100

1.011.

In block 2, the result of the summation is compared with the position number. Since half of the information content (Item 1) is given to the zero channel, then at. The comparison only takes into account the low-order bit of counter 1, the switching frequency of which is also equal to half of the information content, and the low-order bit of the result of adding O 11 - the result of adding O 00 is the position number

no discharge accepted

in attention --- comparable bits.

000 001 010

Frame position number

Channel number The considered cycle of phase-cutting operations performed by the device at the next frame position to determine the channel number of the op-ed channel is similar to the cycle performed by a known device. The frequency delisher 27 divides the clock frequency from the gate 9, and the time scale code from the register 22 output is assigned to the control factor of its control input. At the output of the split 27, a sequence is formed. Thus, in block 2, the comparison operation is implemented as follows (FIG. 2).

The adder 44 through the decoder 42 on the input 49 enters the code contained in the operating sieve 8, and on the input 48 - the inverse frame position number. The decoder 42 is controlled by the position code of the frequency from the decoder b, and set the bits to compare

codes that are not taken into account. After the addition, the presence or absence of a carry from the older bit of the adder 44 will show which

of the compared codes more. The presence in all categories of units means-. It is noted that the codes are equal and the And 45 transmits a control signal to register 3, and for the zero channel

the result of the addition from adder 7 is written to operational register 8 regardless of the result of the comparison.

For the example in question

we have

01 1 - the result of the addition

1 - inverse position number

- result on adder 44

- discharges not taken into account.

Thus, at position 000, a zero channel polling command is generated.

Similarly, codd polling commands are generated at all other frame positions. For the considered example, we obtain the distribution of frame channels (Table 2), corresponding to the given in Table. one.

table 2

100

110 111

101

000

.i ... i total time pulses with a period, which, depending on the value of the time scale code, can take on values from tenths of a second to hundreds of seconds. The scaling of the time pulse period makes it possible to more flexibly program the change of the interrogation programs and the information content of the IIS in relation to the rules of a particular experiment. With the arrival at the counting input of the counter 29 of the first time pulse, the output of the divider 27 starts counting the operating time of the first control program and, consequently, counting the operating time of the device with the informativeness of my programs and polling mode specified in it. In the initial state, the time code for the first control program is stored in the counter 29, the meter operates in the subtraction mode, and as soon as its state becomes zero, which corresponds to the end of the first control program time, a negative pulse is formed at its output. On the first input of the installation, a trigger 30 is set to one state. At the output of element And 31, a second write pulse appears, which records in the storage registers and the counter 2.9 of the new control program. After the end of the recording, the negative edge of the pulse again resets the trigger 30, starts the new time count, and the address of the next control program from register 20 will ensure its selection from block 19, etc. until the next control program, the value of the sign of the end of the work will not be equal to one. The unit value of this bit, which indicates that the experiment nporpaivMa has been exhausted, permits operation on the first input of the setup in trigger 33, and on expiration of the control program time the negative front of the next pulse, co. the counter 29, the trigger 33 is reset to Oi; the device returns to its original state in which it was before the start of the experiment. If necessary, the experiment time limit can be interrupted at any time by applying a single signal to the device input 37, which by the second input of the installation in O flips the trigger 33. The device can operate in the mode, during the manual polling, which. It is used if the experimental procedure is not very diverse and complex. This mode is set by applying a potential signal to the device input 39, thus blocking the frequency divider 27 and switching to the other switching direction switches 25 and 26, resulting in a frequency divider 28, memory 5 and control inputs coming to the control input. the switch inputs 10 and 11, respectively, of the IIS information code from the device input 35, the address of the polling program, and the sign of the polling mode from the device input 36. The informativity code and the address of the program at the specified inputs are set by the operator. With manual control, the device can also be set to cyclically polling by applying a Logic i signal at input 36, corresponding to the attribute of the polling mode. If in addition to this. at the input 16 of the device, to give a Logic signal, the operational test control mode is set. The operation of the device in the cyclic polling modes with manual control and on-line test control is similar to the operation of the known device in the corresponding modes. In all the considered modes, the device is started by applying a Logic i signal to input 38, and a stop by applying the same signal to the device input 37. Thus, the proposed device, as compared with the known one, has an expanded scope of application due to the possibility of its being used as part of an IMS intended for testing technical objects of increased complexity. This possibility is provided as a result of automation of information change control and ASCI interrogation programs in the course of the experiment in order to quickly redistribute the interrogation frequencies between the measurement channels, which eliminates the need for preparatory operations when changing the test mode, eliminates the unacceptable loss of time associated with them and, moreover, the likelihood of error is reduced and the ease of use of the device is increased by excluding the operator from the control process . The advantage of the device is also the ability to flexibly program the control process in relation to the regulations of a particular experiment, which is supported by the setting of the time scale of the control program, its operating time, and also any sequence of transition from one control program to another.

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Claims (1)

DEVICE FOR INTERVIEWING INFORMATION CHANNELS, comprising two switches, a comparison circuit, a frame counter, a control counter, an analysis unit, a command register, a scan counter, a first memory unit, two decoders, an adder, an error trigger, an operational register, and the device’s clock input is connected to clock inputs of the command register, scan counter and one-way register, the input of the frame counter is connected to the input of the scan counter setting, the output of the scan counter is connected to the information input of the command register, first the second, third and third inputs of the analysis unit are connected respectively to the outputs of the frame counter, operational register and the first decoder, and the outputs, respectively, to the control inputs of the command register and operational register, the information input of which is connected to the output of the adder, the first and second inputs of the adder are connected respectively to the outputs of the first decoder and the operational register, the control input of the first switch is connected to the control input of the second switch, the output of the command register is connected to the information the input of the first switch, the outputs of which are connected to the input of the second decoder and the first information input of the comparison circuit, the output of the second decoder is connected to the input of the control counter, the counting input of which is connected to the input of the frame counter, and the output to the second information input of the comparison circuit, the first input setting the device mode is connected to the control input of the comparison circuit, the output of which is connected to the input of the installation of the error trigger, the synchronization input of which is connected to the input of the frame counter, the bus log of the other ¹ '0''andlogical' ¹ 1 '' devices and the output of the first memory block are connected, respectively _, to the information inputs sg of the second switch, the output of which is connected to the input of the first decoder, the outputs of the command register and the error trigger are connected to the output of the polling command and the output of an error signal generating a polling command ^. characterized in that, in order to expand the scope of the device, a second memory block, four storage registers, three switches, two frequency dividers, a program time counter, a trigger for ISI, element And, a single pulse shaper and a trigger, and the output of the second memory block is connected to the information inputs of the storage registers and the program time counter, the first and second information inputs of the third switch are connected respectively to the address input of the device’s first control program and the output of the first storage register , and the output is to the input of the second block of memory. The first and second information inputs of the fourth switch are connected respectively to the outputs of the second storage register and the input of the device information code, and the output is connected to the control input of the first frequency divider, the output of which is connected to the scan counter installation input, the first, second, and third the inputs of the fifth switch are connected respectively 'to the outputs of the scan counter, the third storage register and the input of the address of the device polling program.,' and the information output and the output of the mode indicator respectively to the input of the first memory block and the control input of the second switch, the output of the fourth storage register is connected to the control input of the second frequency divider, the output of which is connected to the counting input of the program time counter, the first installation input in the recording trigger is connected to the output of the program time counter and the first installation input at '' 0 '' of the start trigger, the second input of the installation at '' 1 '' - to the output of the single pulse shaper and the input of the installation to 'Ί''of the start trigger, and the output - to the input of the resolution of the counter of the program time counter Amma and the first input of the And element, the output of which is connected to the installation input in the `` О <sup>1</sup> '' recording trigger, the recording input of the program time counter and the control inputs of the storage registers, the synchronization input and the second installation input in the `` 0 '' trigger trigger are connected respectively, with the output of the sign of the end of the first storage register and the input of the stop signal of the device, and the output is connected to the enable input of the first frequency divider, the first enable input of the second frequency divider and the control input of the third switch, the first input device is connected to a second input of the AND gate, clock inputs ^ frequency dividers and a single pulse generator, the start input of which is connected to the triggering input device, the second input mode assignment device is connected to the second input. resolutions for the frequency of both the fourth and tori. the second share the control input of the fifth commuta-