HU195600B - Method and circuit arrangement for eliminating deterministic phase noise derived from the principle of operation of the digital direct frequency-synthezer - Google Patents

Abstract

The present invention relates to a method for eliminating the deterministic phase noise of a digital direct-frequency synthesizer, in which the output of a synthesized digital network is delayed by a controlled delay circuit to each of the periods so that its period-determining sections follow each other at equal intervals of the nominal frequency to be generated. The present invention further relates to a switching arrangement for eliminating a direct digital frequency synthesizer based on the principle of deterministic phase noise, where a synthesis digital network / 1 / signal output / 3 / controlled delay circuit / 2 / signal input / 6 /, controlled control circuit / 2 / controller input / 4 / is connected to the synthesis digital network III delay control output / 5 /. Controlled Delay Circuit / 2 / One Controller Input / 15 / to Adapter Circuit / 9 / to / 10 / Output / 13 to Data Input / 12 /, to other control input / 16 / to Adapter Circuit / 9 / Frequency Adjuster to Data Input / 7 / is on. (Figure 2) 2-hour -1-

Description

The present invention relates to a process by which the deterministic phase noise due to the principle of operation of a digital direct frequency synthesizer can be reduced to such an extent that it is practically completely eliminated. g

Digital Direct Frequency Synthesizers, despite their many benefits / quick operation, ease of manufacture, integration, low cost /, are still not widespread. This is mainly due to the fact that in more demanding applications the spectral purity of the signal they provide is unsatisfactory and contains a significant amount of phase noise.

The prior art attempts to slightly improve the quality of the output signal by using a follow-up PLL. This method does not actually result in it sacrificing the advantages of digital direct synthesis above and yet it cannot eliminate the low frequency components of phase noise.

It is an object of the present invention, while fully preserving the benefits of digital direct synthesis, to reduce phase noise across all components to such an extent that the spectral purity of the output signal provided can meet all practical needs.

The present invention is based on the discovery that the phase noise of the synthesizer output signal is predominantly deterministic, the result of phase modulation that is clearly still contained in the synthesis process, i.e., the information obtained from the synthesizer can be eliminated by appropriately selected processing.

The invention consists in that the synthesizer output signal is delayed by every period of measure- ^J in that the sections defining the time period proper sequencing of the target nominal frequency value equal intervals.

Its simple implementation is made possible by selecting a specific state code from a state code recorded by a digital network performing gg synthesis, which is known for the amount of delay required in a given period given the frequency value to be generated.

According to the method of the invention and in the switching arrangement for execution, the signal from the signal output of a synthesized digital network is delayed by a controlled delay circuit, the amount of delay in the digital code from each period of the period of the synthesis digital network connected to the controller input set as needed. The frequency to be generated is determined by the code connected to the input of the digital network performing the synthesis. The phase-noise-free output signal is output from the output of the controlled delay circuit. gg

BRIEF DESCRIPTION OF THE DRAWINGS The method and circuit arrangement of the present invention will now be described with reference to the drawings.

Figure 1 illustrates the essence of the method and circuit arrangement of the invention.

Figure 2 illustrates a possible embodiment of a method and circuit arrangement according to the invention.

Figure 3 illustrates a solution for a controlled delay circuit.

In Figure 1, the signal output 3 of a digital network performing synthesis 1 is coupled to signal input 6 of a controlled delay circuit 2. The control input 4 of the controlled delay circuit 2 is connected to the delay control output 5 of the digital network 1 performing the synthesis.

In Fig. 2, the digital network performing synthesis 1 is constructed from a digital adder circuit 9 and a connected digital storage circuit 10.

Fig. 3 illustrates an embodiment of the controlled delay circuit 2, wherein the controlled delay circuit 2 is connected to a control comparator input 24, 23 via a D / A converter 22 via a control input 15, 16. A capacitor 21, bridged by a switching device 19 controlled from the signal output 3 of the digital network 1, is connected to one of the inputs 23 simultaneously.

In the following, the present invention will be described in detail, following one embodiment.

The codes appearing on the sum output 11 of the digital adder 9 are cyclically fed back to the data input 12 of the digital adder 9 via the digital store 10. This can be easily accomplished by constructing the digital storage circuit 10 from type D tilt circuits, each of whose outputs 13 is incremented by the number of its inputs 14 for each clock cycle by the number of inputs 14 of it. A digital code corresponding to the frequency to be generated is coupled to the data input 7. The transmission output 26 of the digital addition circuit 9 forms the signal output 3 of the digital network performing the synthesis. In each case, a signal transition occurs when the sum of the numbers at the inputs of the digital adder circuit 9 is greater than that represented by the sum of all outputs. For example, assuming a m-bit addition and also a m-bit storage, the transmission output 26 generates a signal transition whenever

A + B 2 ^m state is created.

/ A and B represent the numerical values of the codes assigned to the data inputs of the digital addition circuit 9.

Frequency of signal transitions

B f - f ₀ . - where

2 ^m f: frequency produced f ₀ : frequency of the clock controlling the storage

B: numeric value of the code connected to the data input 7 of the digital adder circuit 9.

This frequency is an average value over a long period of time, since the transmissions follow each other at equal intervals. In order to achieve the same intervals, the signal transitions are delayed by a corresponding δ t in each period.

The amount of delay required;

kBfrac 2 ^m nm

B .int 2 where frac int

2 ^m

B

2 '

The fractional fraction of B is the fractional fraction of the quotient

T _o

K is a natural integer

O <K <· int frac

2 ^m varies from period to period.

-2Α Δ π delay time information is therefore a function of the code of the frequency value to be generated / B / and the number “K” for a given digital network and given clock frequency.

The value of the number B is directly available on the data input 7 of the digital adder circuit 9, and the K value can be obtained from the output 13 of the digital adder 10 connected to the data input 12 of the digital adder 9 Figure 3 illustrates an embodiment of 2 controlled delay circuits.

In this way, both digital codes are converted to an analog signal using a D / A converter 17 and 18, respectively. An analog signal proportional to the numerical value B is charged to a capacitor 21 whose voltage is applied to an input 23 of an analog comparator 22. The start of the charge is determined by the signal transduction at the transmission output 26 of the digital addition circuit 9, which eliminates the short-circuiting of the capacitor 21, which is symbolized by a controlled switching device 19. The other input 24 of the analog comparator 22 is connected to an analog signal proportional to the number k, and its output 20 now has transitions of signals which are successively spaced.

Claims (5)

1. / A method for eliminating a deterministic phase noise of a digital direct frequency synthesizer operating in the process of synthesizing a quasi-periodic signal having an average periodic value defined by a digital code using a clock-controlled digital network, characterized in that the synthesized digital network is. the synthesized output signal is delayed by a controlled delay circuit in each period such that its period determining sections follow each other at equal intervals corresponding to the nominal frequency to be generated. 2. The method of claim 1, wherein the amount of delay is derived from a digital code that sets the nominal frequency and a digital code of a specific state selected from the states of the digital network performing the synthesis. Method according to claim 1 or 2, characterized in that both digital codes are converted to an analog signal and compared by means of an analog comparator, 4. / Circuit arrangement for eliminating the deterministic phase noise of a direct digital frequency synthesizer operating principle in which the signal output of a digital network synthesized by an addition and storage circuit is connected to a signal input of a controlled delay circuit, characterized in that the input of the controlled delay circuit. / some of which are one of the control inputs / 15 / to the input circuitry / 9 / to the output circuit of the storage circuit / 10/13 / to the connected input / 12 / and the other control input / 16 / to the frequency setting data input of the adding circuit / 6 / / 7 / is on. The circuit arrangement according to claim 4, characterized in that the controlled delay circuit / 2 / control input / 15, 16 / D / A converters / 17. 18 /, the outputs of the latter being connected to an analog comparator / 22 / to an input / 23, 24 /, of which one input / 23 / from a digital network / 1 / signal output / 3 / via a controlled switching device / 19 / bypassed capacitor / 21 / is on.