HK66095A - Cache subsystem for microprocessor based computer with asynchronous and synchronous datapath - Google Patents
Cache subsystem for microprocessor based computer with asynchronous and synchronous datapathInfo
- Publication number
- HK66095A HK66095A HK66095A HK66095A HK66095A HK 66095 A HK66095 A HK 66095A HK 66095 A HK66095 A HK 66095A HK 66095 A HK66095 A HK 66095A HK 66095 A HK66095 A HK 66095A
- Authority
- HK
- Hong Kong
- Prior art keywords
- asynchronous
- based computer
- microprocessor based
- cache subsystem
- datapath
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
- G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/608—Details relating to cache mapping
- G06F2212/6082—Way prediction in set-associative cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/710,079 US5293603A (en) | 1991-06-04 | 1991-06-04 | Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path |
PCT/US1992/004744 WO1992022035A1 (en) | 1991-06-04 | 1992-06-04 | Cache subsystem for microprocessor based computer with asynchronous and synchronous data path |
Publications (1)
Publication Number | Publication Date |
---|---|
HK66095A true HK66095A (en) | 1995-05-12 |
Family
ID=24852543
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK66095A HK66095A (en) | 1991-06-04 | 1995-05-04 | Cache subsystem for microprocessor based computer with asynchronous and synchronous datapath |
Country Status (6)
Country | Link |
---|---|
US (1) | US5293603A (xx) |
JP (1) | JPH06508457A (xx) |
DE (2) | DE4291778T1 (xx) |
GB (1) | GB2272313B (xx) |
HK (1) | HK66095A (xx) |
WO (1) | WO1992022035A1 (xx) |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6446164B1 (en) * | 1991-06-27 | 2002-09-03 | Integrated Device Technology, Inc. | Test mode accessing of an internal cache memory |
US5414827A (en) * | 1991-12-19 | 1995-05-09 | Opti, Inc. | Automatic cache flush |
JP3517417B2 (ja) * | 1992-01-28 | 2004-04-12 | 株式会社日立製作所 | データ転送装置 |
JP3920931B2 (ja) * | 1992-04-17 | 2007-05-30 | サン・マイクロシステムズ・インコーポレイテッド | キャッシュされたデータを読出しおよび書込む方法ならびにデータをキャッシングする装置 |
US5463753A (en) * | 1992-10-02 | 1995-10-31 | Compaq Computer Corp. | Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller |
US5668971A (en) * | 1992-12-01 | 1997-09-16 | Compaq Computer Corporation | Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer |
US5590307A (en) * | 1993-01-05 | 1996-12-31 | Sgs-Thomson Microelectronics, Inc. | Dual-port data cache memory |
US6311286B1 (en) * | 1993-04-30 | 2001-10-30 | Nec Corporation | Symmetric multiprocessing system with unified environment and distributed system functions |
US5526512A (en) * | 1993-09-20 | 1996-06-11 | International Business Machines Corporation | Dynamic management of snoop granularity for a coherent asynchronous DMA cache |
US6276844B1 (en) * | 1993-12-06 | 2001-08-21 | International Business Machines Corporation | Clustered, buffered simms and assemblies thereof |
US5761476A (en) * | 1993-12-30 | 1998-06-02 | Intel Corporation | Non-clocked early read for back-to-back scheduling of instructions |
JP3490131B2 (ja) * | 1994-01-21 | 2004-01-26 | 株式会社ルネサステクノロジ | データ転送制御方法、データプロセッサ及びデータ処理システム |
US5577200A (en) * | 1994-02-28 | 1996-11-19 | Intel Corporation | Method and apparatus for loading and storing misaligned data on an out-of-order execution computer system |
US5603007A (en) * | 1994-03-14 | 1997-02-11 | Apple Computer, Inc. | Methods and apparatus for controlling back-to-back burst reads in a cache system |
US5826052A (en) * | 1994-04-29 | 1998-10-20 | Advanced Micro Devices, Inc. | Method and apparatus for concurrent access to multiple physical caches |
US5905997A (en) * | 1994-04-29 | 1999-05-18 | Amd Inc. | Set-associative cache memory utilizing a single bank of physical memory |
US5692152A (en) * | 1994-06-29 | 1997-11-25 | Exponential Technology, Inc. | Master-slave cache system with de-coupled data and tag pipelines and loop-back |
JPH0830546A (ja) * | 1994-07-20 | 1996-02-02 | Nec Niigata Ltd | バス制御装置 |
US5634073A (en) * | 1994-10-14 | 1997-05-27 | Compaq Computer Corporation | System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation |
US5640532A (en) * | 1994-10-14 | 1997-06-17 | Compaq Computer Corporation | Microprocessor cache memory way prediction based on the way of previous memory read |
US5835948A (en) * | 1994-10-14 | 1998-11-10 | Compaq Computer Corporation | Single bank, multiple way cache memory |
US5553265A (en) * | 1994-10-21 | 1996-09-03 | International Business Machines Corporation | Methods and system for merging data during cache checking and write-back cycles for memory reads and writes |
TW358907B (en) * | 1994-11-22 | 1999-05-21 | Monolithic System Tech Inc | A computer system and a method of using a DRAM array as a next level cache memory |
EP0793827B1 (en) * | 1994-11-22 | 2002-03-06 | Monolithic System Technology, Inc. | Method and structure for utilizing a dram array as second level cache memory |
US5893921A (en) * | 1995-02-10 | 1999-04-13 | International Business Machines Corporation | Method for maintaining memory coherency in a computer system having a cache utilizing snoop address injection during a read transaction by a dual memory bus controller |
CN1077700C (zh) * | 1995-02-17 | 2002-01-09 | 曼特亚克公司 | 可编程调控交插存取存储器管理系统 |
US5802586A (en) * | 1995-02-27 | 1998-09-01 | Motorola, Inc. | Cache memory having a read-modify-write operation and simultaneous burst read and write operations and a method therefor |
JPH08314794A (ja) * | 1995-02-28 | 1996-11-29 | Matsushita Electric Ind Co Ltd | 安定記憶装置へのアクセス待ち時間を短縮するための方法およびシステム |
WO1996029653A1 (en) * | 1995-03-17 | 1996-09-26 | Intel Corporation | Multi-processing cache coherency protocol on a local bus |
US5617347A (en) * | 1995-03-17 | 1997-04-01 | Fujitsu Limited | Cache memory system and method thereof for storing a staged memory item and a cache tag within a single cache array structure |
US5737550A (en) * | 1995-03-28 | 1998-04-07 | Advanced Micro Devices, Inc. | Cache memory to processor bus interface and method thereof |
US5704058A (en) * | 1995-04-21 | 1997-12-30 | Derrick; John E. | Cache bus snoop protocol for optimized multiprocessor computer system |
US6128700A (en) * | 1995-05-17 | 2000-10-03 | Monolithic System Technology, Inc. | System utilizing a DRAM array as a next level cache memory and method for operating same |
US5983025A (en) * | 1995-06-07 | 1999-11-09 | International Business Machines Corporation | Computer system buffers for providing concurrency and avoid deadlock conditions between CPU accesses, local bus accesses, and memory accesses |
US5652859A (en) * | 1995-08-17 | 1997-07-29 | Institute For The Development Of Emerging Architectures, L.L.C. | Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues |
US5802560A (en) * | 1995-08-30 | 1998-09-01 | Ramton International Corporation | Multibus cached memory system |
US5692165A (en) * | 1995-09-12 | 1997-11-25 | Micron Electronics Inc. | Memory controller with low skew control signal |
US5768550A (en) * | 1995-11-21 | 1998-06-16 | International Business Machines Corporation | Bus interface logic system |
US5758188A (en) * | 1995-11-21 | 1998-05-26 | Quantum Corporation | Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal |
US5963721A (en) * | 1995-12-29 | 1999-10-05 | Texas Instruments Incorporated | Microprocessor system with capability for asynchronous bus transactions |
JPH09231130A (ja) * | 1996-02-26 | 1997-09-05 | Mitsubishi Electric Corp | マイクロコンピュータ |
US5765196A (en) * | 1996-02-27 | 1998-06-09 | Sun Microsystems, Inc. | System and method for servicing copyback requests in a multiprocessor system with a shared memory |
US5916311A (en) * | 1996-03-27 | 1999-06-29 | Matsushita Electric Industrial Co., Ltd. | Bus controller and information processing device providing reduced idle cycle time during synchronization |
US5960453A (en) | 1996-06-13 | 1999-09-28 | Micron Technology, Inc. | Word selection logic to implement an 80 or 96-bit cache SRAM |
US6049847A (en) * | 1996-09-16 | 2000-04-11 | Corollary, Inc. | System and method for maintaining memory coherency in a computer system having multiple system buses |
US5897656A (en) | 1996-09-16 | 1999-04-27 | Corollary, Inc. | System and method for maintaining memory coherency in a computer system having multiple system buses |
US5898895A (en) * | 1996-10-10 | 1999-04-27 | Unisys Corporation | System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing |
US5924121A (en) * | 1996-12-23 | 1999-07-13 | International Business Machines Corporation | Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles |
US5862154A (en) * | 1997-01-03 | 1999-01-19 | Micron Technology, Inc. | Variable bit width cache memory architecture |
US5872913A (en) * | 1997-03-07 | 1999-02-16 | International Business Machines Corporation | System and method for low overhead, high precision performance measurements using state transistions |
US5909694A (en) * | 1997-06-12 | 1999-06-01 | International Business Machines Corporation | Multiway associative external microprocessor cache |
US6073190A (en) | 1997-07-18 | 2000-06-06 | Micron Electronics, Inc. | System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair |
US6243769B1 (en) | 1997-07-18 | 2001-06-05 | Micron Technology, Inc. | Dynamic buffer allocation for a computer system |
US6081876A (en) * | 1997-09-22 | 2000-06-27 | Hewlett-Packard Company | Memory error containment in network cache environment via restricted access |
US6289419B1 (en) * | 1998-03-06 | 2001-09-11 | Sharp Kabushiki Kaisha | Consistency control device merging updated memory blocks |
KR100285956B1 (ko) | 1998-06-30 | 2001-04-16 | 윤종용 | 고속직렬버스에연결된동기식및비동기식장치의제어시스템과제어방법 |
US6198666B1 (en) | 2000-02-29 | 2001-03-06 | International Business Machines Corporation | Control input timing-independent dynamic multiplexer circuit |
US6477622B1 (en) * | 2000-09-26 | 2002-11-05 | Sun Microsystems, Inc. | Simplified writeback handling |
US9710384B2 (en) * | 2008-01-04 | 2017-07-18 | Micron Technology, Inc. | Microprocessor architecture having alternative memory access paths |
CN101290564B (zh) * | 2008-05-26 | 2010-07-28 | 华为技术有限公司 | 数据传输方法、系统及cpu接口控制器 |
CN101340595B (zh) * | 2008-07-21 | 2011-09-21 | 华为技术有限公司 | 一种图像数据回读的方法和装置 |
US8782348B2 (en) * | 2008-09-09 | 2014-07-15 | Via Technologies, Inc. | Microprocessor cache line evict array |
US10521118B2 (en) * | 2016-07-13 | 2019-12-31 | Sandisk Technologies Llc | Methods, systems, and computer readable media for write classification and aggregation using host memory buffer (HMB) |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3972023A (en) * | 1974-12-30 | 1976-07-27 | International Business Machines Corporation | I/O data transfer control system |
US4075686A (en) * | 1976-12-30 | 1978-02-21 | Honeywell Information Systems Inc. | Input/output cache system including bypass capability |
US4342084A (en) * | 1980-08-11 | 1982-07-27 | International Business Machines Corporation | Main storage validation means |
US4467411A (en) * | 1981-03-06 | 1984-08-21 | International Business Machines Corporation | Scheduling device operations in a buffered peripheral subsystem |
US4442487A (en) * | 1981-12-31 | 1984-04-10 | International Business Machines Corporation | Three level memory hierarchy using write and share flags |
US4575792A (en) * | 1982-03-31 | 1986-03-11 | Honeywell Information Systems Inc. | Shared interface apparatus for testing the memory sections of a cache unit |
US4564899A (en) * | 1982-09-28 | 1986-01-14 | Elxsi | I/O Channel bus |
US4724518A (en) * | 1983-07-29 | 1988-02-09 | Hewlett-Packard Company | Odd/even storage in cache memory |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5157776A (en) * | 1987-12-30 | 1992-10-20 | Zenith Data Systems Corporation | High speed memory for microcomputer systems |
US4888679A (en) * | 1988-01-11 | 1989-12-19 | Digital Equipment Corporation | Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements |
US5025366A (en) * | 1988-01-20 | 1991-06-18 | Advanced Micro Devices, Inc. | Organization of an integrated cache unit for flexible usage in cache system design |
US4905188A (en) * | 1988-02-22 | 1990-02-27 | International Business Machines Corporation | Functional cache memory chip architecture for improved cache access |
US5125084A (en) * | 1988-05-26 | 1992-06-23 | Ibm Corporation | Control of pipelined operation in a microcomputer system employing dynamic bus sizing with 80386 processor and 82385 cache controller |
US5003465A (en) * | 1988-06-27 | 1991-03-26 | International Business Machines Corp. | Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device |
US5058006A (en) * | 1988-06-27 | 1991-10-15 | Digital Equipment Corporation | Method and apparatus for filtering invalidate requests |
US5097409A (en) * | 1988-06-30 | 1992-03-17 | Wang Laboratories, Inc. | Multi-processor system with cache memories |
EP0375864A3 (en) * | 1988-12-29 | 1991-03-20 | International Business Machines Corporation | Cache bypass |
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
EP0398523A3 (en) * | 1989-05-19 | 1991-08-21 | Hitachi, Ltd. | A device for data i/o and execution support in digital processors |
US5155843A (en) * | 1990-06-29 | 1992-10-13 | Digital Equipment Corporation | Error transition mode for multi-processor system |
-
1991
- 1991-06-04 US US07/710,079 patent/US5293603A/en not_active Expired - Lifetime
-
1992
- 1992-06-04 JP JP5500668A patent/JPH06508457A/ja active Pending
- 1992-06-04 WO PCT/US1992/004744 patent/WO1992022035A1/en active Application Filing
- 1992-06-04 DE DE4291778T patent/DE4291778T1/de active Pending
- 1992-06-04 DE DE4291778A patent/DE4291778B4/de not_active Expired - Fee Related
- 1992-06-04 GB GB9321174A patent/GB2272313B/en not_active Expired - Fee Related
-
1995
- 1995-05-04 HK HK66095A patent/HK66095A/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US5293603A (en) | 1994-03-08 |
GB9321174D0 (en) | 1994-03-16 |
GB2272313A (en) | 1994-05-11 |
DE4291778B4 (de) | 2005-02-10 |
DE4291778T1 (de) | 1995-07-20 |
JPH06508457A (ja) | 1994-09-22 |
WO1992022035A1 (en) | 1992-12-10 |
GB2272313B (en) | 1994-11-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PF | Patent in force | ||
PC | Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee) |
Effective date: 20100604 |