HK44892A - Semiconductor integrated circuits gettered with phosphorus - Google Patents

Semiconductor integrated circuits gettered with phosphorus

Info

Publication number
HK44892A
HK44892A HK448/92A HK44892A HK44892A HK 44892 A HK44892 A HK 44892A HK 448/92 A HK448/92 A HK 448/92A HK 44892 A HK44892 A HK 44892A HK 44892 A HK44892 A HK 44892A
Authority
HK
Hong Kong
Prior art keywords
gettered
phosphorus
integrated circuits
semiconductor integrated
semiconductor
Prior art date
Application number
HK448/92A
Other languages
English (en)
Inventor
John Vincent Dalton
Kenneth Jeffrey Orlowsky
Ashok Kumar Sinha
Original Assignee
American Telephone & Telegraph
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone & Telegraph filed Critical American Telephone & Telegraph
Publication of HK44892A publication Critical patent/HK44892A/xx

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/06Gettering
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/061Gettering-armorphous layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
HK448/92A 1984-08-21 1992-06-18 Semiconductor integrated circuits gettered with phosphorus HK44892A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/642,932 US4589928A (en) 1984-08-21 1984-08-21 Method of making semiconductor integrated circuits having backside gettered with phosphorus
PCT/US1985/001512 WO1986001638A1 (en) 1984-08-21 1985-08-06 Semiconductor integrated circuits gettered with phosphorus

Publications (1)

Publication Number Publication Date
HK44892A true HK44892A (en) 1992-06-26

Family

ID=24578648

Family Applications (1)

Application Number Title Priority Date Filing Date
HK448/92A HK44892A (en) 1984-08-21 1992-06-18 Semiconductor integrated circuits gettered with phosphorus

Country Status (9)

Country Link
US (1) US4589928A (de)
EP (1) EP0192668B1 (de)
JP (1) JPS61503064A (de)
KR (1) KR930010983B1 (de)
CA (1) CA1226073A (de)
DE (1) DE3581285D1 (de)
HK (1) HK44892A (de)
SG (1) SG83591G (de)
WO (1) WO1986001638A1 (de)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0229180B1 (de) * 1985-06-17 1992-01-22 Sony Corporation Herstellungsverfahren für halbleiteranordnungen
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
US4732865A (en) * 1986-10-03 1988-03-22 Tektronix, Inc. Self-aligned internal mobile ion getter for multi-layer metallization on integrated circuits
US4795722A (en) * 1987-02-05 1989-01-03 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4966865A (en) * 1987-02-05 1990-10-30 Texas Instruments Incorporated Method for planarization of a semiconductor device prior to metallization
US4753709A (en) * 1987-02-05 1988-06-28 Texas Instuments Incorporated Method for etching contact vias in a semiconductor device
JPH0793354B2 (ja) * 1988-11-28 1995-10-09 株式会社東芝 半導体装置の製造方法
US5244819A (en) * 1991-10-22 1993-09-14 Honeywell Inc. Method to getter contamination in semiconductor devices
US5223734A (en) * 1991-12-18 1993-06-29 Micron Technology, Inc. Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion
US5229305A (en) * 1992-02-03 1993-07-20 Motorola, Inc. Method for making intrinsic gettering sites in bonded substrates
US5543335A (en) * 1993-05-05 1996-08-06 Ixys Corporation Advanced power device process for low drop
US5559052A (en) * 1994-12-29 1996-09-24 Lucent Technologies Inc. Integrated circuit fabrication with interlevel dielectric
JP3355851B2 (ja) * 1995-03-07 2002-12-09 株式会社デンソー 絶縁ゲート型電界効果トランジスタ及びその製造方法
JP3412332B2 (ja) * 1995-04-26 2003-06-03 株式会社デンソー 半導体装置
US5573633A (en) * 1995-11-14 1996-11-12 International Business Machines Corporation Method of chemically mechanically polishing an electronic component
US6090707A (en) 1999-09-02 2000-07-18 Micron Technology, Inc. Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials
US6958264B1 (en) * 2001-04-03 2005-10-25 Advanced Micro Devices, Inc. Scribe lane for gettering of contaminants on SOI wafers and gettering method
US7142577B2 (en) * 2001-05-16 2006-11-28 Micron Technology, Inc. Method of forming mirrors by surface transformation of empty spaces in solid state materials and structures thereon
US6898362B2 (en) * 2002-01-17 2005-05-24 Micron Technology Inc. Three-dimensional photonic crystal waveguide structure and method
US7132348B2 (en) * 2002-03-25 2006-11-07 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US6987037B2 (en) * 2003-05-07 2006-01-17 Micron Technology, Inc. Strained Si/SiGe structures by ion implantation
US7273788B2 (en) * 2003-05-21 2007-09-25 Micron Technology, Inc. Ultra-thin semiconductors bonded on glass substrates
US7662701B2 (en) 2003-05-21 2010-02-16 Micron Technology, Inc. Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers
US7008854B2 (en) * 2003-05-21 2006-03-07 Micron Technology, Inc. Silicon oxycarbide substrates for bonded silicon on insulator
US7501329B2 (en) * 2003-05-21 2009-03-10 Micron Technology, Inc. Wafer gettering using relaxed silicon germanium epitaxial proximity layers
US6929984B2 (en) * 2003-07-21 2005-08-16 Micron Technology Inc. Gettering using voids formed by surface transformation
US7439158B2 (en) 2003-07-21 2008-10-21 Micron Technology, Inc. Strained semiconductor by full wafer bonding
US7153753B2 (en) * 2003-08-05 2006-12-26 Micron Technology, Inc. Strained Si/SiGe/SOI islands and processes of making same
JP4134199B2 (ja) * 2006-05-25 2008-08-13 エルピーダメモリ株式会社 半導体装置の製造方法
TWI355046B (en) * 2007-07-10 2011-12-21 Nanya Technology Corp Two bit memory structure and method of making the
US8541305B2 (en) * 2010-05-24 2013-09-24 Institute of Microelectronics, Chinese Academy of Sciences 3D integrated circuit and method of manufacturing the same
US9425153B2 (en) 2013-04-04 2016-08-23 Monolith Semiconductor Inc. Semiconductor devices comprising getter layers and methods of making and using the same
US8994118B2 (en) * 2013-04-04 2015-03-31 Monolith Semiconductor, Inc. Semiconductor devices comprising getter layers and methods of making and using the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3740835A (en) * 1970-08-31 1973-06-26 Fairchild Camera Instr Co Method of forming semiconductor device contacts
NL7100275A (de) * 1971-01-08 1972-07-11
US3997368A (en) * 1975-06-24 1976-12-14 Bell Telephone Laboratories, Incorporated Elimination of stacking faults in silicon devices: a gettering process
US4018626A (en) * 1975-09-10 1977-04-19 International Business Machines Corporation Impact sound stressing for semiconductor devices
FR2340619A1 (fr) * 1976-02-04 1977-09-02 Radiotechnique Compelec Perfectionnement au procede de fabrication de dispositifs semiconducteurs et dispositifs ainsi obtenus
US4053335A (en) * 1976-04-02 1977-10-11 International Business Machines Corporation Method of gettering using backside polycrystalline silicon
US4151631A (en) * 1976-09-22 1979-05-01 National Semiconductor Corporation Method of manufacturing Si gate MOS integrated circuit
US4114256A (en) * 1977-06-24 1978-09-19 Bell Telephone Laboratories, Incorporated Reliable metal-to-junction contacts in large-scale-integrated devices
US4131487A (en) * 1977-10-26 1978-12-26 Western Electric Company, Inc. Gettering semiconductor wafers with a high energy laser beam
DE2829983A1 (de) * 1978-07-07 1980-01-24 Siemens Ag Verfahren zum gettern von halbleiterbauelementen und integrierten halbleiterschaltkreisen
US4291322A (en) * 1979-07-30 1981-09-22 Bell Telephone Laboratories, Incorporated Structure for shallow junction MOS circuits
JPS5674939A (en) * 1979-11-22 1981-06-20 Toshiba Corp Preparation method of semiconductor integrated circuit
JPS5766673A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of mos type semiconductor device
US4463491A (en) * 1982-04-23 1984-08-07 Gte Laboratories Incorporated Method of fabricating a monolithic integrated circuit structure
US4470852A (en) * 1982-09-03 1984-09-11 Ncr Corporation Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions

Also Published As

Publication number Publication date
EP0192668A1 (de) 1986-09-03
JPH0528899B2 (de) 1993-04-27
JPS61503064A (ja) 1986-12-25
KR930010983B1 (ko) 1993-11-18
US4589928A (en) 1986-05-20
WO1986001638A1 (en) 1986-03-13
CA1226073A (en) 1987-08-25
KR880700461A (ko) 1988-03-15
SG83591G (en) 1991-11-22
DE3581285D1 (de) 1991-02-14
EP0192668B1 (de) 1991-01-09

Similar Documents

Publication Publication Date Title
SG83591G (en) Semiconductor integrated circuits gettered with phosphorus
GB8503310D0 (en) Semiconductor integrated circuit
HK85295A (en) Semiconductor integrated circuit device
GB8507524D0 (en) Semiconductor integrated circuit device
GB8421200D0 (en) Semiconductor integrated circuit
GB8720041D0 (en) Semiconductor integrated circuit device
EP0190027A3 (en) Semiconductor integrated circuit
GB8619512D0 (en) Semiconductor integrated circuit
EP0181059A3 (en) Semiconductor integrated circuit for clock distribution
GB8432458D0 (en) Integrated circuits
GB8506105D0 (en) Semiconductor integrated circuit device
EP0255362A3 (en) Semiconductor integrated circuit
EP0192456A3 (en) Semiconductor integrated circuit
HK50995A (en) Semiconductor integrated circuit
EP0176226A3 (en) Semiconductor circuit
GB8403698D0 (en) Semiconductor device fabrication
GB8412275D0 (en) Manufacturing semiconductor devices
EP0178133A3 (en) Semiconductor integrated circuit device
JPS57207358A (en) Circuit with semiconductor integrated circuit
DE3474485D1 (en) Semiconductor integrated circuit with gate-array arrangement
EP0293808A3 (en) Semiconductor integrated circuit
GB8431534D0 (en) Semiconductor integrated circuit
GB8813042D0 (en) Semiconductor integrated circuit
GB8527128D0 (en) Semiconductor logic circuits
EP0158222A3 (en) Semiconductor integrated circuit having multiple-layered connection