HK40112912A - Protection loop for power amplifier - Google Patents

Description

Protection loop for power amplifier

Priority application

This application relates to U.S. Provisional Patent Application No. 63/379,516, filed October 14, 2022, entitled “Protection Loop for Power Amplifier,” the contents of which are incorporated herein by reference in their entirety.

This application relates to U.S. Provisional Patent Application No. 63/354,292, filed June 22, 2022, entitled “5G POWER AMPLIFIER USING FAST ENGAGE AND RECOVERY DISTRIBUTED DIRECT-BASE SIGNAL LIMITING AND OVP PROTECTION LOOP,” the contents of which are incorporated herein by reference in their entirety.

background

I. Technical Field

The technology disclosed herein generally relates to power amplifiers, and more specifically, to overvoltage protection (OVP) loops for power amplifiers.

II. Background Technology

In modern society, computing devices are ubiquitous, and more specifically, mobile communication devices are becoming increasingly prevalent. The proliferation of these mobile devices is partly driven by the numerous functions currently enabled on them. The increased processing power in these devices means that mobile communication devices have evolved from mere communication tools into sophisticated mobile entertainment hubs, thereby enhancing the user experience. With the emergence of countless functions available on such devices, there has been a shift towards newer cellular standards to provide greater bandwidth to accommodate all the data used by these functions. New cellular standards such as fifth-generation (5G) have new power level fluctuations, which may place new strain on the power amplifiers associated with the transceivers in mobile computing devices. This strain provides space for innovation.

Summary of the Invention

The aspects disclosed in the detailed embodiments include systems and methods for providing a protection loop for a power amplifier. Specifically, exemplary aspects of this disclosure detect overvoltage conditions at the output of the power amplifier and selectively create a short circuit at the base or gate of a transistor within the power amplifier to debias the transistor and prevent damage from the overvoltage condition. Providing this fast-acting overvoltage protection option makes it easier to adjust and protect the power amplifier under conditions with peak-to-average power ratios. This protection can prevent damage to transistors from possible rapid power fluctuations, especially in current cellular standards.

In this regard, in one aspect, a power amplifier stage is disclosed. The power amplifier stage includes a power amplifier unit. The power amplifier stage also includes a voltage detection circuit coupled to the output of the power amplifier unit. The power amplifier stage further includes an overvoltage protection (OVP) circuit coupled to the voltage detection circuit. The power amplifier stage also includes a switch configured to short-circuit the power amplifier unit to ground based on a signal from the OVP circuit.

In another aspect, a method for protecting a power amplifier stage from overvoltage conditions is disclosed. The method includes detecting the voltage at the output of a power amplifier unit. The method further includes closing a switch to short-circuit and ground the power amplifier unit when the voltage at the output of the power amplifier unit exceeds a threshold.

In another aspect, a mobile terminal is disclosed. The mobile terminal includes a power amplifier stage. The power amplifier stage includes a power amplifier unit. The power amplifier stage further includes a voltage detection circuit coupled to the output of the power amplifier unit. The power amplifier stage also includes an OVP circuit coupled to the voltage detection circuit. The power amplifier stage further includes a switch configured to short-circuit the power amplifier unit to ground based on a signal from the OVP circuit.

Attached Figure Description

Figure 1 is a circuit diagram of a power amplifier with conventional overvoltage protection (OVP) circuitry;

Figure 2A is a circuit diagram of a single-ended power amplifier stage with an OVP circuit according to an exemplary aspect of this disclosure;

Figure 2B is a circuit diagram of a differential power amplifier stage with an OVP circuit according to an exemplary aspect of this disclosure;

Figure 3 is a block diagram of the hybrid circuit and the OVP circuit;

Figure 4 is a flowchart illustrating an exemplary process using the OVP circuit of this disclosure;

Figure 5 is a block diagram of a mobile terminal, which may include the OVP circuitry of Figures 2A-3 and 6 according to this disclosure;

Figure 6 is a block diagram illustrating how to provide protection circuitry for the switches used to provide OVP for the power amplifier stage.

Detailed Implementation

The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. Those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically described herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extending to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

For example, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a (a, an)” and “described” are intended to also include the plural forms. It should be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” as used herein specify the presence of stated features, integrals, steps, operations, elements, and/or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formal sense.

The aspects disclosed in the detailed embodiments include systems and methods for providing a protection loop for a power amplifier. Specifically, exemplary aspects of this disclosure detect overvoltage conditions at the output of the power amplifier and selectively create a short circuit at the base or gate of a transistor within the power amplifier to debias the transistor and prevent damage from the overvoltage condition. Providing this fast-acting overvoltage protection option makes it easier to adjust and protect the power amplifier under conditions with peak-to-average power ratios. This protection can prevent damage to transistors from possible rapid power fluctuations, especially in current cellular standards.

Before describing the exemplary aspects of this disclosure, a brief discussion of the disadvantages of existing overvoltage protection (OVP) circuits is provided with reference to Figure 1. The exemplary aspects of this disclosure will now be discussed with reference to Figure 2A.

In this regard, Figure 1 is a circuit diagram of a power amplifier stage 100, which may have multiple parallel power amplifier units 102(1)-102(N), where N = 4 for illustrative purposes. As shown, each power amplifier unit 102(1)-102(N) may include a corresponding transistor 104(1)-104(N). The corresponding collector (unlabeled) of transistor 104(1)-104(N) may be coupled to a radio frequency (RF) output 106. The incoming signal to be amplified may pass through a corresponding AC blocking capacitor 108(1)-108(N). A bias circuit 110 may provide a bias at the corresponding base (unlabeled) of transistor 104(1)-104(N) via corresponding ballast resistors 112(1)-112(N). A voltage detector circuit 114 may detect the voltage at the RF output 106 and provide an indication of the voltage condition to an OVP circuit 116. OVP circuit 116 can provide control signals to bias circuit 110 to debias power amplifier units 102(1)-102(N) in the presence of overvoltage conditions.

The OVP scheme includes a bias circuit 110, which results in relatively slow debiasing of transistors 104(1)-104(N) because the bias circuit 110 may have a relatively long time constant or otherwise impose a delay. While effective for many types of overvoltage protection, the advent of newer cellular standards has brought the possibility that fast, large peak powers may exist that do not significantly alter the average power but do exert short-term transient stress on transistors 104(1)-104(N). When these peak powers are too high, transistors 104(1)-104(N) may be damaged before they can be debiased.

The exemplary aspect of this disclosure provides a much faster debiasing solution that will allow for the avoidance of rapidly shifting peak power, and thus avoid damage to transistors within the power amplifier unit. More specifically, the exemplary aspect of this disclosure envisions distributed shunt to ground associated with the input of the power amplifier unit.

In this regard, Figure 2A illustrates a power amplifier stage 200A according to an exemplary aspect of the present disclosure. The power amplifier stage 200A is a single-ended power amplifier stage and may have multiple parallel power amplifier units 202(1)-202(M), wherein for illustrative purposes, M = 4. It should be understood that each power amplifier unit 202(1)-202(M) may include a transistor. In the exemplary aspect, the transistor may be a bipolar junction transistor (BJT) 204A or a field-effect transistor (FET) 204B. The corresponding power amplifier units 202(1)-202(M) may be coupled to an RF output 206. The incoming signal to be amplified may pass through corresponding AC blocking capacitors 208(1)-208(M). A bias circuit 210 may provide bias to the power amplifier units 202(1)-202(M) via corresponding ballast resistors 212(1)-212(M). Voltage detector circuit 214 can detect the voltage at RF output 206 and provide an indication of voltage conditions to OVP circuit 216. OVP circuit 216 can provide control signals to switches 218(1)-218(M).

Voltage detection in voltage detector circuit 214 is relatively fast. Similarly, activity in OVP circuit 216 is relatively fast. Therefore, most of the delay in the previous OVP circuit is in bias circuit 110. By not passing through bias circuit 110, switches 218(1)-218(M) can open and close much faster, and if switches 218(1)-218(M) are also fast, a short-circuit ground can be formed much faster than debiasing through bias circuit 110 or 210. This short-circuit grounding at the base of the BJT or the gate of the FET effectively shuts off and protects the transistors in power amplifier units 202(1)-202(M). While switches 218(1)-218(M) can be addressed individually, they can also be turned on simultaneously.

Although the power amplifier stage 200A is single-ended, this disclosure is not limited thereto. A differential power amplifier stage 200B is shown in Figure 2B. The power amplifier stage 200B may have multiple parallel power amplifier units 202A(1)-202A(M) and 202B(1)-202B(M), where M = 4 for illustrative purposes. It should be understood that each power amplifier unit 202A(1)-202A(M) and 202B(1)-202B(M) may include a transistor, such as a BJT or FET. The corresponding power amplifier units 202A(1)-202A(M) and 202B(1)-202B(M) may be coupled to RF outputs 206A, 206B. The incoming signal to be amplified may pass through the corresponding AC blocking capacitors 208A(1)-208A(M) and 208B(1)-208B(M). Bias circuit 210 can provide bias to power amplifier units 202B(1)-202B(M) via corresponding ballast resistors 212A(1)-212A(M) and 212B(1)-212B(M). Voltage detector circuits 214A and 214B can detect the voltage at RF outputs 206A and 206B and provide an indication of voltage conditions to OVP circuit 216. OVP circuit 216 can provide control signals to switches 218A(1)-218A(M) and 218B(1)-218B(M). In other respects, operation is essentially the same as that of power amplifier stage 200A in Figure 2A.

Although single-ended and differential power amplifier stages have been explicitly disclosed and illustrated, it should be understood that this disclosure is equally applicable to quadrature power amplifier stages, Dougherty power amplifiers, and any other load-modulated power amplifiers.

It should be understood that switch 218 can also be a transistor, and can be, for example, a BJT. The switch may be exposed to a large RF signal at its collector. If the RF signal at the collector becomes negative, the switch may turn on in an undesirable reverse mode. To prevent this undesirable operation, protection can be provided to the switch, as better illustrated by power amplifier stage 600 in Figure 6. Specifically, diode 602 can be positioned in series between the collector 604 of switch 218 and power amplifier unit 202. Diode 602 allows current in only one direction, so switch 218 will not operate in reverse mode. Alternatively, because diode 602, connected in series with switch 218, introduces some voltage drop between power amplifier unit 202 and ground (which may be suboptimal for protecting the power amplifier unit), diode 606 can be positioned together with bias circuit 210 (e.g., in series with internal bias transistor 608) such that switch 218 is always biased to prevent operation in reverse mode.

Figure 3 shows further details regarding a possible configuration of the OVP circuit 216. Specifically, the OVP circuit 216 can be coupled to output 206 (and, as shown, to differential outputs 206A, 206B). A voltage detector circuit 214 can be formed from diodes and capacitors to generate a detected voltage signal 300, which includes information about the voltage level. This signal 300 is then compared to a threshold. More specifically, the threshold level is subtracted from the detected voltage signal 300 in a threshold circuit 302. The threshold circuit 302 includes a coarse value formed by a plurality of transistors 304 operating as diodes and a fine value formed by transistors 306 having a resistor network 308. That is, the diodes are relatively coarse in terms of the value they add to the total threshold. To tune this value, the resistor network 308 coupled to transistors 306 adds a portion of the value of transistors 306 to the threshold. An overvoltage condition exists when the detected voltage signal 300 is high enough to turn on all of the plurality of transistors 304 and transistors 306. This overvoltage condition is detected using, for example, current-mode operation, and specifically, a Darlington current mirror 310 that requires a low current level to activate. Additional circuitry 312 may be present, but this signal, provided by the current mirror 310 at node 314, can be used to control switch 218. Note that there are many other ways to implement an overvoltage circuit.

Figure 4 provides a flowchart of process 400 associated with the operation of the power amplifier stage of this disclosure. Specifically, process 400 begins during normal operation and includes amplifying the incoming signal (box 402). Voltage detector circuit 214 detects the voltage at output 206 (box 404) and provides information about the detected voltage to OVP circuit 216. OVP circuit 216 determines whether the voltage exceeds a threshold (box 406) and closes switches 218(1)-218(M) to ground power amplifier units 202(1)-202(M) (box 408).

It should be understood that the power amplifier stage of this disclosure is well-suited for integration into mobile computing devices or mobile terminals or other devices capable of wireless communication. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

In this regard, Figure 5 is a system-level block diagram of an exemplary mobile terminal 500. The mobile terminal 500 includes an application processor 504 (sometimes referred to as a host), which communicates with a mass storage element 506 via a Universal Flash Memory (UFS) bus 508. The application processor 504 may further be connected to a display 510 via a Display Serial Interface (DSI) bus 512 and to a camera 514 via a Camera Serial Interface (CSI) bus 516. Various audio components, such as a microphone 518, a speaker 520, and an audio codec 522, may be coupled to the application processor 504 via a Serial Low Power Inter-Chip Multimedia Bus (SLIMbus) 524. Additionally, the audio components may communicate with each other via a Soundwire bus 526. A modem 528 may also be coupled to the SLIMbus 524 and/or the Soundwire bus 526. The modem 528 may be further connected to the application processor 504 via a peripheral component interconnect (PCI) or PCI high-speed (PCIe) bus 530 and/or a system power management interface (SPMI) bus 532.

Referring again to Figure 5, the SPMI bus 532 can also be coupled to a local area network (LAN or WLAN) IC 534, a power management integrated circuit (PMIC) 536, a companion IC (sometimes referred to as a bridge chip) 538, and a radio frequency IC (RFIC) 540. It should be understood that separate PCI buses 542 and 544 can also couple the application processor 504 to the companion IC 538 and the WLAN IC 534. The application processor 504 can further be connected to the sensor 546 via the sensor bus 548. The modem 528 and the RFIC 540 can communicate using bus 550.

Referring again to Figure 5, RFIC 540 can be coupled to one or more RFFE components, such as antenna tuner 552, switch 554, and power amplifier 556, via RF front-end (RFFE) bus 558. Additionally, RFIC 540 can be coupled to packet tracking power supply (ETPS) 560 via bus 562, and ETPS 560 can communicate with power amplifier 556. Generally, the RFFE components including RFIC 540 can be considered as RFFE system 564. It should be understood that RFFE bus 558 can be formed by clock lines and data lines (not shown). The power amplifier stage of this disclosure can be found in power amplifier 556 or other transceivers (e.g., Wi-Fi, Bluetooth, or similar transceivers) within mobile terminal 500.

It should also be noted that the operational steps described in any of the exemplary aspects herein are for the purpose of providing examples and discussion. The described operations can be performed in a number of different orders besides the order shown. Furthermore, the operations described in a single operational step can actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that those skilled in the art will readily appreciate that the operational steps shown in the flowcharts can undergo numerous different modifications. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description.

The prior description of this disclosure has been provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims (19)

1. A power amplifier stage, comprising: Power amplifier unit; A voltage detection circuit coupled to the output of the power amplifier unit; An overvoltage protection (OVP) circuit coupled to the voltage detection circuit; and A switch configured to short-circuit the power amplifier unit to ground based on a signal from the OVP circuit. 2. The power amplifier stage according to claim 1 further includes a plurality of power amplifier units, each power amplifier unit being coupled to the voltage detection circuit. 3. The power amplifier stage according to claim 1, wherein the output includes a single-ended output. 4. The power amplifier stage according to claim 2, wherein the output includes a differential output. 5. The power amplifier stage according to claim 1, wherein the power amplifier unit comprises a bipolar junction transistor (BJT). 6. The power amplifier stage of claim 1, wherein the power amplifier unit comprises a field-effect transistor (FET). 7. The power amplifier stage of claim 1, wherein the switch comprises a transistor. 8. The power amplifier stage according to claim 1 further includes a bias circuit coupled to the switch via a ballast resistor. 9. The power amplifier stage of claim 1, wherein the OVP circuit includes a Darlington current mirror. 10. A method for protecting a power amplifier stage from overvoltage conditions, the method comprising the steps of: Detect the voltage at the output of the power amplifier unit; and When the voltage at the output of the power amplifier unit exceeds a threshold, the switch is closed, causing the power amplifier unit to be short-circuited to ground. 11. The method of claim 10, wherein detecting the voltage includes detecting the voltage of the plurality of power amplifier units. 12. The method of claim 10, further comprising comparing the voltage at the output with the threshold in an overvoltage protection (OVP) circuit. 13. The method of claim 10, wherein the detection comprises detection using a diode and a capacitor. 14. The method of claim 10, wherein closing the switch comprises using a transistor as the switch. 15. The method of claim 10, further comprising biasing the power amplifier unit. 16. A mobile terminal, comprising: The power amplifier stage includes: Power amplifier unit; A voltage detection circuit coupled to the output of the power amplifier unit; An overvoltage protection (OVP) circuit coupled to the voltage detection circuit; and A switch configured to short-circuit the power amplifier unit to ground based on a signal from the OVP circuit. 17. The mobile terminal according to claim 16 further includes a plurality of power amplifier units, each power amplifier unit being coupled to the voltage detection circuit. 18. The mobile terminal according to claim 16, wherein the output includes a single-ended output. 19. The mobile terminal according to claim 17, wherein the output includes differential output.