WO2019200612A1

WO2019200612A1 - Overvoltage protection circuit of mos transistor in wireless receiving circuit

Info

Publication number: WO2019200612A1
Application number: PCT/CN2018/083927
Authority: WO
Inventors: 王红波
Original assignee: 华为技术有限公司
Priority date: 2018-04-20
Filing date: 2018-04-20
Publication date: 2019-10-24
Also published as: CN111492580A

Abstract

An overvoltage protection circuit, which relates to the technical field of electronics and which comprises a first detection circuit (11) and a protection circuit (12); the first detection circuit (11) is used for outputting a first mark signal (60) according to an input signal (50) and a reference signal (40) of an input terminal (200) of a wireless receiving circuit (20); the input terminal (200) of the wireless receiving circuit (20) is coupled to a first MOS transistor (21) comprised in the wireless circuit (20); and the protection circuit (12) enters a protection state in response to the first mark signal (60) so as to attenuate the voltage amplitude of the input signal (50). The overvoltage protection circuit is used for overvoltage protection and may accurately and promptly protect a MOS transistor in case of overvoltage of a MOS transistor in a wireless receiving circuit, improving the service life of the MOS transistor.

Description

Overvoltage protection circuit for MOS tube in wireless receiving circuit

Technical field

The present application relates to the field of electronic technologies, and in particular, to an overvoltage protection circuit for a metal oxide semiconductor field effect transistor (MOS) tube in a wireless receiving circuit.

Background technique

The radio frequency chip in the electronic device is used to implement functions such as radio frequency transmission and reception, frequency synthesis, and power amplification of the electronic device. When a high-power (ie, large-scale) RF AC signal is present at the receiving port of the RF chip, the voltage drop between the MOS ports at the input end of the receiving circuit is likely to be greater than the operating voltage, thereby making the MOS tube susceptible to an overvoltage condition and being damaged. For example, the wireless fidelity (wifi) chip of the mobile phone is close to the transmitting antenna, and the MOS tube of the RF input end of the low noise amplifier (LNA) at the front end of the RF receiving circuit in the wifi chip is easily damaged in an overvoltage state. .

The prior art places a diode between the RF input of the LNA and the power supply and between the RF input and the ground, between the gate and the drain of the MOS transistor at the RF input of the LNA, and between the gate and the source. Place one or more diodes in series. When there is a high-power RF input signal externally, if the amplitude of the RF input signal is greater than the sum of the turn-on voltages of n (positive integer) diodes, the current in the diode increases exponentially, and the diode is in an on state, each The forward voltage drop of the diode is clamped around the turn-on voltage. Therefore, the voltage drop between the gate and the source of the MOS transistor at the RF input terminal and between the gate and the drain can be limited to the clamp voltage by n diode forward conduction characteristics, and the clamp voltage is basically The sum of the n diode turn-on voltages prevents the MOS transistor at the RF input from being damaged due to overvoltage, thereby protecting the MOS transistor and the RF chip at the RF input end.

That is to say, in the prior art, when the amplitude of the RF input signal is greater than the turn-on voltage of the n diodes, the overvoltage protection of the MOS transistor at the RF input terminal is turned on. In fact, due to different manufacturing processes, temperature differences and variations, and differences and changes in currents in the diodes, the value of the diode turn-on voltage fluctuates somewhat. Therefore, the method of using diodes to protect MOS transistors in the prior art cannot be accurate. The overvoltage protection is provided for the MOS tube of the RF input terminal in time, so that the MOS tube at the RF input end is easily damaged by overvoltage.

Summary of the invention

The embodiment of the present invention provides an overvoltage protection circuit for a MOS tube in a wireless receiving circuit, which can accurately and timely protect the MOS tube in the case of overvoltage of the MOS tube in the wireless receiving circuit, thereby improving the service life of the MOS tube.

To achieve the above objective, the embodiment of the present application adopts the following technical solutions:

On the one hand, the embodiment of the present application provides an overvoltage protection circuit 10 of the first MOS transistor 21 in the wireless receiving circuit 20, including a first detecting circuit 11 and a protection circuit 12. The first detecting circuit 11 is configured to output the first flag signal 60 according to the input signal 50 and the reference signal 40 of the input terminal 200 of the wireless receiving circuit 20, the input terminal 200 of the wireless receiving circuit 20 and the first MOS tube included in the wireless circuit 20 21 coupling. The protection circuit 12 enters a protection state in response to the first flag signal 60 to attenuate the voltage amplitude of the input signal 50.

In this solution, the first detecting circuit 11 can accurately determine whether the input signal 50 is a high power signal according to the voltage amplitude of the input signal 50 and the voltage amplitude of the reference signal 40, thereby triggering the protection circuit 12 to enter protection when determined as a high power signal. The state, in turn, opens the overvoltage protection of the first MOS transistor 21, attenuates the voltage amplitude of the input signal 50, and increases the lifetime of the first MOS transistor 21.

In one possible design, the first detection circuit 11 includes a comparator 111, the input of which inputs a first signal 30 and a reference signal 40, respectively, the first signal 30 being associated with the input signal 50. The comparator 111 is configured to output the first flag signal 60 according to a comparison result of the voltage value of the first signal 30 and the reference voltage value of the reference signal 40.

In this solution, the first detecting circuit 11 can accurately determine the signal input by the external receiving circuit 20 as a high-power signal by comparing the reference voltage value with the voltage value of the first signal 30 by the comparator 111, thereby turning on the pair in time. Protection of the first MOS tube 21.

In another possible design, the protection circuit 12 includes a second MOS transistor 121, the gate of the second MOS transistor 121 is coupled to the output of the first detection circuit 11, and the second MOS transistor 121 is coupled to the input terminal 200 and ground. between. The second MOS transistor 121 is turned on in response to the first flag signal 60 to cause the protection circuit 12 to enter a protection state.

The function of the second MOS transistor 121 is equivalent to a switch, and can be used to disconnect when the input signal 50 is a low power signal, and to be turned on when the input signal 50 is a high power signal.

In another possible design, the second MOS transistor 121 is an n-metal oxide semiconductor (NMOS) transistor, the source of the second MOS transistor 121 is grounded, and the drain of the second MOS transistor 121 is It is coupled to the input 200 of the wireless receiving circuit 20.

In another possible design, the protection circuit 12 further includes two anti-parallel diodes 122 coupled to the input 200 of the wireless receiving circuit 20 by two anti-parallel diodes 122.

In this scheme, the protection circuit can limit the magnitude of the voltage amplitude of the input signal 50 through the second MOS transistor 121 and the two anti-parallel diodes 122.

In another possible design, the input signal 50 of the wireless receiving circuit 20 is an AC input signal, and the first detecting circuit 11 further includes a converting circuit 112 for converting the AC input signal into the first signal 30, A signal 30 is a DC signal.

In another possible design, the first detecting circuit 11 further includes a reference circuit 113 for outputting the reference signal 40, and the reference signal 40 is a direct current signal.

In another possible design, the conversion circuit 112 includes a third MOS transistor 1121 and a first component 1123 connected in series, the first component 1123 is a current source or a resistor, and the gate of the third MOS transistor 1121 is coupled to an AC input signal. The series connection point of the third MOS transistor 1121 and the first component 1123 is used to output the first signal 30.

In another possible design, the reference circuit 113 includes a fourth MOS transistor 1131 and a second component 1132 connected in series, the second component 1132 is a current source or a resistor, and the gate of the fourth MOS transistor 1131 is coupled to a reference point. The series connection of the fourth MOS transistor 1131 and the second component 1132 is used to output the reference signal 40.

In another possible design, the third MOS transistor 1121 is identical in size to the fourth MOS transistor 1132, and the first component 1123 is identical in size to the second component 1132.

In this scheme, there is a good match when the circuit layout is implemented, so that the threshold voltage caused by the process, that is, the change of the voltage at which the MOS transistor starts to operate, affects the accuracy of the first detection circuit 11 and thus the high power signal can be reduced. The identification achieves a more accurate judgment.

In another possible design, the first detecting circuit 11 further includes a delay circuit 114 for maintaining the output first in the preset time period when the comparator 111 outputs the first flag signal 60. Flag signal 60.

In this scheme, after the first flag signal 60 jumps into a valid signal to cause the protection circuit 12 to enter the protection state, the delay circuit 114 can prevent the first flag signal 60 from jumping to the invalid signal again within a preset period of time. Thus, the protection circuit 12 can be continuously protected by the first MOS transistor 21 for a preset period of time.

In another possible design, the delay circuit 114 includes a fifth MOS transistor 1143, a first resistor 1141, and a first capacitor 1142. The fifth MOS transistor 1143 is connected in series with the first resistor 1141 between the power source and the ground. A series connection point of the MOS transistor 1143 and the first resistor 1141 is coupled to the first capacitor 1142 and is used to maintain the output of the first flag signal 60 for a predetermined period of time.

In another possible design, the first resistor 1141 and the first capacitor 1142 are respectively implemented by a MOS transistor.

In this solution, the first resistor 1141 and the first capacitor 1142 are both implemented by the MOS transistor to reduce the influence of process fluctuation on the magnitude of the RC product value, and improve the delay precision of the delay circuit 114.

In another possible design, the first detection circuit 11 is further configured to provide the first flag signal 60 to a digital baseband (DBB) circuit 22 in the wireless receiving circuit 20. The DBB 22 is for outputting the first control signal 70 to the protection circuit 12. Protection circuit 12 maintains a protected state in response to first control signal 70.

In this scheme, even if the first flag signal 60 is attenuated due to the attenuation of the input signal 50 in the protected state, the first control signal 70 may cause the protection circuit 12 to remain in a protected state.

In another possible design, the digital baseband circuit DBB 22 in the wireless receiving circuit 20 is further configured to provide the second control signal 80 to the protection circuit 12 when determining that the voltage amplitude of the input signal 50 is less than the first preset value. Protection circuit 12 exits the protection state in response to second control signal 80.

In this scheme, the DBB 22 can trigger the protection circuit 12 to exit the protection state when it is determined that the signal input from the outside of the wireless receiving circuit 20 is a low power signal.

In another possible design, the overvoltage protection circuit 10 further includes a second detection circuit 13 for providing a second flag when detecting that the voltage amplitude of the input signal 50 is less than a second predetermined value. Signal 90 is applied to protection circuit 12, which exits the protection state in response to second flag signal 90.

In this scheme, the second detecting circuit 13 can trigger the protection circuit 12 to exit the protection state when it is determined that the signal input from the outside of the wireless receiving circuit 20 is a low power signal.

In another possible design, the overvoltage protection circuit 10 further includes a second detection circuit 13 for providing a second flag when detecting that the voltage amplitude of the input signal 50 is less than a second predetermined value. The signal 90 is applied to the DBB 22. The second flag signal 90 is used to control the DBB 22 to provide a second control signal 80 to the protection circuit 12, and the protection circuit 12 exits the protection state in response to the second control signal 80.

In this scheme, the second detecting circuit 13 can trigger the DBB 22 to provide the second control signal 80 to the protection circuit 12 when determining that the signal input from the outside of the wireless receiving circuit 20 is a low power signal, thereby triggering the protection circuit 12 to exit the protection state.

In another possible design, the first flag signal 60 is also used to control the digital baseband circuit DBB 22 to reduce the gain of the amplifier in the wireless receiving circuit 20.

In this way, problems such as signal distortion due to saturation of the amplified signal of the amplifier in the wireless receiving circuit 20 can be prevented.

In another aspect, embodiments of the present application provide a circuit system including the overvoltage protection circuit 10 and the wireless receiving circuit 20 in any of the possible designs of the above aspects.

In one possible design, the wireless receiving circuit 20 includes one or more of a low noise amplifier, a mixer, a low pass filter, a variable gain amplifier, an analog to digital converter, or a digital baseband circuit.

In another aspect, embodiments of the present application provide a chip including circuitry in any of the possible designs of the above aspects of the claims.

DRAWINGS

1 is a schematic structural diagram of a mobile phone according to an embodiment of the present application;

2 is a schematic structural diagram of a receiving module according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a circuit according to an embodiment of the present disclosure;

4 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 5 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 10 is a timing diagram of signals according to an embodiment of the present application;

FIG. 11 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 12 is another timing diagram of signals provided by an embodiment of the present application;

FIG. 13 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 14 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 15 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

16 is another signal timing diagram provided by an embodiment of the present application;

FIG. 17 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 18 is another timing diagram of signals provided by an embodiment of the present application;

FIG. 19 is a schematic structural diagram of a delay circuit according to an embodiment of the present disclosure;

FIG. 20 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 21 is another timing diagram of signals provided by an embodiment of the present application;

FIG. 22 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 23 is another timing diagram of signals provided by an embodiment of the present application;

FIG. 24 is a schematic structural diagram of another circuit according to an embodiment of the present disclosure;

FIG. 25 is another timing diagram of signals provided by an embodiment of the present application.

detailed description

For ease of understanding, the description of some of the concepts related to the embodiments of the present application is given for reference. As follows:

MOS tube port: 4 ports including gate, source, drain and substrate.

Overvoltage state: The voltage drop between the ports of the MOS transistor (for example, the voltage drop between the gate and the source, the voltage drop between the gate and the drain, etc.) is greater than the state in which the MOS transistor is in the operating voltage.

Clamp: Limit the potential of a point to a specified potential.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise stated, "/" means the meaning of or, for example, A/B may represent A or B; "and/or" herein is merely a description of the associated object. The association relationship indicates that there may be three relationships, for example, A and/or B, which may indicate that there are three cases in which A exists separately, A and B exist at the same time, and B exists separately. In addition, in the description of the embodiments of the present application, "a plurality" means two or more than two.

The overvoltage protection circuit provided by the embodiment of the present application can be used for a wireless receiving circuit of an electronic device in a wireless communication system, and can prevent the first MOS transistor connected to the input end of the wireless receiving circuit when the wireless receiving circuit receives the high power signal Overpressure and damage.

The wireless communication system refers to a system for communicating by using wireless electromagnetic waves, and the wireless electromagnetic wave may include a radio frequency signal, a microwave signal, a radio signal having a lower frequency than the radio frequency information, and a wireless electromagnetic wave signal of other frequency bands. For example, the wireless communication system may be wifi, wideband code division multiple access (WCDMA), time division synchronous code division multiple access (TD-SCDMA) time division synchronization code division. Multiple access, long term evolution (LTE), near field communication (NFC), new radio (NR) or Bluetooth system.

The electronic device may be a mobile phone, a tablet computer, a wearable device, an in-vehicle device, an augmented reality (AR)/virtual reality (VR) device, a notebook computer, a super mobile personal computer (ultra-mobile personal) Any device or chip that can receive a wireless signal, such as a UMPC, a netbook, a personal digital assistant (PDA), and the like, is not limited in this embodiment.

Taking the electronic device in the embodiment of the present application as a mobile phone as an example, the general hardware architecture of the mobile phone is described. As shown in FIG. 1, the mobile phone 001 may include: a display 01, a processor 02, a memory 03, a wireless communication module 04, a radio frequency (RF) circuit 05, a gravity sensor 06, an audio circuit 07, a speaker 08, a microphone 09, and the like. Components, which can be connected by bus or directly. It will be understood by those skilled in the art that the structure of the handset shown in FIG. 1 does not constitute a limitation to the handset, and the handset may include more components than those illustrated, or some components of the combination, or have different component arrangements.

The display 01 can be used to display information input by the user or information provided to the user, as well as various menus of the mobile phone, and can also accept input operations of the user. Specifically, the display 01 may include a display panel 011 and a touch panel 012. The display panel 011 can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like. The touch panel 012, which may also be referred to as a touch screen, a touch sensitive screen, a touch screen, etc., can collect contact or non-contact operations on or near the user (eg, the user uses any suitable object or accessory such as a finger, a stylus, etc. The operation on the touch panel 012 or in the vicinity of the touch panel 012) and driving the corresponding connection device according to a preset program.

Further, the touch panel 012 can cover the display panel 011, and the user can display the content according to the display panel 011 (the displayed content includes any one or more of the following combinations: a soft keyboard, a virtual mouse, a virtual button, an icon, etc. The operation is performed on or near the touch panel 012 covered on the display panel 011. After the touch panel 012 detects an operation thereon or nearby, it is transmitted to the processor 02 through the input/output subsystem to determine the user input, and then the processor 02 provides the display panel 011 through the input/output subsystem according to the user input. Corresponding visual output. Although the touch panel 012 and the display panel 011 are used as two independent components to implement the input and input functions of the mobile phone in FIG. 1, in some embodiments, the touch panel 012 can be integrated with the display panel 011. Realize the input and output functions of the phone.

The processor 02 is a control center of the mobile phone 001, which connects various parts of the entire mobile phone by various interfaces and lines, by running or executing software programs and/or modules stored in the memory 03, and calling data stored in the memory 03, The mobile phone 001 is monitored as a whole by performing various functions and processing data of the mobile phone 001. In a specific implementation, as an embodiment, processor 02 may include one or more processing units; processor 02 may integrate an application processor and a modem processor. The application processor mainly processes an operating system, a user interface, an application, etc., and the modem processor mainly processes wireless communication. It can be understood that the above modem processor may not be integrated into the processor 02.

The memory 03 can be used to store data, software programs, and modules, and can be a volatile memory such as a random-access memory (RAM) or a non-volatile memory. For example, a read-only memory (ROM), a flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); or a combination of the above types of memories.

The wireless communication module 04 may include one or more of a wifi chip, a Bluetooth module, an NFC module, or a general packet radio service (GPRS) module, and may be used to communicate with other devices through wireless communication technologies or call.

The RF circuit 05 may include a transmitting module 051 and a receiving module 052, which may be used to transmit information during communication or a call, and the receiving module 052 may be used to receive information during communication or during a call, and process the received information to the processor 02 for processing. . Generally, the RF circuit 05 specifically includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, and the like. For example, referring to FIG. 2, the receiving module 052 can include an LNA 521, a mixer 522, a low pass filter (LPF) 523, a variable gain amplifier (VGA) 524, and analog to digital conversion. (analog to digital converter, ADC) 525 and DBB 526. The RF input signal received by the receiving module 52 is amplified by the LNA, and then down-converted by the mixer into a signal including an intermediate frequency signal component or a baseband signal component; the filter filters out the useful intermediate frequency signal or baseband signal and sends it to the modulus. The converter converts to a digital signal; then, the digital signal enters the DBB for processing. For example, the DBB performs operations such as decoding or demodulating a digital signal. The LNA is located at the front end of the receiving module 052, that is, the signal received by the receiving module 052 passes through the LNA before reaching the other components of the receiving module 052. Alternatively, the DBB can also be integrated in the processor 02. The receiving module 052 can also be called a wireless receiving circuit or simply a receiving circuit.

Gravity sensor 06 can detect the acceleration of the mobile phone in all directions (usually three-axis). When it is stationary, it can detect the magnitude and direction of gravity. It can be used to identify the gesture of the mobile phone (such as horizontal and vertical screen switching, related Game, magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tapping). It should be noted that the mobile phone 001 may also include other sensors, such as a pressure sensor, a light sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, and the like, and details are not described herein.

The audio circuit 07, the speaker 08, and the microphone 09 can provide an audio interface between the user and the handset 001.

Although not shown, the mobile phone 001 may further include a function module such as a camera, a power source, and the like, and details are not described herein again.

For example, the wireless receiving circuit involved in the embodiment of the present application may be a radio frequency receiving circuit, such as a radio frequency receiving circuit in a mobile phone wifi chip. The overvoltage protection circuit according to the embodiment of the present application may be disposed in the mobile phone wifi chip for protecting the first MOS transistor connected to the LNA input end in the wifi chip receiving circuit. The wireless receiving circuit may be the receiving module 052 or other receiving component mentioned in the previous embodiment.

The overvoltage protection circuit of the MOS transistor in the wireless receiving circuit provided by the embodiment of the present application will be described in detail below through specific embodiments.

The embodiment of the present application provides an overvoltage protection circuit, which can be used to protect a MOS tube at an input end of a wireless signal receiving circuit, and prevent the MOS tube at the input end of the receiving circuit from being damaged due to overvoltage. Referring to FIG. 3, the overvoltage protection circuit 10 may include a first detection circuit 11 and a protection circuit 12. The first detecting circuit 11 can be configured to output the first flag signal 60 according to the input signal 50 of the input terminal 200 of the wireless receiving circuit 20 and the reference signal 40. The input terminal 200 of the wireless receiving circuit 20 is coupled to the first MOS transistor 21 included in the wireless circuit 20. For example, the first MOS transistor 21 is the first MOS transistor in the wireless receiving circuit 20 for receiving signals, that is, the MOS transistor is not coupled between the input terminal 200 of the wireless receiving circuit 20 and the first MOS transistor 21. The protection circuit 12 enters a protection state in response to the first flag signal 60 to attenuate the voltage amplitude of the input signal 50. Wherein, when the input signal 50 reaches or is greater than the reference signal 40, the first detecting circuit 11 outputs the first flag signal 60 to trigger the attenuation.

It should be noted that, in various embodiments of the present application, coupling refers to direct connection or connection through other devices, exemplarily representing an electrical connection relationship. For example, the input terminal 200 of the wireless receiving circuit 20 and the first MOS transistor 21 may include: the input terminal 200 is directly connected to the first MOS transistor 21; or the input terminal 200 and the first MOS transistor 21 are indirectly through some capacitor or resistance device. connection.

Further, in FIG. 3, the wireless receiving circuit 20 may further include a module 24 and a module 25. The module 24 is coupled to the first port of the first MOS transistor 21 for providing a DC bias to drive the first MOS transistor 21 to operate. The second port of the first MOS transistor 21 is coupled to the ground, and the third port of the first MOS transistor 21 is connected to the other portion of the wireless receiving circuit 20, that is, the module 25, to realize the receiving function of the wireless receiving circuit 20 in combination with other portions. Module 25 can cooperate with first MOS transistor 21 to form at least a portion of LNA 521.

It can be understood that, in FIG. 3, the first MOS transistor 21 is taken as an NMOS transistor as an example. Alternatively, the first MOS transistor 21 may be a P-channel metal oxide semiconductor (positive channel metal oxide semiconductor). The PMOS) tube, the type of the first MOS transistor 21 is not limited in the embodiment of the present application.

Specifically, the first detecting circuit 11 can monitor the voltage amplitude of the input signal 50 at the input end 200 of the wireless receiving circuit 20 in real time. When the first detecting circuit 11 accurately determines the voltage amplitude of the input signal 50 of the input terminal 200 of the wireless receiving circuit 20 reaches or exceeds the preset value a according to the voltage amplitude of the reference signal 40 and the voltage amplitude of the input signal 50, that is, the reference signal corresponds to In the amplitude, it can be stated that the input signal 50 is a high-power signal, that is, the signal input from the outside by the wireless receiving circuit 20 is a high-power signal, and the first detecting circuit 11 can output the first flag signal 60 to the protection circuit 12, and the protection circuit 12 responds to The first flag signal 60 outputted by the first detecting circuit 11 enters a protection state, thereby turning on the overvoltage protection of the MOS transistor of the input port of the wireless receiving circuit 20, and attenuating the voltage amplitude of the input signal 50 to prevent the MOS tube from being damaged due to overvoltage. . The preset value a can be set according to actual needs.

Since the on-voltage of the diode is dynamically fluctuating and the fluctuation range is large, the overvoltage of the MOS transistor is turned on by the prior art simply by the input signal 50 having a larger amplitude than the single or multiple diodes of the simple device. Compared with the protection, the first detecting circuit 11 in the embodiment of the present application can accurately determine whether the input signal 50 is a high-power signal according to the voltage amplitude of the input signal 50 and the voltage amplitude of the reference signal 40, thereby triggering when determining to be a high-power signal. The protection circuit 12 enters the protection state, and the overvoltage protection of the first MOS transistor 21 is turned on, the voltage amplitude of the input signal 50 is attenuated, and the service life of the first MOS transistor 21 is improved.

In some embodiments of the present application, referring to FIG. 4, the first detection circuit 11 includes a comparator 111. The input terminal 1110 of the comparator 111 inputs a first signal 30 and a reference signal 40, respectively, and the first signal 30 is associated with the input signal 50. In other words, the first signal 30 is used to indicate the voltage amplitude of the input signal 50. The comparator 111 is configured to output the first flag signal 60 according to a comparison result of the voltage value of the first signal 30 and the reference voltage value of the reference signal 40.

In one case, the voltage value of the first signal 30 can be positively correlated with the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, that is, the greater the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, the higher the voltage value of the first signal 30 is. Big. Alternatively, in another case, the voltage value of the first signal 30 may also be negatively correlated with the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, that is, the voltage amplitude of the input signal 50 of the wireless receiving circuit 20 is larger, the first signal 30 is The smaller the voltage value. In the case of a positive correlation and a negative correlation, the reference voltage value of the reference signal 40 can be set to a value of a different magnitude, the flipping condition of the comparator 111 is different, and the output signal is also different. The voltage amplitude of the input signal 50 can be understood as a parameter for describing the magnitude of the amplitude, such as the peak-to-peak value or the effective value of the input signal 50.

Specifically, the first detecting circuit 11 can determine whether the voltage amplitude of the input signal 50 exceeds the preset value a by comparing the reference voltage value with the voltage value of the first signal 30 by the comparator 111. When the voltage amplitude of the input signal 50 exceeds the preset value a, it can be stated that the input signal 50 is a high power signal, that is, the signal input externally by the wireless receiving circuit 20 is a high power signal, and the first detecting circuit 11 can output through the comparator 111. The first flag signal 60 is applied to the protection circuit 12, thereby triggering the protection circuit 12 to enter the protection state in time, turning on the overvoltage protection of the first MOS transistor 21, and attenuating the voltage amplitude of the input signal 50 to prevent the MOS transistor from being damaged due to overvoltage.

In addition, the wireless receiving circuit 20 may further include a DBB 22, which may be used to set a reference voltage value of the reference signal 40. That is to say, the reference voltage value can be accurately configured by the DBB 22 (for example, register configuration or digital configuration), and the configured reference voltage value can be kept stable and substantially does not fluctuate, so that the first detecting circuit 11 is based on the accurate reference voltage. The value, the voltage amplitude of the input signal 50, and the comparator 111 can accurately determine whether the amplitude of the input signal 50 is greater than a preset value a, that is, whether the signal externally input by the wireless receiving circuit 20 is a high power signal. When the reference voltage value needs to be changed, the reference voltage value can be changed by DBB 22 by software upgrade or the like. Illustratively, the DBB 22 can be the DBB 526 in FIG.

The DBB 22 can flexibly set the specific value of the reference voltage value according to actual needs. For example, the reference voltage value can be any value such as 0.8V, 0.81V, or 0.75V. The prior art turns on the overvoltage protection of the MOS transistor when the amplitude of the input signal 50 is greater than the sum of the n diode turn-on voltages, and the sum of the n diode turn-on voltages can be considered as an integral multiple of the single diode turn-on voltage, which is discrete The value, for example, when the turn-on voltage is 0.7V, the sum of the n diode turn-on voltages may be a value of 0.7V, 1.4V, or 2.1V, and the span between adjacent values is large, when the first MOS transistor 21 works normally. The operating voltage in the state is between two adjacent values. For example, when the operating voltage is 1.1V, if a single diode is used to protect the MOS transistor, the single diode clamps the voltage between the ports of the first MOS transistor 21 at 0.7V. Left and right, the operating voltage of the first MOS transistor 21 is much different, which easily affects the normal operation of the first MOS transistor 21; if two diodes are used to protect the first MOS transistor 21, the two diodes will be the first MOS transistor 21 The voltage between the ports is clamped at 1.4 V, which is much different from the operating voltage of the first MOS transistor 21, and the first MOS transistor 21 is easily damaged by overvoltage. Embodiments of the present invention help to increase design flexibility compared to the prior art.

It should be noted that the operating voltage of the first MOS transistor 21 is a parameter value provided when the first MOS transistor 21 is shipped from the factory. When the voltage difference between the different ports of the first MOS transistor 21 is less than the operating voltage, the first MOS transistor 21 It can work normally; when the voltage difference between the different ports of the first MOS transistor 21 is greater than the operating voltage, the first MOS transistor 21 is in an overvoltage state, and the performance and the like of the first MOS transistor 21 will be affected.

For example, referring to FIG. 5, the wireless receiving circuit 20 may specifically be the receiving module 052 shown in FIG. 2, and the first MOS transistor 21 in the wireless receiving circuit 20 is located in the device LNA coupled to the input terminal 200, and is an LNA input terminal. MOS tube. The DBB 22 in the wireless receiving circuit 20 can be used to configure the reference voltage value of the reference signal 40.

In addition, as the process size (nm) of the complementary metal oxide semiconductor (CMOS) process of the radio frequency chip is gradually decreased, the gate oxide layer is thinner and thinner, and the operating voltage and breakdown voltage of the MOS transistor are also decreasing gradually. For MOS transistors using advanced process processes (such as 28nm, 16nm, etc.), the gate oxide layer is thinner, the MOS tube's withstand voltage is getting lower and lower, and the small diode turn-on voltage fluctuation may cause the MOS transistor to overvoltage. And damaged. Moreover, with the reduction of the withstand voltage of the MOS tube, the voltage on the MOS cannot be limited to a safe range by diode protection. When the high-power RF signal is input, the maximum overvoltage of the MOS tube will exceed the normal operating voltage. More, so it is easier to damage. For example, when the operating voltage of the first MOS transistor 21 is 0.5V, the protection by a single diode can only limit the voltage between the ports of the first MOS transistor 21 to the conduction voltage, and the conduction voltage of the diode is higher than the operating voltage. At 0.5 V, the first MOS transistor 21 is easily in an overvoltage state. Further, since there is fluctuation, if the on-voltage of the diode is 0.9 V, 0.9 V is much higher than 0.5 V, and the first MOS transistor 21 is easily damaged by overvoltage. In the embodiment of the present application, the specific value of the reference voltage value can be flexibly set according to actual needs, so that the protection circuit 12 can be turned on accurately and timely even if the operating voltage of the first MOS transistor 21 is less than 0.7V of the single diode. The first MOS transistor 21 is protected.

In the embodiment of the present application, the protection circuit 12 includes a second MOS transistor 121, the gate of the second MOS transistor 121 is coupled to the output end of the first detection circuit 11, and the second MOS transistor 121 is coupled between the input terminal 200 and the ground. . The second MOS transistor 121 is turned on in response to the first flag signal 60 to cause the protection circuit 12 to enter a protection state. Referring to FIG. 6 , the second MOS transistor 121 may be an NMOS transistor. The source of the second MOS transistor 121 is grounded, and the drain of the second MOS transistor 121 is coupled to the input terminal 200 of the wireless receiving circuit 20 . The second MOS transistor 121 functions as a switch that can be used to disconnect when the input signal 50 is a low power signal and to conduct when the input signal 50 is a high power signal.

Specifically, in the protection circuit 12 shown in FIG. 6, when the input signal 50 is a high power signal, the first detection circuit 11 outputs the first flag signal 60, and the second MOS transistor 121 is turned on. The turned-on second MOS transistor 121 is equivalent to a resistor having a small resistance (for example, 10 Ω), and can attenuate the amplitude of the high-power signal of the input terminal 200 of the wireless receiving circuit 20 to a small value, and the second MOS transistor 121 does not substantially affect the normal receiving performance of the first MOS transistor 21. When the input signal 50 is a low power signal, the first detecting circuit 11 does not output the first flag signal 60, that is, the voltage of the output first flag signal 60 changes, the second MOS transistor 121 does not conduct, and the second at this time The MOS transistor 121 is equivalent to a resistor having a large resistance value (for example, several tens of MΩ). It can be considered that the protection circuit 12 is disconnected from the wireless receiving circuit 20 at this time, and the second MOS transistor 121 is substantially not applied to the wireless receiving circuit 20. Normal reception performance has an impact.

Further, referring to FIG. 7, the protection circuit 12 may further include two anti-parallel diodes 122 coupled to the input terminal 200 of the wireless receiving circuit 20 through two anti-parallel diodes 122. The reverse parallel diode 122 includes a first diode and a second diode, and a positive pole of the first diode is connected to a cathode of the second diode, and a cathode of the first diode is connected to the second diode. The positive pole of the pole tube is connected.

In the protection circuit 12 shown in FIG. 7, when the input signal 50 is a high power signal, the first detection circuit 11 outputs a first flag signal 60, the second MOS transistor 121 is turned on, and the antiparallel diode 122 is used for The voltage at the input terminal 200 of the wireless receiving circuit 20 is clamped at the turn-on voltage of the diode, thereby preventing the first MOS transistor 21 from being damaged due to overvoltage, and the second MOS transistor 121 does not substantially generate normal reception performance of the wireless receiving circuit 20. influences. When the input signal 50 is a low power signal, the first detecting circuit 11 does not output the first flag signal 60, the second MOS transistor 121 is not turned on, and the second MOS transistor 121 corresponds to a large resistance value (for example, several tens of MΩ). The resistance of the diode 122 in the anti-parallel can be considered to be disconnected from the wireless receiving circuit 20 at this time, and the diode may affect the normal receiving performance of the wireless receiving circuit 20.

That is to say, in the overvoltage protection circuit 10 provided in the embodiment of the present application, if the protection circuit 12 shown in FIG. 6 is used, the protection circuit 12 is substantially not applicable regardless of whether the input signal 50 is a high power signal or a low power signal. The normal receiving performance of the wireless receiving circuit 20 has an influence; if the protection circuit 12 shown in FIG. 7 is used, the diode 122 in the anti-parallel connection in the protection circuit 12 will be the wireless receiving circuit 20 only when the input signal 50 is a high-power signal. The normal reception performance has an effect, and when the input signal 50 is a low power signal, the diode in the protection circuit 12 does not substantially affect the normal reception performance of the wireless reception circuit 20. In the prior art, whether the input signal 50 is a high power signal or a low power signal, the protection diode affects the normal receiving performance of the wireless receiving circuit 20.

In the embodiment of the present application, the input signal 50 of the wireless receiving circuit 20 is a wireless AC input signal. Exemplarily, when the wireless receiving circuit 20 is the wireless receiving circuit 20 in the mobile phone wifi chip, and the first MOS transistor 21 is the MOS transistor of the LNA input end of the wireless receiving circuit 20, the AC input signal is a radio frequency AC input signal. Referring to Figure 8, the first detection circuit 11 includes a conversion circuit 112 that can be used to convert an AC input signal into a first signal 30, which is a DC signal.

Specifically, referring to FIG. 9 or FIG. 11, the conversion circuit 112 may include a third MOS transistor 1121 and a first component 1123 connected in series. The first component 1123 is a current source or a resistor, and the gate of the third MOS transistor 1121 is coupled to an AC. The input signal, the series connection point of the third MOS transistor 1121 and the first element 1123 is used to output the first signal 30. Also, the gate of the third MOS transistor 1121 is provided with a DC bias 1125 for superimposing the AC input signal at the input of the wireless receiving circuit 20 on the DC bias 1125. The DBB 22 can be specifically configured to set a reference voltage value according to the operating voltage of the first MOS transistor 21 and the DC bias 1125.

The type of the third MOS transistor 1121 is different, and the specific connection manner of the third MOS transistor 1121 and the first component is also different. Exemplarily, in one case, referring to FIG. 9, the third MOS transistor 1121 is a PMOS transistor, the gate of the third MOS transistor 1121 is connected to the input end of the wireless receiving circuit 20, and the drain of the third MOS transistor 1121 is grounded. The source of the third MOS transistor 1121 is connected to one end of the first component 1123, the other end of the first component 1123 is connected to the power supply in the wireless receiving circuit 20, one end of the first capacitor 1122 is grounded, and the other end of the first capacitor 1122 is It is connected to the source of the third MOS transistor 1121. In addition, as shown in FIG. 9, the conversion circuit 112 can also include a low pass filter 1126 that can be used to filter out the AC signal such that the output first signal 30 contains as small an AC component as possible. Illustratively, the low pass filter can include a resistor and a capacitor as shown in FIG.

When the conversion circuit 112 shown in FIG. 9 is employed, the conversion circuit 112 can be used to detect the lower envelope of the AC input signal superimposed on the DC offset 1125 and output the first signal 30 based on the lower envelope. Wherein, the lower envelope of the AC input signal refers to a negative phase envelope signal referenced by a DC offset. The operation timing chart of the first detecting circuit 11 can be seen in FIG. As shown in Fig. 10, the larger the voltage amplitude of the AC input signal, the smaller the voltage value of the first signal 30 output from the conversion circuit 112. When the voltage value of the first signal 30 is less than the reference voltage value, it may be indicated that the voltage amplitude of the AC input signal is greater than the preset value a, the first detecting circuit 11 detects the high power signal, and 111 outputs the first flag signal 60 of the high level. The first flag signal 60 transitions from an initial low level to a high level, that is, there is a rising edge such that a high level first flag signal 60 is generated, and the protection circuit 12 is responsive to the high level state of the first flag signal 60. Enter the protection state to attenuate the voltage amplitude of the AC input signal. When the protection circuit 12 enters the protection state, the voltage amplitude of the input signal 50 is attenuated, the voltage amplitude of the input signal 50 detected by the first detection circuit 11 is less than the preset value a, and the first flag signal 60 is jumped again from the high level. It is low, that is, the first flag signal 60 disappears. It should be noted that, in the embodiment of the present application, the first flag signal 60 is effective as an example. The first flag signal 60 may also be active at a low level, which is not limited in this embodiment.

It should be noted that, since the first detecting circuit 11 detects whether the input signal 50 is a high power signal and requires a certain device reaction time, the first flag signal 60 lags from the low level to the high level transition time t1 (for example, Several ns) appear at time t0 at the high power signal. Similarly, since the circuit requires a certain processing time, the time t2 at which the protection circuit 12 enters the protection state also lags behind the time t1 at which the first flag signal 60 jumps.

Illustratively, in another case, referring to FIG. 11, the third MOS transistor 1121 is an NMOS transistor, the gate of the third MOS transistor 1121 is connected to the input terminal 200 of the wireless receiving circuit 20, and the drain of the third MOS transistor 1121 The pole is connected to the power supply of the wireless receiving circuit 20, the source of the third MOS transistor 1121 is connected to one end of the first element 1123, and the other end of the first element 1123 is grounded.

When the conversion circuit 112 shown in FIG. 11 is employed, the conversion circuit 112 can be used to detect the upper envelope of the AC input signal superimposed on the DC offset 1125 and output the first signal 30 based on the upper envelope. Wherein, the upper envelope of the AC input signal refers to a positive phase envelope signal referenced by a DC offset. The operation timing chart of the first detecting circuit 11 can be seen in FIG. As shown in FIG. 12, the larger the voltage amplitude of the AC input signal, the larger the voltage value of the first signal 30. When the voltage value of the first signal 30 is greater than the reference voltage value, it may be indicated that the voltage amplitude of the AC input signal is greater than the preset value a, the first detecting circuit 11 detects the high power signal, and the comparator 111 outputs the first flag of the high level. Signal 60. The first flag signal 60 triggers the protection circuit 12 to enter a protection state to attenuate the voltage amplitude of the AC input signal. When the protection circuit 12 enters the protection state, the voltage amplitude of the input signal 50 is attenuated, the voltage amplitude of the input signal 50 detected by the first detection circuit 11 is less than the preset value a, and the first flag signal 60 is jumped again from the high level. It is low, that is, the first flag signal 60 disappears.

Further, referring to FIG. 13, the first detecting circuit 11 further includes a reference circuit 113 for outputting a reference signal 40, which is a direct current signal, and the voltage value of the direct current reference signal is a reference voltage value.

Specifically, referring to FIG. 14 or FIG. 15, the reference circuit 113 includes a fourth MOS transistor 1131 and a second component 1132 connected in series, the second component 1132 is a current source or a resistor, and the gate of the fourth MOS transistor 1131 is coupled to a reference point. To receive the original reference voltage, the series junction of the fourth MOS transistor 1131 and the second component 1132 is used to output the reference signal 40.

The third MOS tube 1121 and the fourth MOS tube 1132 have the same size, and the first element 1123 and the second element 1132 have the same size. The third MOS transistor 1121 and the fourth MOS transistor 1132 have the same size, and the third MOS transistor 1121 and the fourth MOS transistor 1132 type, such as NMOS or PMOS, and the conductive channels of the two have the same width and length. When the first element 1123 and the second element 1132 are resistors, the uniform size includes the resistance of the resistor and the physical size of the resistor. In this way, there is a good match in the implementation of the circuit layout, which can reduce the influence of the threshold voltage caused by the process, that is, the change of the voltage at which the MOS transistor starts to operate, on the accuracy of the first detection circuit 11, thereby realizing the recognition of the high-power signal. More accurate judgment.

Illustratively, when the reference circuit 113 is included, the specific structure of the first detecting circuit 111 can be seen in FIG. In some embodiments of the present application, the comparator 111 may be a hysteresis comparator for suppressing the effects of AC input signal fluctuations on the first flag signal 60 (eg, reducing generated noise or glitch, etc.) when the comparator 111 is flipped. Moreover, the DBB 22 can also generate the first flag signal 60 in the first detecting circuit 11, that is, when the comparator 111 is flipped, adjust the reference voltage value, improve the difficulty of flipping again, and realize the function similar to the comparator hysteresis, thereby further reducing When the comparator 111 is turned over, the influence of the fluctuation of the AC input signal on the first flag signal 60 is suppressed.

Further, referring to FIG. 15, the first detecting circuit 11 may further include a delay circuit 114, and the delay circuit 114 may be configured to keep the output first for a preset period of time when the comparator 111 outputs the first flag signal 60. Flag signal 60.

When the first flag signal 60 jumps into a valid signal to cause the protection circuit 12 to enter the protection state, the delay circuit 114 can prevent the first flag signal 60 from jumping to the invalid signal again within a preset period of time, thereby allowing The protection circuit 12 continues to protect the first MOS transistor 21 for a set period of time. During the hold time, even if the input signal 50 is attenuated such that the first flag signal 60 of the comparator 111 disappears, the protection function is not affected.

In one case, the duration of the preset time period corresponding to the delay circuit 114 may be longer, for example, may be 100 microseconds (us), and the delay signal 114 keeps the first flag signal 60 for a preset time. After the segment, the output of the first flag signal 60 is stopped, and the protection circuit 12 exits the protection state. Thereafter, the first detecting circuit 11 can output the first flag signal 60 when the high power input signal 50 is detected again. That is to say, the first detecting circuit 11 can detect whether the input signal 50 is a high power signal according to the length of time delay that the delay circuit 114 can delay. For example, the working timing diagram corresponding to this mode can be seen in FIG. 16. Here, as shown in FIG. 16, since the circuit processing requires a certain time, the time t3 at which the protection circuit 12 exits the protection state lags behind the time t4 at which the first flag signal 60 jumps to the low level.

In some embodiments of the present application, the first detecting circuit 11 is further configured to provide the first flag signal 60 to the DBB 22 in the wireless receiving circuit 20, and the DBB 22 is configured to output the first control signal 70 to the protection circuit 12, the protection circuit 12 maintains a protection state in response to the first control signal 70. In this case, the preset time period corresponding to the delay circuit 114 may be shorter, for example, 10 us.

In this case, the signal for controlling whether the protection circuit 12 is in the protection state includes the first flag signal 60 and the first control signal 70, and when any one of the two signals is valid, the protection circuit 12 remains in the protection state. . Thus, even if the first flag signal 60 is attenuated due to the attenuation of the input signal 50 in the protected state, the first control signal 70 can cause the protection circuit 12 to remain in a protected state. Alternatively, the first flag signal 60 and the first control signal 70 may be coupled to the protection circuit 12 via an OR gate. In this case, the operation timing chart of the overvoltage protection circuit 10 can be seen in FIG. It should be noted that, in the embodiment of the present application, the first control signal 70 is active at a high level as an example. The first control signal may also be active at a low level, which is not specifically limited in this embodiment. Exemplarily, when the first detecting circuit 11 includes the first control signal 70, the signal transmission relationship between the modules can be seen in FIG.

Specifically, referring to FIG. 19, the delay circuit 114 mentioned in the previous embodiment may include a fifth MOS transistor 1143, a first resistor 1141, and a first capacitor 1142. The fifth MOS transistor 1143 is connected in series with the first resistor 1141 at a power source (for example, Between the preset voltage source and ground, the series connection point of the fifth MOS transistor 1143 and the first resistor 1141 is coupled to the first capacitor 1142 and is used to maintain the output of the first flag signal 60 for a preset period of time. In addition, in FIG. 19, IN represents the input terminal of the delay circuit 114, and OUT represents the output terminal of the delay circuit 114. The delay time of the delay circuit 114 is the product of the resistance R of the first resistor 1141 and the capacitance C of the first capacitor 1142.

The first resistor 1141 and the first capacitor 1142 in the delay circuit 114 can be implemented by a MOS transistor. In this way, the influence of process fluctuations on the magnitude of the RC product value can be reduced, thereby improving the delay accuracy of the delay circuit 114. Specifically, when the first resistor 1141 is implemented by the sixth MOS transistor and the first capacitor 1142 is implemented by the seventh MOS transistor, if the resistance of the sixth MOS transistor and the seventh MOS transistor is increased due to the manufacturing process of the MOS transistor or the like. If the value is large, the capacitance values of the sixth MOS transistor and the seventh MOS transistor are decreased, that is, the resistance value R of the first resistor 1141 is increased, and the capacitance C of the first capacitor 1142 is decreased; if the manufacturing process of the MOS transistor is due to reasons, etc. When the resistance values of the sixth MOS transistor and the seventh MOS transistor are reduced, the capacitance values of the sixth MOS transistor and the seventh MOS transistor are increased, that is, the resistance R of the first resistor 1141 is decreased, and the capacitance of the first capacitor 1142 is reduced. The value C increases; thus, the product of RC is substantially constant or the change is small. Alternatively, the first resistor 1141 may be a variable resistor so as to flexibly set the size of R, thereby flexibly setting the length of time delay circuit 114 can be delayed.

In some embodiments of the present application, the DBB 22 is further configured to provide a second control signal 80 to the protection circuit 12 when the voltage amplitude of the input signal 50 is determined to be less than the first predetermined value, and the protection circuit 12 is responsive to the second control signal 80. Exit the protection state. Exemplarily, referring to FIG. 20, the DBB 22 can determine the input signal 50 of the input end of the wireless receiving circuit 20 by receiving signals from the receiving path of the LNA, the mixer, the LPF, the VGA, and the ADC in the wireless receiving circuit 20. Whether the voltage amplitude is smaller than the first preset value; if it is smaller than the first preset value, it can be considered that the signal input from the outside by the wireless receiving circuit 20 is a low power signal. In the case of a low power signal, DBB 22 provides a second control signal 80 to protection circuit 12, which exits the protection state. Wherein, in the protected state, since the input signal 50 is attenuated by the protection circuit 12, when the signal input from the outside by the wireless receiving circuit 20 is a low power signal, the signal received by the DBB 22 from the wireless receiving circuit 20 is small, and thus A preset value can be set smaller, for example smaller than the previously mentioned preset value a.

The operation timing chart of the overvoltage protection circuit 10 shown in FIG. 20 can be seen in FIG. 21. It should be noted that, in the embodiment of the present application, the second control signal 80 is effective as an example. The second control signal 80 can also be active at a high level, which is not limited in the embodiment of the present application. The timing t3 at which the protection circuit 12 exits the protection state lags behind the timing t5 at which the second control signal 80 transitions from a high level to a low level. When the first flag signal 60 is active high, the first control signal 70 is active high, and the second control signal 80 is active low, optionally, the first flag signal 60 and the first control signal 70 And the second control signal 80 can be coupled to the protection circuit 12 via an OR gate.

In some other embodiments of the present application, referring to FIG. 22, the overvoltage protection circuit 10 may further include a second detection circuit 13 for detecting an input signal 50 of the input terminal 200 of the wireless receiving circuit 20 When the voltage amplitude is less than the second predetermined value, the second flag signal 90 is provided to the protection circuit 12, and the protection circuit 12 exits the protection state in response to the second flag signal 90.

When the second detecting circuit 13 detects that the voltage amplitude of the input signal 50 is less than the second preset value, it can be considered that the signal input from the outside by the wireless receiving circuit 20 is a low power signal, and the protection circuit 12 can exit the protection state. It should be noted that, in the protected state, since the input signal 50 is attenuated by the protection circuit 12, when the signal input from the outside by the wireless receiving circuit 20 is a low power signal, the input detected by the second detecting circuit 13 from the input terminal 200 is input. The amplitude of the signal is small, so the second preset value can be set smaller, for example smaller than the previously mentioned preset value a. The second detecting circuit 13 is similar in structure to the first detecting circuit 11, and will not be described in detail herein.

The operation timing diagram of the overvoltage protection circuit shown in FIG. 22 can be seen in FIG. 23. It should be noted that, in the embodiment of the present application, the second flag signal 90 is effective as an example. The second flag signal 90 can also be active at a low level, which is not limited in this embodiment. In FIG. 23, the timing t3 at which the protection circuit 12 exits the protection state lags behind the timing t6 at which the first flag signal transitions from the high level to the low level. When the first flag signal 60 is active high, the first control signal 70 is active high, and the second flag signal 90 is active low, optionally, the first flag signal 60 and the first control signal 70 And the second flag signal 90 can be coupled to the protection circuit 12 via an OR gate.

Further, on the basis of the scenario shown in FIG. 22, the second detecting circuit 13 can also notify the DBB 22 of the second flag signal 90, so that the DBB 22 can know in time that the signal input from the outside by the wireless receiving circuit 20 is a low power signal. . In some other embodiments of the present application, referring to FIG. 24, the overvoltage protection circuit 10 further includes a second detection circuit 13 for detecting the voltage of the input signal 50 of the input terminal 200 of the wireless receiving circuit 20 The second flag signal 90 is provided to the DBB 22 when the amplitude is less than the second preset value, and the second flag signal 90 is used to control the DBB 22 to provide the second control signal 80 to the protection circuit 12, and the protection circuit 12 exits in response to the second control signal 80. Protection status.

The operation timing chart of the overvoltage protection circuit 10 shown in FIG. 24 can be seen in FIG. 25. When the first flag signal 60 and the first control signal 70 are active high, and the second control signal 80 and the second flag signal 90 are active low, optionally, the first flag signal 60, the first control signal 70. The second control signal 80 and the second flag signal 90 can be coupled to the protection circuit 12 via an OR gate.

In addition, in the embodiment of the present application, the first flag signal 60 is also used to control the digital baseband circuit DBB 22 to reduce the gain of the amplifier in the wireless receiving circuit 20. In this way, problems such as signal distortion due to saturation of the amplified signal of the amplifier in the wireless receiving circuit 20 can be prevented. Illustratively, the amplifier in the wireless receiving circuit 20 may include an LNA or VGA or the like.

Another embodiment of the present application further provides a circuit system including the overvoltage protection circuit 10 and the wireless receiving circuit 20 shown in FIGS. Alternatively, the wireless receiving circuit 20 may include one or more of an LNA, a mixer, an LPF, a VGA, an ADC, or a DBB. Alternatively, the circuitry can also be integrated on a chip. For example, the overvoltage protection circuit 10 is specifically configured to protect the first MOS transistor 21 in the LNA in the wireless receiving circuit 20, and the first MOS transistor 21 may be coupled to the input end of the wireless receiving circuit 20, which is the first inside the wireless receiving circuit 20. Transistors.

Through the description of the above embodiments, those skilled in the art can understand that for the convenience and brevity of the description, only the division of the above functional modules is illustrated. In practical applications, the above functions may be assigned differently according to needs. The functional module is completed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

The above content is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It is covered by the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of protection of the claims.

Claims

An overvoltage protection circuit (10) of a first MOS transistor (21) in a wireless receiving circuit (20), characterized by comprising a first detecting circuit (11) and a protection circuit (12);

The first detecting circuit (11) is configured to output a first flag signal (60) according to an input signal (50) and a reference signal (40) of an input end (200) of the wireless receiving circuit (20), the wireless receiving circuit An input end (200) of (20) is coupled to a first MOS transistor (21) included in the wireless circuit (20);

The protection circuit (12) enters a protection state in response to the first flag signal (60) to attenuate a voltage amplitude of the input signal (50).
The overvoltage protection circuit (10) according to claim 1, wherein the first detecting circuit (11) comprises a comparator (111), and the input end of the comparator (111) inputs a first signal respectively (30) and the reference signal (40), the first signal (30) being associated with the input signal (50);

The comparator (111) is configured to output a first flag signal (60) according to a comparison result between a voltage value of the first signal (30) and a reference voltage value of the reference signal (40).
The overvoltage protection circuit (10) according to claim 1 or 2, wherein the protection circuit (12) comprises a second MOS transistor (121), and a gate of the second MOS transistor (121) The output of the first detecting circuit (11) is coupled, and the second MOS transistor (121) is coupled between the input terminal (200) and the ground;

The second MOS transistor (121) is turned on in response to the first flag signal (60) to cause the protection circuit (12) to enter a protection state.
The overvoltage protection circuit (10) according to claim 3, wherein the second MOS transistor (121) is an N-type metal oxide semiconductor NMOS transistor, and a source of the second MOS transistor (121) Grounded, the drain of the second MOS transistor (121) is coupled to the input (200) of the wireless receiving circuit (20).
The overvoltage protection circuit (10) according to claim 3 or 4, wherein the protection circuit (12) further comprises two antiparallel diodes (122), the second MOS transistor (121) The two anti-parallel diodes (122) are coupled to the input (200) of the wireless receiving circuit (20).
The overvoltage protection circuit (10) according to any one of claims 2-5, wherein the input signal (50) of the wireless receiving circuit (20) is an alternating current input signal, and the first detecting circuit ( 11) further comprising a conversion circuit (112) for converting the alternating current input signal into the first signal (30), the first signal (30) being a direct current signal.
The overvoltage protection circuit (10) according to claim 6, wherein said first detecting circuit (11) further comprises a reference circuit (113) for outputting said reference signal (40), the reference signal (40) is a direct current signal.
The overvoltage protection circuit (10) according to claim 7, wherein said conversion circuit (112) comprises a third MOS transistor (1121) and a first component (1123) connected in series, said first component (1123) is a current source or a resistor, a gate of the third MOS transistor (1121) is coupled to the alternating current input signal, and a series connection point of the third MOS transistor (1121) and the first component (1123) is used Outputting the first signal (30);

The reference circuit (113) includes a fourth MOS transistor (1131) and a second component (1132) connected in series, the second component (1132) being a current source or a resistor, and the fourth MOS transistor (1131) a gate is coupled to a reference point, and a series connection point of the fourth MOS transistor (1131) and the second component (1132) is used to output the reference signal (40);

Wherein, the third MOS tube (1121) and the fourth MOS tube (1132) have the same size, and the first element (1123) and the second element (1132) have the same size.
The overvoltage protection circuit (10) according to any one of claims 2-8, characterized in that the first detection circuit (11) further comprises a delay circuit (114), the delay circuit (114) And when the comparator (111) outputs the first flag signal (60), maintaining the first flag signal (60) for a preset period of time.
The overvoltage protection circuit (10) according to claim 9, wherein the delay circuit (114) comprises a fifth MOS transistor (1143), a first resistor (1141), and a first capacitor (1142), The fifth MOS transistor (1143) is connected in series with the first resistor (1141) between the power source and the ground, and the series connection point of the fifth MOS transistor (1143) and the first resistor (1141) is coupled to the The first capacitor (1142) is used to keep outputting the first flag signal (60) for a preset period of time.
The overvoltage protection circuit (10) according to any one of claims 1 to 10, wherein the first detection circuit (11) is further configured to provide the first flag signal (60) to the a digital baseband circuit DBB (22) in the wireless receiving circuit (20);

The DBB (22) is configured to output a first control signal (70) to the protection circuit (12);

The protection circuit (12) maintains the protection state in response to the first control signal (70).
The overvoltage protection circuit (10) according to any one of claims 1-11, wherein the digital baseband circuit DBB (22) in the wireless receiving circuit (20) is further configured to determine the input signal When the voltage amplitude of (50) is less than the first preset value, providing a second control signal (80) to the protection circuit (12);

The protection circuit (12) exits the protection state in response to the second control signal (80).
The overvoltage protection circuit (10) according to any one of claims 1 to 11, characterized in that the overvoltage protection circuit (10) further comprises a second detection circuit (13), the second detection circuit ( 13) for providing a second flag signal (90) to the protection circuit (12) when detecting that the voltage amplitude of the input signal (50) is less than a second predetermined value;

The protection circuit (12) exits the protection state in response to the second flag signal (90).
The overvoltage protection circuit (10) according to any one of claims 1 to 11, characterized in that the overvoltage protection circuit (10) further comprises a second detection circuit (13);

The second detecting circuit (13) is configured to provide a second flag signal (90) to the DBB (22) when detecting that the voltage amplitude of the input signal (50) is less than a second preset value;

The second flag signal (90) is used to control the DBB (22) to provide a second control signal (80) to the protection circuit (12);

The protection circuit (12) exits the protection state in response to the second control signal (80).
The overvoltage protection circuit (10) according to any one of claims 1 to 14, wherein the first flag signal (60) is further used to control the digital baseband circuit DBB (22) to lower the wireless receiving circuit. (20) The gain of the amplifier.
A circuit system comprising the overvoltage protection circuit (10) and the wireless receiving circuit (20) according to any of claims 1-15.
The circuit system according to claim 16, wherein said wireless receiving circuit (20) comprises a low noise amplifier LNA, a mixer, a low pass filter LPF, a variable gain amplifier VGA, an analog to digital converter ADC Or one or more devices in the digital baseband circuit DBB.
A chip characterized by comprising the circuit system of claim 16 or 17.