CN111492580A

CN111492580A - Overvoltage protection circuit of MOS (metal oxide semiconductor) tube in wireless receiving circuit

Info

Publication number: CN111492580A
Application number: CN201880080686.6A
Authority: CN
Inventors: 王红波
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-04-20
Filing date: 2018-04-20
Publication date: 2020-08-04
Also published as: WO2019200612A1

Abstract

The utility model provides an overvoltage crowbar, relates to electron technical field, including first detection circuitry (11) and protection circuit (12), this first detection circuitry (11) are used for exporting first flag signal (60) according to input signal (50) and reference signal (40) of input (200) of wireless receiving circuit (20), input (200) of this wireless receiving circuit (20) and the first MOS pipe (21) that include in this wireless receiving circuit (20) couple, this protection circuit (12) respond to this first flag signal (60) and get into the protection state to attenuate the voltage amplitude of this input signal (50). The overvoltage protection circuit is used for overvoltage protection, can accurately and timely protect the MOS tube under the condition that the MOS tube in the wireless receiving circuit is in overvoltage, and prolongs the service life of the MOS tube.

Description

Overvoltage protection circuit of MOS (metal oxide semiconductor) tube in wireless receiving circuit

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to an overvoltage protection circuit for a metal oxide semiconductor field effect transistor (MOS) in a wireless receiving circuit.

Background

For example, a wireless fidelity (wifi) chip of a mobile phone is close to a transmitting antenna, and an MOS tube at a radio frequency input end of a radio frequency receiving circuit at the forefront of the wifi chip is easily damaged in an overvoltage state.

When a high-power radio-frequency input signal exists outside, if the amplitude of the radio-frequency input signal is greater than the sum of the turn-on voltages of n (positive integers) diodes, the current in the diodes is increased exponentially, the diodes are in a conducting state, and the forward voltage drop of each diode is clamped to the left and right of the conducting voltage.

That is to say, in the prior art, when the amplitude of the radio frequency input signal is greater than the conduction voltage of the n diodes, the overvoltage protection of the MOS transistor at the radio frequency input end is turned on. In fact, due to different manufacturing processes, temperature differences and changes, current differences and changes in diodes, and the like, the value of the diode conduction voltage has certain fluctuation, so that the method for protecting the MOS transistor by using the diode in the prior art cannot accurately and timely provide overvoltage protection for the MOS transistor at the radio frequency input end, and the MOS transistor at the radio frequency input end is easily damaged by overvoltage.

Disclosure of Invention

The embodiment of the application provides an overvoltage protection circuit of an MOS (metal oxide semiconductor) tube in a wireless receiving circuit, which can accurately and timely protect the MOS tube under the condition of overvoltage of the MOS tube in the wireless receiving circuit, and the service life of the MOS tube is prolonged.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in one aspect, the embodiment of the present application provides an overvoltage protection circuit 10 for a first MOS transistor 21 in a wireless receiving circuit 20, which includes a first detection circuit 11 and a protection circuit 12. The first detection circuit 11 is configured to output a first flag signal 60 according to the input signal 50 at the input 200 of the wireless receiving circuit 20 and the reference signal 40, and the input 200 of the wireless receiving circuit 20 is coupled to the first MOS transistor 21 included in the wireless circuit 20. The protection circuit 12 enters a protection state in response to the first flag signal 60 to attenuate the voltage amplitude of the input signal 50.

In this scheme, the first detection circuit 11 can accurately determine whether the input signal 50 is a high-power signal according to the voltage amplitude of the input signal 50 and the voltage amplitude of the reference signal 40, so that the protection circuit 12 is triggered to enter a protection state when the input signal is determined to be the high-power signal, and overvoltage protection for the first MOS transistor 21 is started, the voltage amplitude of the input signal 50 is attenuated, and the service life of the first MOS transistor 21 is prolonged.

In one possible design, the first detection circuit 11 includes a comparator 111, and inputs of the comparator 111 respectively input the first signal 30 and the reference signal 40, and the first signal 30 is related to the input signal 50. The comparator 111 is configured to output the first flag signal 60 according to a comparison result between the voltage value of the first signal 30 and the reference voltage value of the reference signal 40.

In this scheme, the first detection circuit 11 can accurately determine that the signal externally input to the wireless receiving circuit 20 is a high-power signal according to the comparison result between the reference voltage value and the voltage value of the first signal 30 by the comparator 111, so as to timely start the protection of the first MOS transistor 21.

In another possible design, the protection circuit 12 includes a second MOS transistor 121, a gate of the second MOS transistor 121 is coupled to the output terminal of the first detection circuit 11, and the second MOS transistor 121 is coupled between the input terminal 200 and the ground. The second MOS transistor 121 is turned on in response to the first flag signal 60 to cause the protection circuit 12 to enter a protection state.

The second MOS transistor 121 functions as a switch, and can be used to disconnect the input signal 50 when the input signal 50 is a low-power signal and to conduct the input signal 50 when the input signal 50 is a high-power signal.

In another possible design, the second MOS transistor 121 is an N-metal oxide semiconductor (NMOS) transistor, a source of the second MOS transistor 121 is grounded, and a drain of the second MOS transistor 121 is coupled to the input terminal 200 of the wireless receiving circuit 20.

In another possible design, the protection circuit 12 further includes two anti-parallel diodes 122, and the second MOS transistor 121 is coupled to the input end 200 of the wireless receiving circuit 20 through the two anti-parallel diodes 122.

In this scheme, the protection circuit may limit the magnitude of the voltage amplitude of the input signal 50 through the second MOS transistor 121 and the two inverse parallel diodes 122.

In another possible design, the input signal 50 of the wireless receiving circuit 20 is an ac input signal, the first detecting circuit 11 further includes a converting circuit 112, the converting circuit 112 is configured to convert the ac input signal into the first signal 30, and the first signal 30 is a dc signal.

In another possible design, the first detection circuit 11 further includes a reference circuit 113, where the reference circuit 113 is configured to output a reference signal 40, and the reference signal 40 is a dc signal.

In another possible design, the converting circuit 112 includes a third MOS tube 1121 and a first element 1123 connected in series, the first element 1123 is a current source or a resistor, a gate of the third MOS tube 1121 is coupled to an ac input signal, and a series connection point of the third MOS tube 1121 and the first element 1123 is used for outputting the first signal 30.

In another possible design, the reference circuit 113 includes a series connection of a fourth MOS transistor 1131 and a second element 1132, the second element 1132 is a current source or a resistor, a gate of the fourth MOS transistor 1131 is coupled to a reference point, and a series connection point of the fourth MOS transistor 1131 and the second element 1132 is used for outputting the reference signal 40.

In another possible design, the third MOS tube 1121 is the same size as the fourth MOS tube 1132, and the first element 1123 is the same size as the second element 1132.

In the scheme, better matching is achieved when the circuit layout is realized, so that the influence of the threshold voltage caused by the process, namely the change of the voltage at which the MOS tube starts to work, on the precision of the first detection circuit 11 can be reduced, and more accurate judgment on the identification of high-power signals is realized.

In another possible design, the first detection circuit 11 further includes a delay circuit 114, and the delay circuit 114 is configured to keep outputting the first flag signal 60 for a preset time period when the comparator 111 outputs the first flag signal 60.

In this scheme, after the first flag signal 60 transitions to the active signal to enable the protection circuit 12 to enter the protection state, the delay circuit 114 may prevent the first flag signal 60 from transitioning to the inactive signal again within a preset time period, so that the protection circuit 12 may continuously protect the first MOS transistor 21 within the preset time period.

In another possible design, the delay circuit 114 includes a fifth MOS tube 1143, a first resistor 1141 and a first capacitor 1142, the fifth MOS tube 1143 and the first resistor 1141 are connected in series between the power supply and the ground, and a series connection point of the fifth MOS tube 1143 and the first resistor 1141 is coupled to the first capacitor 1142 and configured to keep outputting the first flag signal 60 for a preset time period.

In another possible design, the first resistor 1141 and the first capacitor 1142 are implemented by MOS transistors, respectively.

In this scheme, the first resistor 1141 and the first capacitor 1142 are implemented by MOS transistors, so that the influence of process fluctuation on the magnitude of the RC product value can be reduced, and the delay accuracy of the delay circuit 114 is improved.

In another possible design, the first detection circuit 11 is further configured to provide the first flag signal 60 to a digital baseband (DBB) circuit 22 in the wireless receiving circuit 20. The DBB 22 is used to output a first control signal 70 to the protection circuit 12. The protection circuit 12 maintains a protection state in response to the first control signal 70.

In this scheme, the first control signal 70 may cause the protection circuit 12 to maintain the protection state even if the first flag signal 60 transitions to an invalid signal due to the input signal 50 being attenuated in the protection state.

In another possible design, the digital baseband circuit DBB 22 in the wireless receiving circuit 20 is further configured to provide the second control signal 80 to the protection circuit 12 when the voltage amplitude of the input signal 50 is determined to be less than the first preset value, and the protection circuit 12 exits the protection state in response to the second control signal 80.

In this scenario, the DBB 22 may trigger the protection circuit 12 to exit the protection state when it determines that the signal input outside the wireless receiving circuit 20 is a low-power signal.

In another possible design, the overvoltage protection circuit 10 further includes a second detection circuit 13, the second detection circuit 13 is configured to provide a second flag signal 90 to the protection circuit 12 when detecting that the voltage amplitude of the input signal 50 is smaller than a second preset value, and the protection circuit 12 exits the protection state in response to the second flag signal 90.

In this scheme, the second detection circuit 13 may trigger the protection circuit 12 to exit the protection state when determining that the signal externally input to the wireless receiving circuit 20 is a low-power signal.

In another possible design, the overvoltage protection circuit 10 further includes a second detection circuit 13, the second detection circuit 13 is configured to provide a second flag signal 90 to the DBB 22 when detecting that the voltage amplitude of the input signal 50 is smaller than a second preset value, the second flag signal 90 is configured to control the DBB 22 to provide a second control signal 80 to the protection circuit 12, and the protection circuit 12 exits the protection state in response to the second control signal 80.

In this scheme, the second detection circuit 13 may trigger the DBB 22 to provide the second control signal 80 to the protection circuit 12 when determining that the signal externally input to the wireless receiving circuit 20 is a low-power signal, thereby triggering the protection circuit 12 to exit the protection state.

In another possible design, first flag signal 60 is also used to control digital baseband circuit DBB 22 to reduce the gain of the amplifiers in wireless receive circuitry 20.

In this way, it is possible to prevent the problem of signal distortion or the like due to saturation of the signal amplified by the amplifier in the wireless receiving circuit 20.

In another aspect, embodiments of the present application provide a circuit system including the overvoltage protection circuit 10 and the wireless receiving circuit 20 in any possible design of the above aspects.

In one possible design, wireless receiving circuitry 20 includes one or more devices in a low noise amplifier, a mixer, a low pass filter, a variable gain amplifier, an analog-to-digital converter, or a digital baseband circuit.

In another aspect, embodiments of the present application provide a chip including circuitry in any possible design according to the above aspects of the present application.

Drawings

Fig. 1 is a schematic structural diagram of a mobile phone according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a receiving module according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit structure diagram according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

fig. 5 is a schematic diagram of another circuit structure provided in the embodiment of the present application;

fig. 6 is a schematic diagram of another circuit structure provided in the embodiment of the present application;

fig. 7 is a schematic diagram of another circuit structure provided in the embodiment of the present application;

fig. 8 is a schematic diagram of another circuit structure provided in the embodiment of the present application;

fig. 9 is a schematic diagram of another circuit structure provided in the embodiment of the present application;

FIG. 10 is a timing diagram of signals provided by an embodiment of the present application;

fig. 11 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

FIG. 12 is a timing diagram of another embodiment of the present invention;

fig. 13 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

fig. 14 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

fig. 15 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

FIG. 16 is a timing diagram of another embodiment of the present invention;

fig. 17 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

FIG. 18 is a timing diagram of another embodiment of the present invention;

fig. 19 is a schematic structural diagram of a delay circuit according to an embodiment of the present application;

fig. 20 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

FIG. 21 is a timing diagram of another embodiment of the present invention;

fig. 22 is a schematic structural diagram of another circuit provided in the embodiment of the present application;

FIG. 23 is a timing diagram of another embodiment of the present application;

FIG. 24 is a schematic diagram of another circuit configuration provided in an embodiment of the present application;

fig. 25 is another signal timing diagram provided in the present embodiment.

Detailed Description

For ease of understanding, examples are given in part to illustrate concepts related to embodiments of the present application. As follows:

and a MOS tube port: including 4 ports for gate, source, drain and substrate.

An overvoltage condition: when the voltage drop (for example, the voltage drop between the gate and the source, the voltage drop between the gate and the drain, etc.) between the ports of the MOS transistor is greater than the operating voltage, the MOS transistor is in the state.

Clamping: the potential at a certain point is limited to a prescribed potential.

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Wherein in the description of the embodiments of the present application, "/" indicates an OR meaning unless otherwise specified, for example, A/B may indicate A or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality" means two or more than two.

The overvoltage protection circuit provided by the embodiment of the application can be used for a wireless receiving circuit of electronic equipment in a wireless communication system, and can prevent a first MOS tube connected with the input end of the wireless receiving circuit from being damaged due to overvoltage when the wireless receiving circuit receives a high-power signal.

For example, the wireless communication system may be wifi, Wideband Code Division Multiple Access (WCDMA), time division synchronous code division multiple access (TD-SCDMA), time division synchronous code division multiple access (L TE), Near Field Communication (NFC), new air interface (NR), or bluetooth system.

The electronic device may be any device or chip capable of receiving a wireless signal, such as a mobile phone, a tablet computer, a wearable device, an in-vehicle device, an Augmented Reality (AR)/Virtual Reality (VR) device, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a Personal Digital Assistant (PDA), and the like, which is not limited in this embodiment.

Taking the electronic device in the embodiment of the present application as an example of a mobile phone, a general hardware architecture of the mobile phone is described. As shown in fig. 1, the mobile phone 001 may include: the display 01, the processor 02, the memory 03, the wireless communication module 04, a Radio Frequency (RF) circuit 05, the gravity sensor 06, the audio circuit 07, the speaker 08, the microphone 09, and the like may be connected by a bus or may be directly connected. Those skilled in the art will appreciate that the handset configuration shown in fig. 1 is not intended to be limiting, and that the handset may include more components than those shown, or combine some of the components in the figures, or have a different arrangement of components.

Specifically, the display 01 may include a display panel 011 and a touch panel 012, the display panel 011 may be configured in the form of a liquid crystal display (L CD), an organic light-emitting diode (O L ED), and the like, the touch panel 012, which may also be referred to as a touch screen, a touch-sensitive screen, a touch screen, and the like, may collect a contact or non-contact operation by a user on or near the touch panel 012 (e.g., an operation by a user on or near the touch panel 012 using any suitable object or accessory such as a finger, a stylus, and the like), and drive a corresponding connection device according to a preset program.

Further, the touch panel 012 may cover the display panel 011, and a user may operate on or near the touch panel 012 covered on the display panel 011 according to the contents displayed on the display panel 011 (the displayed contents include any one or a combination of a soft keyboard, a virtual mouse, virtual keys, icons, and the like). After the touch panel 012 detects an operation thereon or nearby, it is transmitted to the processor 02 through the input/output subsystem to determine a user input, and then the processor 02 provides a corresponding visual output on the display panel 011 through the input/output subsystem according to the user input. Although the touch panel 012 and the display panel 011 are shown in fig. 1 as two separate components to implement the input and output functions of the mobile phone, in some embodiments, the touch panel 012 and the display panel 011 can be integrated to implement the input and output functions of the mobile phone.

The processor 02 is a control center of the mobile phone 001, connects various parts of the entire mobile phone by using various interfaces and lines, and executes various functions of the mobile phone 001 and processes data by operating or executing software programs and/or modules stored in the memory 03 and calling data stored in the memory 03, thereby integrally monitoring the mobile phone 001. In particular implementations, processor 02 may include one or more processing units, as one embodiment; the processor 02 may integrate an application processor and a modem processor. The application processor mainly processes an operating system, a user interface, applications and the like, and the modem processor mainly processes wireless communication. It will be appreciated that the modem processor described above may not be integrated into the processor 02.

The memory 03 may be used for storing data, software programs and modules, and may be a volatile memory (volatile memory), such as a random-access memory (RAM); or a non-volatile memory (non-volatile memory), such as a read-only memory (ROM), a flash memory (flash memory), a Hard Disk Drive (HDD) or a solid-state drive (SSD); or a combination of the above types of memories.

The wireless communication module 04 may include one or more of a wifi chip, a bluetooth module, an NFC module, or a General Packet Radio Service (GPRS) module, and may be configured to communicate or talk with other devices through a wireless communication technology.

The RF circuit 05 may include a transmitting module 051 and a receiving module 052, the transmitting module 051 may be used to transmit information during communication or conversation, the receiving module 052 may be used to receive information during communication or conversation, and to process the received information to the processor 02. generally, the RF circuit 05 specifically includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (L NA), a duplexer, etc. referring to fig. 2, the receiving module 052 may include L NA521, a mixer 522, a low pass filter (L PF)523, a Variable Gain Amplifier (VGA) 524, an analog to digital converter (ADC) 525, and a DBB 526. a radio frequency input signal received by the receiving module 52 is amplified by L NA, down-converted to a signal containing an intermediate frequency signal component or a baseband signal component by the mixer, the signal or baseband signal component is processed by the ADC, and the signal is processed by the receiving module 052, where the signal may be received by the receiving module 052 or the receiving module 052, where the signal may be processed by the receiving module 052, or by the receiving module.

The gravity sensor 06 can detect the acceleration of the mobile phone in each direction (generally three axes), detect the gravity and direction when the mobile phone is stationary, and can be used for applications of recognizing the posture of the mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like. It should be noted that the mobile phone 001 may further include other sensors, such as a pressure sensor, an optical sensor, a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor, and so on, which are not described herein again.

The audio circuit 07, speaker 08, microphone 09 can provide an audio interface between the user and the handset 001.

Although not shown, the mobile phone 001 may further include a camera, a power supply, and other functional modules, which are not described in detail herein.

The overvoltage protection circuit can be arranged in the wifi chip of the mobile phone and used for protecting a first MOS tube connected with an L NA input end in the wifi chip receiving circuit.

The overvoltage protection circuit of a MOS transistor in a wireless receiving circuit provided by the embodiment of the present application will be described in detail through specific embodiments.

The embodiment of the application provides an overvoltage crowbar, can be used for protecting the MOS pipe of wireless signal receiving circuit input, prevents that the MOS pipe of receiving circuit input from because the excessive pressure from damaging. Referring to fig. 3, the overvoltage protection circuit 10 may include a first detection circuit 11 and a protection circuit 12. Wherein the first detection circuit 11 is operable to output a first flag signal 60 based on the input signal 50 at the input 200 of the wireless receiving circuit 20 and the reference signal 40. Wherein, the input terminal 200 of the wireless receiving circuit 20 is coupled with the first MOS transistor 21 included in the wireless circuit 20. For example, the first MOS transistor 21 is a first MOS transistor in the radio receiver circuit 20 for receiving signals, that is, no other MOS transistor is coupled between the input end 200 of the radio receiver circuit 20 and the first MOS transistor 21. The protection circuit 12 enters a protection state in response to the first flag signal 60 to attenuate the voltage amplitude of the input signal 50. Wherein the first detection circuit 11 outputs the first flag signal 60 to trigger the attenuation when the input signal 50 reaches or exceeds the reference signal 40.

It should be noted that in the embodiments of the present application, the coupling means direct connection or connection through other devices, and exemplarily represents an electrical connection relationship. For example, the coupling of the input end 200 of the wireless receiving circuit 20 and the first MOS transistor 21 may include: the input end 200 is directly connected with the first MOS tube 21; alternatively, the input terminal 200 is indirectly connected to the first MOS transistor 21 through some capacitance or resistance device.

In addition, in fig. 3, the wireless receiving circuit 20 may further include a module 24 and a module 25, where the module 24 is coupled to the first port of the first MOS transistor 21 and is configured to provide a dc bias to drive the first MOS transistor 21 to operate, the second port of the first MOS transistor 21 is coupled to ground, and the third port of the first MOS transistor 21 is connected to another part of the wireless receiving circuit 20, that is, the module 25, so as to implement a receiving function of the wireless receiving circuit 20 in combination with the other part, and the module 25 may cooperate with the first MOS transistor 21 to form at least a part of L NA 521.

It should be understood that fig. 3 illustrates the first MOS transistor 21 as an NMOS transistor, but the first MOS transistor 21 may also be a P-channel metal oxide semiconductor (PMOS) transistor instead of the NMOS transistor, and the type of the first MOS transistor 21 is not limited in the embodiment of the present application.

Specifically, the first detection circuit 11 may monitor the voltage amplitude of the input signal 50 at the input end 200 of the wireless receiving circuit 20 in real time. When the first detection circuit 11 accurately determines that the voltage amplitude of the input signal 50 at the input end 200 of the wireless receiving circuit 20 reaches or exceeds the preset value a, that is, the amplitude corresponding to the reference signal, according to the voltage amplitude of the reference signal 40 and the voltage amplitude of the input signal 50, it can be said that the input signal 50 is a high-power signal, that is, the signal input by the wireless receiving circuit 20 from the outside is a high-power signal, the first detection circuit 11 can output the first flag signal 60 to the protection circuit 12, and the protection circuit 12 enters a protection state in response to the first flag signal 60 output by the first detection circuit 11, so as to start overvoltage protection on the MOS transistor at the input port of the wireless receiving circuit 20, and attenuate the voltage amplitude of the input signal 50, so as to prevent the MOS transistor from being damaged due to overvoltage. The preset value a can be set according to actual needs.

Because the conduction voltage of the diode is dynamically fluctuated and the fluctuation range is large, compared with the prior art that the overvoltage protection of the MOS transistor is started simply by the fact that the amplitude of the input signal 50 is larger than the conduction voltage of a simple device such as a single diode or a plurality of diodes, the first detection circuit 11 in the embodiment of the present application can accurately determine whether the input signal 50 is a high-power signal according to the voltage amplitude of the input signal 50 and the voltage amplitude of the reference signal 40, so that the protection circuit 12 is triggered to enter a protection state when the input signal is determined to be the high-power signal, and the overvoltage protection of the first MOS transistor 21 is started, the voltage amplitude of the input signal 50 is attenuated, and the service life of the first MOS transistor 21 is prolonged.

In some embodiments of the present application, referring to fig. 4, the first detection circuit 11 includes a comparator 111, and the input terminals 1110 of the comparator 111 respectively input the first signal 30 and the reference signal 40, and the first signal 30 is related to the input signal 50. Alternatively, the first signal 30 is indicative of the voltage amplitude of the input signal 50. The comparator 111 is configured to output the first flag signal 60 according to a comparison result between the voltage value of the first signal 30 and the reference voltage value of the reference signal 40.

In one case, the voltage value of the first signal 30 may be positively correlated with the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, i.e., the larger the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, the larger the voltage value of the first signal 30. Alternatively, in another case, the voltage value of the first signal 30 may also be inversely related to the voltage amplitude of the input signal 50 of the wireless receiving circuit 20, that is, the voltage value of the first signal 30 is smaller when the voltage amplitude of the input signal 50 of the wireless receiving circuit 20 is larger. In the case of positive correlation and negative correlation, the reference voltage value of the reference signal 40 can be set to different values, and the inversion condition of the comparator 111 is different, and the output signal is also different. The voltage amplitude of the input signal 50 can be understood as a parameter used to describe the amplitude, such as a peak-to-peak value or an effective value of the input signal 50.

Specifically, the first detection circuit 11 may determine whether the voltage amplitude of the input signal 50 exceeds the preset value a through the comparison result of the comparator 111 between the reference voltage value and the voltage value of the first signal 30. When the voltage amplitude of the input signal 50 exceeds the preset value a, it can be said that the input signal 50 is a high-power signal, that is, the signal input outside the wireless receiving circuit 20 is a high-power signal, the first detection circuit 11 can output the first flag signal 60 to the protection circuit 12 through the comparator 111, thereby triggering the protection circuit 12 to enter a protection state in time, starting overvoltage protection on the first MOS transistor 21, and attenuating the voltage amplitude of the input signal 50 to prevent the MOS transistor from being damaged due to overvoltage.

In addition, the wireless receiving circuit 20 may further include a DBB 22, and the DBB 22 may be used to set a reference voltage value of the reference signal 40. That is, the reference voltage value can be precisely configured (e.g., register configuration or digital configuration) by the DBB 22, and the configured reference voltage value can be kept stable and substantially not fluctuated, so that the first detection circuit 11 can accurately determine whether the amplitude of the input signal 50 is greater than the preset value a, that is, whether the signal externally input to the wireless receiving circuit 20 is a high-power signal, according to the accurate reference voltage value, the voltage amplitude of the input signal 50, and the comparator 111. When the reference voltage value needs to be changed, the reference voltage value can be changed through the DBB 22 by adopting a software upgrading mode and the like. Illustratively, the DBB 22 may be the DBB 526 of FIG. 2.

The DBB 22 may flexibly set a specific value of the reference voltage value according to actual needs, for example, the reference voltage value may be any value such as 0.8V, 0.81V, or 0.75V. In the prior art, when the amplitude of the input signal 50 is greater than the sum of the n diode conduction voltages, the overvoltage protection of the MOS transistor is turned on, and the sum of the n diode conduction voltages may be considered as an integral multiple of the conduction voltage of a single diode, and is a discrete value, for example, when the conduction voltage is 0.7V, the sum of the n diode conduction voltages may be a value such as 0.7V, 1.4V, or 2.1V, and the span between adjacent values is large, and when the operating voltage of the first MOS transistor 21 in the normal operating state is between two adjacent values, for example, the operating voltage is 1.1V, if the single diode is used to protect the MOS transistor, the single diode clamps the inter-port voltage of the first MOS transistor 21 at about 0.7V, and has a large difference from the operating voltage of the first MOS transistor 21, which easily affects the normal operation of the first MOS transistor 21; if the first MOS transistor 21 is protected by using two diodes, the voltage between the ports of the first MOS transistor 21 is clamped at 1.4V by the two diodes, which is much different from the operating voltage of the first MOS transistor 21, and the first MOS transistor 21 is easily damaged by overvoltage. Compared with the prior art, the embodiment of the invention is beneficial to improving the design flexibility.

It should be noted that the working voltage of the first MOS transistor 21 is a parameter value provided when the first MOS transistor 21 leaves a factory, and when the voltage difference between different ports of the first MOS transistor 21 is smaller than the working voltage, the first MOS transistor 21 can work normally; when the voltage difference between different ports of the first MOS transistor 21 is greater than the operating voltage, the first MOS transistor 21 is in an overvoltage state, and the performance and the like of the first MOS transistor 21 are affected.

For example, referring to fig. 5, the wireless receiving circuit 20 may specifically be the receiving module 052 shown in fig. 2, and the first MOS transistor 21 in the wireless receiving circuit 20 is located in the device L NA coupled to the input terminal 200 and is an MOS transistor at the input terminal L NA the DBB 22 in the wireless receiving circuit 20 may be used to configure the reference voltage value of the reference signal 40.

In addition, as the process size (nm) of a Complementary Metal Oxide Semiconductor (CMOS) process adopted by the rf chip is gradually decreased, the gate oxide layer is thinner and thinner, and the operating voltage and breakdown voltage of the MOS transistor are also gradually decreased. For the MOS transistor using advanced process (such as 28nm, 16nm, etc.), the gate oxide layer is thinner, the voltage resistance of the MOS transistor is lower and lower, and the MOS transistor may be damaged due to overvoltage caused by the small fluctuation of the diode on-voltage. And with the reduction of the voltage resistance of the MOS tube, the voltage on the MOS tube cannot be limited within a safe range by only diode protection, and when a high-power radio-frequency signal is input, the maximum overvoltage born by the MOS tube exceeds the normal working voltage more, so that the MOS tube is easier to damage. For example, when the operating voltage of the first MOS transistor 21 is 0.5V, the protection using a single diode can only limit the voltage between the ports of the first MOS transistor 21 to about the on-voltage, the on-voltage of the diode is higher than the operating voltage by 0.5V, and the first MOS transistor 21 is easily in an overvoltage state. In addition, since there is a ripple, if the on voltage of the diode is 0.9V, 0.9V is much higher than 0.5V, and the first MOS transistor 21 is easily damaged by overvoltage. In the embodiment of the present application, the specific value of the reference voltage value can be flexibly set according to actual needs, so that even if the working voltage of the first MOS transistor 21 is less than the conduction voltage of a single diode by 0.7V, the protection circuit 12 can be accurately and timely turned on to protect the first MOS transistor 21.

In the embodiment of the present application, the protection circuit 12 includes a second MOS transistor 121, a gate of the second MOS transistor 121 is coupled to the output terminal of the first detection circuit 11, and the second MOS transistor 121 is coupled between the input terminal 200 and the ground. The second MOS transistor 121 is turned on in response to the first flag signal 60 to cause the protection circuit 12 to enter a protection state. Referring to fig. 6, the second MOS transistor 121 may specifically be an NMOS transistor, a source of the second MOS transistor 121 is grounded, and a drain of the second MOS transistor 121 is coupled to the input end 200 of the wireless receiving circuit 20. The second MOS transistor 121 functions as a switch, and can be used to disconnect when the input signal 50 is a low power signal and to conduct when the input signal 50 is a high power signal.

Specifically, in the protection circuit 12 shown in fig. 6, when the input signal 50 is a high-power signal, the first detection circuit 11 outputs the first flag signal 60, and the second MOS transistor 121 is turned on. The second MOS transistor 121 after being turned on is equivalent to a resistor with a small resistance value (e.g., 10 Ω), so that the amplitude of the high-power signal at the input end 200 of the wireless receiving circuit 20 can be attenuated to a small value, and the second MOS transistor 121 does not substantially affect the normal receiving performance of the first MOS transistor 21. When the input signal 50 is a low-power signal, the first detection circuit 11 does not output the first flag signal 60, that is, the voltage of the output first flag signal 60 changes, the second MOS transistor 121 is not turned on, and the second MOS transistor 121 at this time is equivalent to a resistor with a large resistance value (for example, several tens of M Ω), and it can be considered that the protection circuit 12 is disconnected from the wireless receiving circuit 20 at this time, and the second MOS transistor 121 does not substantially affect the normal receiving performance of the wireless receiving circuit 20.

Further, referring to fig. 7, the protection circuit 12 may further include two anti-parallel diodes 122, and the second MOS transistor 121 is coupled to the input end 200 of the wireless receiving circuit 20 through the two anti-parallel diodes 122. The reverse parallel diode 122 includes a first diode and a second diode, wherein the anode of the first diode is connected to the cathode of the second diode, and the cathode of the first diode is connected to the anode of the second diode.

In the protection circuit 12 shown in fig. 7, when the input signal 50 is a high-power signal, the first detection circuit 11 outputs the first flag signal 60, the second MOS transistor 121 is turned on, and the inverse parallel diode 122 is used to clamp the voltage at the input end 200 of the wireless receiving circuit 20 to the on-voltage of the diode, so as to prevent the first MOS transistor 21 from being damaged due to overvoltage, and the second MOS transistor 121 does not substantially affect the normal receiving performance of the wireless receiving circuit 20. When the input signal 50 is a low-power signal, the first detection circuit 11 does not output the first flag signal 60, the second MOS transistor 121 is not turned on, and the second MOS transistor 121 is equivalent to a resistor with a large resistance value (for example, several tens of M Ω), and it can be considered that the anti-parallel diode 122 is disconnected from the wireless receiving circuit 20, and the diode may affect the normal receiving performance of the wireless receiving circuit 20.

That is, in the overvoltage protection circuit 10 provided in the embodiment of the present application, if the protection circuit 12 shown in fig. 6 is used, the protection circuit 12 does not substantially affect the normal receiving performance of the wireless receiving circuit 20 whether the input signal 50 is a high-power signal or a low-power signal; with the protection circuit 12 shown in fig. 7, the diode 122 connected in parallel in the protection circuit 12 will have an effect on the normal receiving performance of the wireless receiving circuit 20 only when the input signal 50 is a high-power signal, and the diode in the protection circuit 12 will have substantially no effect on the normal receiving performance of the wireless receiving circuit 20 when the input signal 50 is a low-power signal. In the prior art, whether the input signal 50 is a high-power signal or a low-power signal, the diode for protection affects the normal receiving performance of the wireless receiving circuit 20.

In the embodiment of the present application, the input signal 50 of the wireless receiving circuit 20 is a wireless ac input signal, for example, when the wireless receiving circuit 20 is a wireless receiving circuit 20 in a wifi chip of a mobile phone and the first MOS transistor 21 is a MOS transistor at the L NA input end of the wireless receiving circuit 20, the ac input signal is a radio frequency ac input signal, referring to fig. 8, the first detecting circuit 11 includes a converting circuit 112, which can be used to convert the ac input signal into a first signal 30, and the first signal 30 is a dc signal.

Specifically, referring to fig. 9 or fig. 11, the conversion circuit 112 may include a third MOS tube 1121 and a first element 1123 connected in series, where the first element 1123 is a current source or a resistor, a gate of the third MOS tube 1121 is coupled to an ac input signal, and a series connection point of the third MOS tube 1121 and the first element 1123 is used for outputting the first signal 30. The gate of the third MOS tube 1121 is provided with a dc offset 1125, and the dc offset 1125 is used for superimposing an ac input signal at the input terminal of the radio receiver circuit 20 on the dc offset 1125. The DBB 22 may specifically be configured to set a reference voltage value according to the operating voltage of the first MOS transistor 21 and the dc bias 1125.

The type of the third MOS tube 1121 is different, and the specific connection manner of the third MOS tube 1121 and the first element is also different. Illustratively, referring to fig. 9, the third MOS tube 1121 is a PMOS tube, a gate of the third MOS tube 1121 is connected to the input terminal of the wireless receiving circuit 20, a drain of the third MOS tube 1121 is grounded, a source of the third MOS tube 1121 is connected to one end of the first element 1123, the other end of the first element 1123 is connected to the power supply in the wireless receiving circuit 20, one end of the first capacitor 1122 is grounded, and the other end of the first capacitor 1122 is connected to the source of the third MOS tube 1121. Furthermore, as shown in fig. 9, the conversion circuit 112 may further include a low-pass filter 1126, and the low-pass filter 1126 may be configured to filter the ac signal so that the output first signal 30 contains as little ac component as possible. Illustratively, the low pass filter may include a resistor and a capacitor as shown in FIG. 9.

When the conversion circuit 112 shown in fig. 9 is employed, the conversion circuit 112 may be configured to detect a lower envelope of the ac input signal superimposed on the dc offset 1125 and output the first signal 30 according to the lower envelope. The lower envelope of the ac input signal is a negative-phase envelope signal with reference to a dc bias. The operation timing diagram of the first detection circuit 11 can be seen in fig. 10. As shown in fig. 10, the larger the voltage amplitude of the ac input signal, the smaller the voltage value of the first signal 30 output by the conversion circuit 112. When the voltage value of the first signal 30 is smaller than the reference voltage value, which may indicate that the voltage amplitude of the ac input signal is greater than the preset value a, the first detection circuit 11 detects the high-power signal, 111 outputs the first flag signal 60 with a high level, the first flag signal 60 jumps from an initial low level to a high level, that is, there is a rising edge such that the first flag signal 60 with a high level is generated, and the protection circuit 12 enters a protection state in response to the high level state of the first flag signal 60 to attenuate the voltage amplitude of the ac input signal. When the protection circuit 12 enters the protection state, the voltage amplitude of the input signal 50 is attenuated, the voltage amplitude of the input signal 50 detected by the first detection circuit 11 is smaller than the preset value a, and the first flag signal 60 jumps from the high level to the low level again, that is, the first flag signal 60 disappears. It should be noted that, in the embodiment of the present application, the first flag signal 60 is active at a high level, and the first flag signal 60 may also be active at a low level, which is not limited in the embodiment of the present application.

It should be noted that, since the first detection circuit 11 needs a certain device response time to detect whether the input signal 50 is a high-power signal, the transition time t1 from low level to high level of the first flag signal 60 lags (for example, several ns) behind the occurrence time t0 of the high-power signal. Similarly, since the circuit requires a certain processing time, the time t2 at which the protection circuit 12 enters the protection state also lags behind the time t1 at which the first flag signal 60 transitions.

Illustratively, in another case, referring to fig. 11, the third MOS tube 1121 is an NMOS tube, a gate of the third MOS tube 1121 is connected to the input terminal 200 of the wireless receiving circuit 20, a drain of the third MOS tube 1121 is connected to a power supply of the wireless receiving circuit 20, a source of the third MOS tube 1121 is connected to one end of the first element 1123, and the other end of the first element 1123 is grounded.

When the conversion circuit 112 shown in fig. 11 is employed, the conversion circuit 112 may be configured to detect an upper envelope of the ac input signal superimposed on the dc bias 1125 and output the first signal 30 according to the upper envelope. The upper envelope of the ac input signal refers to a positive-phase envelope signal with a dc offset as a reference. The operation timing diagram of the first detection circuit 11 can be seen in fig. 12. As shown in fig. 12, the larger the voltage amplitude of the ac input signal, the larger the voltage value of the first signal 30. When the voltage value of the first signal 30 is greater than the reference voltage value, it can be shown that the voltage amplitude of the ac input signal is greater than the preset value a, the first detection circuit 11 detects a high power signal, and the comparator 111 outputs the first flag signal 60 with a high level. The first flag signal 60 triggers the protection circuit 12 to enter a protection state to attenuate the voltage amplitude of the ac input signal. When the protection circuit 12 enters the protection state, the voltage amplitude of the input signal 50 is attenuated, the voltage amplitude of the input signal 50 detected by the first detection circuit 11 is smaller than the preset value a, and the first flag signal 60 jumps from the high level to the low level again, that is, the first flag signal 60 disappears.

Further, referring to fig. 13, the first detection circuit 11 further includes a reference circuit 113, the reference circuit 113 is configured to output a reference signal 40, the reference signal 40 is a dc signal, and a voltage value of the dc reference signal is a reference voltage value.

Specifically, referring to fig. 14 or fig. 15, the reference circuit 113 includes a fourth MOS transistor 1131 and a second element 1132 connected in series, the second element 1132 is a current source or a resistor, a gate of the fourth MOS transistor 1131 is coupled to a reference point to receive an original reference voltage, and a series connection point of the fourth MOS transistor 1131 and the second element 1132 is used for outputting the reference signal 40.

The third MOS tube 1121 is the same as the fourth MOS tube 1132 in size, and the first element 1123 is the same as the second element 1132 in size. The sizes of the third MOS tube 1121 and the fourth MOS tube 1132 are the same, including the types of the third MOS tube 1121 and the fourth MOS tube 1132, such as NMOS or PMOS, and the widths and lengths of the conductive channels of the two are the same. When the first element 1123 and the second element 1132 are resistors, the consistent size includes a resistance value of the resistor and a physical size of the resistor being consistent. Therefore, the circuit layout can be well matched when being realized, so that the influence of the threshold voltage caused by the process, namely the change of the voltage at which the MOS tube starts to work, on the precision of the first detection circuit 11 can be reduced, and the identification of high-power signals is more accurately judged.

Illustratively, when the reference circuit 113 is included, the specific structure of the first detection circuit 111 may be referred to fig. 14. In some embodiments of the present application, the comparator 111 may be a hysteresis comparator for suppressing the influence of the ac input signal fluctuation on the first flag signal 60 (e.g., reducing the generated noise or glitch, etc.) when the comparator 111 flips. In addition, the DBB 22 may also adjust the reference voltage value when the first detection circuit 11 generates the first flag signal 60, that is, when the comparator 111 is flipped, to improve the difficulty of flipping again, and implement a function similar to comparator hysteresis, so as to further reduce the influence of the ac input signal fluctuation on the first flag signal 60 when the comparator 111 is flipped.

Further, referring to fig. 15, the first detection circuit 11 may further include a delay circuit 114, and the delay circuit 114 may be configured to keep outputting the first flag signal 60 for a preset time period when the comparator 111 outputs the first flag signal 60.

After the first flag signal 60 transitions to the active signal to enable the protection circuit 12 to enter the protection state, the delay circuit 114 may prevent the first flag signal 60 from transitioning to the inactive signal again within a preset time period, so that the protection circuit 12 may continuously protect the first MOS transistor 21 within the preset time period. During the hold time, the protection function is not affected even if the first flag signal 60 of the comparator 111 disappears because the input signal 50 is attenuated.

In one case, the duration of the preset time period corresponding to the delay circuit 114 may be longer, for example, 100 microseconds (us), after the delay circuit 114 keeps outputting the first flag signal 60 for the preset time period, the output of the first flag signal 60 is stopped, and the protection circuit 12 exits the protection state. Thereafter, the first detection circuit 11 may output the first flag signal 60 when the high power input signal 50 is detected again. That is, the first detection circuit 11 can cyclically detect whether the input signal 50 is a high power signal according to the time duration that can be delayed by the delay circuit 114. For example, the operation timing chart corresponding to this manner can be seen in fig. 16. However, as shown in fig. 16, since the circuit processing requires a certain time, the time t3 at which the protection circuit 12 exits the protection state lags behind the time t4 at which the first flag signal 60 jumps to the low level.

In some embodiments of the present application, the first detection circuit 11 is further configured to provide the first flag signal 60 to the DBB 22 in the wireless receiving circuit 20, the DBB 22 is configured to output a first control signal 70 to the protection circuit 12, and the protection circuit 12 maintains a protection state in response to the first control signal 70. In this case, the preset time period corresponding to the delay circuit 114 may be short, for example, 10 us.

In this case, the signal for controlling whether the protection circuit 12 is in the protection state includes the first flag signal 60 and the first control signal 70, and the protection circuit 12 is maintained in the protection state when either of the two signals is active. Thus, even if the first flag signal 60 transitions to an invalid signal due to the input signal 50 being attenuated in the protection state, the first control signal 70 may cause the protection circuit 12 to maintain the protection state. Optionally, the first flag signal 60 and the first control signal 70 may be coupled to the protection circuit 12 through an or gate. In this case, the operation timing diagram of the overvoltage protection circuit 10 can be seen in fig. 18. It should be noted that, in the embodiment of the present application, the first control signal 70 is active at a high level for example, and the first control signal may also be active at a low level, which is not particularly limited in the embodiment of the present application. For example, when the first detection circuit 11 includes the first control signal 70, the signal transmission relationship between the modules can be seen in fig. 17.

Specifically, referring to fig. 19, the delay circuit 114 according to the previous embodiment may include a fifth MOS tube 1143, a first resistor 1141 and a first capacitor 1142, the fifth MOS tube 1143 and the first resistor 1141 are connected in series between a power source (e.g., a predetermined voltage source) and ground, and a series connection point of the fifth MOS tube 1143 and the first resistor 1141 is coupled to the first capacitor 1142 and configured to keep outputting the first flag signal 60 for a predetermined period of time. IN fig. 19, IN denotes an input terminal of the delay circuit 114, and OUT denotes an output terminal of the delay circuit 114. The delay circuit 114 can delay for a period of time which is a product of the resistance R of the first resistor 1141 and the capacitance C of the first capacitor 1142.

The first resistor 1141 and the first capacitor 1142 in the delay circuit 114 may be implemented by MOS transistors. In this way, the influence of process fluctuation on the magnitude of the RC product value can be reduced, thereby improving the delay accuracy of the delay circuit 114. Specifically, when the first resistor 1141 is implemented by a sixth MOS transistor and the first capacitor 1142 is implemented by a seventh MOS transistor, if the resistance values of the sixth MOS transistor and the seventh MOS transistor are increased due to reasons such as the manufacturing process of the MOS transistors, the capacitance values of the sixth MOS transistor and the seventh MOS transistor are decreased, that is, the resistance value R of the first resistor 1141 is increased, and the capacitance value C of the first capacitor 1142 is decreased; if the resistance values of the sixth MOS transistor and the seventh MOS transistor are reduced due to reasons such as the manufacturing process of the MOS transistors, the capacitance values of the sixth MOS transistor and the seventh MOS transistor are increased, that is, the resistance value R of the first resistor 1141 is reduced, and the capacitance value C of the first capacitor 1142 is increased; thus, the product of RC is substantially unchanged or varies little. Optionally, the first resistor 1141 may be a variable resistor to flexibly set the magnitude of R and thus the time length that the delay circuit 114 can delay.

For example, referring to fig. 20, the DBB 22 may determine whether the voltage amplitude of the input signal 50 at the input end of the wireless receiving circuit 20 is smaller than a first preset value by a signal received from a receiving path in which the devices such as L NA, mixer, L PF, VGA, and ADC in the wireless receiving circuit 20 are located, and may consider the signal input from the outside by the wireless receiving circuit 20 as a low-power signal if the voltage amplitude is smaller than the first preset value.

The operation timing diagram of the overvoltage protection circuit 10 shown in fig. 20 can be seen in fig. 21. It should be noted that, in the embodiment of the present application, the second control signal 80 is active at a low level for example, and the second control signal 80 may also be active at a high level, which is not limited in the embodiment of the present application. The time t3 at which the protection circuit 12 exits the protection state lags the time t5 at which the second control signal 80 jumps from a high level to a low level. When the first flag signal 60 is active high, the first control signal 70 is active high, and the second control signal 80 is active low, optionally, the first flag signal 60, the first control signal 70, and the second control signal 80 may be coupled to the protection circuit 12 through an or gate.

In some other embodiments of the present application, referring to fig. 22, the overvoltage protection circuit 10 may further include a second detection circuit 13, where the second detection circuit 13 is configured to provide a second flag signal 90 to the protection circuit 12 when detecting that the voltage amplitude of the input signal 50 at the input end 200 of the wireless receiving circuit 20 is smaller than a second preset value, and the protection circuit 12 exits the protection state in response to the second flag signal 90.

When the second detection circuit 13 detects that the voltage amplitude of the input signal 50 is smaller than the second preset value, the signal input from the outside by the wireless receiving circuit 20 may be considered as a low-power signal, and the protection circuit 12 may exit the protection state. It should be noted that, in the protection state, since the input signal 50 is attenuated by the protection circuit 12, when the signal inputted from the outside by the wireless receiving circuit 20 is a low-power signal, the amplitude of the input signal detected from the input terminal 200 by the second detecting circuit 13 is small, and thus the second preset value may be set to be small, for example, smaller than the previously mentioned preset value a. The second detection circuit 13 is similar in structure to the first detection circuit 11 and will not be described in detail here.

The operation timing diagram of the overvoltage protection circuit shown in fig. 22 can be seen in fig. 23. It should be noted that, in the embodiment of the present application, the second flag signal 90 is active low, and the second flag signal 90 may also be active low, which is not limited in the embodiment of the present application. In fig. 23, the time t3 at which the protection circuit 12 exits the protection state lags behind the time t6 at which the first flag signal jumps from high to low. When the first flag signal 60 is active high, the first control signal 70 is active high, and the second flag signal 90 is active low, the first flag signal 60, the first control signal 70, and the second flag signal 90 may be optionally coupled to the protection circuit 12 through an or gate.

Further, on the basis of the scenario shown in fig. 22, the second detection circuit 13 may also notify the DBB 22 of the second flag signal 90, so that the DBB 22 knows that the signal input from the outside by the wireless receiving circuit 20 is a low-power signal in time. In some other embodiments of the present application, referring to fig. 24, the overvoltage protection circuit 10 further includes a second detection circuit 13, the second detection circuit 13 is configured to provide a second flag signal 90 to the DBB 22 when detecting that the voltage amplitude of the input signal 50 at the input end 200 of the wireless receiving circuit 20 is smaller than a second preset value, the second flag signal 90 is configured to control the DBB 22 to provide a second control signal 80 to the protection circuit 12, and the protection circuit 12 exits the protection state in response to the second control signal 80.

The operation timing diagram of the overvoltage protection circuit 10 shown in fig. 24 can be seen in fig. 25. When the first flag signal 60 and the first control signal 70 are active high and the second control signal 80 and the second flag signal 90 are active low, the first flag signal 60, the first control signal 70, the second control signal 80, and the second flag signal 90 may be optionally coupled to the protection circuit 12 through an or gate.

In addition, in the embodiment of the present application, the first flag signal 60 is also used to control the digital baseband circuit DBB 22 to reduce the gain of the amplifier in the wireless receiving circuit 20. thus, the signal distortion and other problems caused by the saturation of the signal amplified by the amplifier in the wireless receiving circuit 20 can be prevented.

Another embodiment of the present application further provides a circuit system, which includes the overvoltage protection circuit 10 and the wireless receiving circuit 20 shown in fig. 3-25, optionally, the wireless receiving circuit 20 may include one or more devices of L NA, a mixer, L PF, VGA, ADC, or DBB, optionally, the circuit system may also be integrated on a chip, for example, the overvoltage protection circuit 10 is specifically configured to protect the first MOS transistor 21 in L NA of the wireless receiving circuit 20, and the first MOS transistor 21 may be coupled to an input terminal of the wireless receiving circuit 20, which is the first transistor inside the wireless receiving circuit 20.

Through the description of the above embodiments, those skilled in the art will understand that, for convenience and simplicity of description, only the division of the above functional modules is used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

An overvoltage protection circuit (10) of a first MOS transistor (21) in a wireless receiving circuit (20) is characterized by comprising a first detection circuit (11) and a protection circuit (12);

the first detection circuit (11) is used for outputting a first mark signal (60) according to an input signal (50) of an input end (200) of a wireless receiving circuit (20) and a reference signal (40), wherein the input end (200) of the wireless receiving circuit (20) is coupled with a first MOS (21) tube included in the wireless circuit (20);

the protection circuit (12) enters a protection state in response to the first flag signal (60) to attenuate a voltage amplitude of the input signal (50).
The overvoltage protection circuit (10) of claim 1, wherein the first detection circuit (11) comprises a comparator (111), inputs of the comparator (111) input a first signal (30) and the reference signal (40), respectively, the first signal (30) being related to the input signal (50);

the comparator (111) is configured to output a first flag signal (60) based on a comparison of a voltage value of the first signal (30) and a reference voltage value of the reference signal (40).
The overvoltage protection circuit (10) according to claim 1 or 2, wherein the protection circuit (12) comprises a second MOS transistor (121), a gate of the second MOS transistor (121) being coupled to the output of the first detection circuit (11), the second MOS transistor (121) being coupled between the input (200) and ground;

the second MOS transistor (121) is turned on in response to the first flag signal (60) to cause the protection circuit (12) to enter a protection state.
The overvoltage protection circuit (10) according to claim 3, wherein the second MOS transistor (121) is an N-type metal oxide semiconductor (NMOS) transistor, a source of the second MOS transistor (121) is grounded, and a drain of the second MOS transistor (121) is coupled to the input terminal (200) of the wireless receiving circuit (20).
The overvoltage protection circuit (10) according to claim 3 or 4, characterized in that the protection circuit (12) further comprises two anti-parallel diodes (122), and the second MOS transistor (121) is coupled to the input (200) of the wireless receiving circuit (20) via the two anti-parallel diodes (122).
The overvoltage protection circuit (10) according to any one of claims 2 to 5, wherein the input signal (50) of the wireless receiving circuit (20) is an AC input signal, the first detection circuit (11) further comprises a conversion circuit (112), the conversion circuit (112) is configured to convert the AC input signal into the first signal (30), and the first signal (30) is a DC signal.
The overvoltage protection circuit (10) of claim 6, wherein the first detection circuit (11) further comprises a reference circuit (113), the reference circuit (113) being configured to output the reference signal (40), the reference signal (40) being a direct current signal.
The overvoltage protection circuit (10) according to claim 7, wherein the conversion circuit (112) comprises a third MOS transistor (1121) and a first element (1123) connected in series, the first element (1123) is a current source or a resistor, a gate of the third MOS transistor (1121) is coupled to the ac input signal, and a connection point of the third MOS transistor (1121) and the first element (1123) connected in series is used for outputting the first signal (30);

the reference circuit (113) comprises a fourth MOS tube (1131) and a second element (1132) which are connected in series, wherein the second element (1132) is a current source or a resistor, the gate of the fourth MOS tube (1131) is coupled to a reference point, and the serial connection point of the fourth MOS tube (1131) and the second element (1132) is used for outputting the reference signal (40);

the third MOS tube (1121) and the fourth MOS tube (1132) are consistent in size, and the first element (1123) and the second element (1132) are consistent in size.
The overvoltage protection circuit (10) according to any one of claims 2 to 8, wherein the first detection circuit (11) further comprises a delay circuit (114), the delay circuit (114) being configured to keep outputting the first flag signal (60) for a preset period of time while the comparator (111) is outputting the first flag signal (60).
The overvoltage protection circuit (10) of claim 9, wherein the delay circuit (114) comprises a fifth MOS transistor (1143), a first resistor (1141), and a first capacitor (1142), the fifth MOS transistor (1143) and the first resistor (1141) are connected in series between a power source and ground, and a series connection point of the fifth MOS transistor (1143) and the first resistor (1141) is coupled to the first capacitor (1142) and configured to keep outputting the first flag signal (60) for a predetermined period of time.
The overvoltage protection circuit (10) of any one of claims 1-10, wherein the first detection circuit (11) is further configured to provide the first flag signal (60) to a digital baseband circuit DBB (22) in the wireless receiving circuit (20);

the DBB (22) is configured to output a first control signal (70) to the protection circuit (12);

the protection circuit (12) maintains the protection state in response to the first control signal (70).
The overvoltage protection circuit (10) of any one of claims 1-11, wherein the digital baseband circuit DBB (22) in the wireless receiving circuit (20) is further configured to provide a second control signal (80) to the protection circuit (12) upon determining that the voltage amplitude of the input signal (50) is less than a first predetermined value;

the protection circuit (12) exits the protection state in response to the second control signal (80).
The overvoltage protection circuit (10) according to any one of claims 1-11, wherein the overvoltage protection circuit (10) further comprises a second detection circuit (13), the second detection circuit (13) being configured to provide a second flag signal (90) to the protection circuit (12) upon detecting that the voltage amplitude of the input signal (50) is less than a second preset value;

the protection circuit (12) exits the protection state in response to the second flag signal (90).
The overvoltage protection circuit (10) according to any one of claims 1-11, wherein the overvoltage protection circuit (10) further comprises a second detection circuit (13);

the second detection circuit (13) is used for providing a second mark signal (90) to the DBB (22) when detecting that the voltage amplitude of the input signal (50) is smaller than a second preset value;

the second flag signal (90) is used for controlling the DBB (22) to provide a second control signal (80) to the protection circuit (12);

the protection circuit (12) exits the protection state in response to the second control signal (80).
The overvoltage protection circuit (10) of any one of claims 1-14, wherein the first flag signal (60) is further configured to control a digital baseband circuit DBB (22) to reduce a gain of an amplifier in the wireless receiving circuit (20).
A circuit system comprising the overvoltage protection circuit (10) of any one of claims 1 to 15 and a wireless receiver circuit (20).
The circuitry of claim 16, wherein the wireless receiving circuit (20) comprises one or more of a low noise amplifier L NA, a mixer, a low pass filter L PF, a variable gain amplifier VGA, an analog-to-digital converter ADC, or a digital baseband circuit DBB.
A chip comprising the circuitry of claim 16 or 17.