HK40103418A - Equalization filter calibration in a transceiver circuit - Google Patents

Description

Equalization filter calibration in transceiver circuit

Cross-referencing related applications

This application claims the benefit of Provisional Patent Application No. 63/245,139, filed September 16, 2021; Provisional Patent Application No. 63/303,531, filed January 27, 2022; and U.S. Patent Application No. 17/737,300, filed May 5, 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The technology disclosed herein generally relates to a transmitting circuit for transmitting radio frequency (RF) signals modulated in a wide modulation bandwidth.

Background Technology

Mobile communication devices have become increasingly prevalent in modern society for providing wireless communication services. This widespread adoption is partly driven by the numerous features now available on these devices. The increased processing power of these devices means they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

The redefined user experience relies on higher data rates provided by advanced fifth-generation (5G) and 5G New Radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in the millimeter-wave spectrum. Given that RF signals are more susceptible to attenuation and interference in the millimeter-wave spectrum, they are typically amplified by state-of-the-art power amplifiers to help increase the RF signal to higher power before transmission.

Envelope tracking (ET) is a power management technique designed to improve the efficiency and/or linearity performance of power amplifiers. In an ET power management circuit, a power management integrated circuit (PMIC) is configured to generate a time-varying ET voltage based on the time-varying voltage envelope of an RF signal, and the power amplifier is configured to amplify the RF signal based on the time-varying ET voltage. It is understood that the better the time-varying ET voltage is aligned with the time-varying voltage envelope in time and amplitude, the better the performance (e.g., efficiency and/or linearity) achievable at the power amplifier. However, due to a range of factors (e.g., group delay, impedance mismatch, etc.), the time-varying ET voltage may be misaligned with the time-varying voltage envelope in time and/or amplitude. Therefore, it is desirable to always maintain good alignment between the time-varying voltage and the time-varying voltage envelope, as well as over a wide modulation bandwidth.

Summary of the Invention

Embodiments of this disclosure relate to equalization filter calibration in transceiver circuitry. The transceiver circuitry generates a radio frequency (RF) signal from a time-varying modulation vector, and a power amplifier circuitry amplifies the RF signal based on the modulated voltage and provides the amplified RF signal to a coupled RF front-end circuitry (e.g., a filter/multiplexer circuitry). Notably, when the power amplifier circuitry is coupled to the RF front-end circuitry, the output reflection coefficient of the power amplifier circuitry (e.g., _S22 ) can interact with the input reflection coefficient of the RF front-end circuitry (e.g., _S11 ) to produce voltage distortion filtering at the output stage of the power amplifier circuitry, which can result in unwanted distortion in the RF signal. In this regard, the transceiver circuitry is configured to apply equalization filtering to the time-varying modulation vector to compensate for voltage distortion filtering at the output stage of the power amplifier circuitry. In the embodiments disclosed herein, calibration circuitry can be configured to calibrate the equalization filter across multiple frequencies within the modulation bandwidth of the power amplifier circuitry to generate gain offset (LUT) and delay LUT. Therefore, equalization filtering can be dynamically adapted to reduce unwanted transient overcompression and/or spectral regeneration caused by voltage distortion filtering within the modulation bandwidth of the power amplifier circuit.

In one aspect, a transceiver circuit is provided. The transceiver circuit includes memory circuitry. The transceiver circuit also includes calibration circuitry. The calibration circuitry is coupled to a power amplifier circuit. The calibration circuitry is configured to determine a gain offset LUT and store it in the memory circuitry to correlate a plurality of calibrated frequencies within the modulation bandwidth of the power amplifier circuit with a plurality of gain offsets, respectively. The calibration circuitry is also configured to determine a delay offset LUT and store it in the memory circuitry to correlate the plurality of calibrated frequencies with a plurality of delay factors, respectively.

On the other hand, a method for calibrating equalization filtering in transceiver circuitry is provided. The method includes determining and storing a gain offset LUT to correlate a plurality of calibrated frequencies within a modulation bandwidth with a plurality of gain offsets, respectively. The method also includes determining and storing a delay offset LUT to correlate the plurality of calibrated frequencies with a plurality of delay factors, respectively.

Those skilled in the art will recognize the scope of this disclosure and understand its other aspects after reading the following detailed description of preferred embodiments and the accompanying drawings.

Attached Figure Description

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

Figure 1A is a schematic diagram of an exemplary existing transmitter circuit, in which unwanted voltage distortion filtering may occur on the power amplifier circuit when the power amplifier circuit is coupled to the radio frequency (RF) front-end circuit.

Figure 1B is a schematic diagram illustrating an exemplary diagram of the output stage of the power amplifier circuit in Figure 1A;

Figure 2 is a schematic diagram of an exemplary equivalent model, providing an exemplary illustration of unwanted voltage distortion filtering caused by the coupling between the power amplifier circuit and the RF front-end circuit 14 in Figure 1A.

Figure 3 is a schematic diagram of an exemplary transmitter circuit configured to compensate for unwanted voltage distortion in the existing transmitter circuit of Figure 1A based on equalization filtering.

Figures 4A-4C are diagrams providing exemplary illustrations of why the equalization filter in Figure 3 must be calibrated within the modulation bandwidth of the transmitting circuit;

Figure 5 is a schematic diagram of an exemplary transceiver circuit, which can be configured, according to embodiments of the present disclosure, to calibrate equalization filtering within the modulation bandwidth of the transmitting circuit of Figure 3.

Figure 6 is a flowchart of an exemplary calibration process that can be used by the transceiver circuit of Figure 5 to calibrate the equalization filter;

Figure 7 is a flowchart of an exemplary process by which the transceiver circuitry of Figure 5 can be used to determine the gain offset lookup table (LUT) as part of the calibration process of Figure 6.

Figures 8A-8B are graphs illustrating the effects of equalization filter calibration performed based on the processes in Figures 6 and 7;

Figure 9 is a flowchart of an exemplary process for determining a gain offset LUT using the transceiver circuitry of Figure 5, according to an alternative embodiment of the present disclosure; and

Figure 10 is a flowchart of an exemplary process that can be used by the transceiver circuitry of Figure 5 to determine the delay LUT as part of the calibration process of Figure 6.

Detailed Implementation

The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. Those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically described herein when reading the following description in conjunction with the accompanying drawings. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending" to another element, it may be directly on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "above another element" or "extending above another element," it may be directly above or directly extended above the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly above another element" or "extending directly above another element," no intermediate elements are present. It will also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

For example, relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or area to another element, layer, or area as shown in the figures. It should be understood that these terms, and those discussed above, are intended to include different orientations of the device other than those depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a/an” and “described” are also intended to include the plural forms. It should also be understood that, when used herein, the terms “comprises/comprising” and/or “includes/including” specify the presence of the said feature, integer, step, operation, element, and/or component, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, the terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and in the relevant art, and shall not be interpreted in an idealized or overly formal sense.

Embodiments of this disclosure relate to equalization filter calibration in transceiver circuitry. The transceiver circuitry generates a radio frequency (RF) signal based on a time-varying modulation vector, and a power amplifier circuitry amplifies the RF signal based on the modulated voltage and provides the amplified RF signal to a coupled RF front-end circuitry (e.g., a filter/multiplexer circuitry). Notably, when the power amplifier circuitry is coupled to the RF front-end circuitry, the output reflection coefficient of the power amplifier circuitry (e.g., _S22 ) can interact with the input reflection coefficient of the RF front-end circuitry (e.g., _S11 ) to produce voltage distortion filtering at the output stage of the power amplifier circuitry, which can result in unwanted distortion in the RF signal. In this regard, the transceiver circuitry is configured to apply equalization filtering to the time-varying modulation vector to compensate for voltage distortion filtering at the output stage of the power amplifier circuitry. In the embodiments disclosed herein, calibration circuitry can be configured to calibrate the equalization filter across multiple frequencies within the modulation bandwidth of the power amplifier circuitry to generate gain offset (LUT) and delay LUT. Therefore, equalization filtering can be dynamically adapted to reduce unwanted transient overcompression and/or spectral regeneration caused by voltage distortion filtering within the modulation bandwidth of the power amplifier circuit.

Before discussing the transceiver circuitry and calibration process according to this disclosure, starting with Figure 5, a brief discussion is first provided to help explain why it is necessary to calibrate the equalization filter used in existing transmitter circuits to suppress unwanted voltage distortion filtering.

Figure 1A is a schematic diagram of an exemplary conventional transmitter circuit 10, in which unwanted voltage distortion filtering H _IV (s) presented to the power amplifier circuit 12 when the power amplifier circuit 12 is coupled to the RF front-end circuit 14 may cause memory distortion in the power amplifier circuit 12. It is worth noting that in unwanted voltage distortion filtering H _IV (s), "s" is a representation of the Laplace transform.

The existing transmitting circuit 10 includes a transceiver circuit 16, an ETIC 18, and a transmitter circuit 20, which may include, for example, an antenna (not shown). The transceiver circuit 16 is configured to generate an RF signal 22 with a time-varying input power P_{_IN} and provide the RF signal 22 to a power amplifier circuit 12. The transceiver circuit 16 is also configured to generate a time-varying target voltage _VTGT that tracks the time-varying input power P_{_IN} of the RF signal 22. The ETIC 18 is configured to generate a modulated voltage V_{_CC} that tracks the time-varying target voltage _VTGT and provide the modulated voltage V_{_CC} to the power amplifier circuit 12. Therefore, the power amplifier circuit 12 can amplify the RF signal 22 to a time-varying output power P _{_OUT} based on the time-varying output voltage V _{_OUT}. The power amplifier circuit 12 then provides the amplified RF signal 22 to an RF front-end circuit 14. The RF front-end circuit 14 may be a filtering circuit that performs further frequency filtering on the amplified RF signal 22 before providing it to the transmitter circuit 20 for transmission.

Figure 1B is a schematic diagram providing an exemplary illustration of the output stage 24 of the power amplifier circuit 12 in Figure 1A. Common components between Figures 1A and 1B are shown with common component reference numerals and will not be described again herein.

Output stage 24 may include at least one transistor 26, such as a bipolar junction transistor (BJT) or a complementary metal-oxide-semiconductor (CMOS) transistor. Taking a BJT as an example, transistor 26 may include a base electrode B, a collector C, and an emitter E. The base electrode B is configured to receive a bias voltage _VBIAS , and the collector C is configured to receive a modulated voltage _VCC . The collector C is also coupled to RF front-end circuitry 14 and configured to output an amplified RF signal 22 at an output voltage _VOUT. In this respect, the output voltage _VOUT may depend on the modulated voltage _VCC . It is understood that when the time-varying modulated voltage _VCC is aligned with the time-varying input power _PIN , the power amplifier circuitry 12 will operate with good efficiency and linearity.

Figure 2 is a schematic diagram of an exemplary equivalent model 28, providing an exemplary illustration of voltage distortion filtering _HIV (s) resulting from the coupling between the power amplifier circuit 12 and the RF front-end circuit 14 in the existing transmitter circuit 10 of Figure 1A. The components in Figures 1A and 1B are mentioned in Figure 2 and will not be described again herein.

In equivalent model 28, _VPA and _ZPA represent the output stage 24 and the inherent impedance of the power amplifier circuit 12, respectively, and _Z11 represents the inherent impedance associated with the input port of the RF front-end circuit 14. In this document, _VOUT represents the output voltage associated with the RF signal 22 before the power amplifier circuit 12 is coupled to the RF front-end circuit 14, and _V'OUT represents the output voltage associated with the RF signal 22 after the power amplifier circuit 12 is coupled to the RF front-end circuit 14. Hereinafter, the output voltages _VOUT and _V'OUT are referred to as "uncoupled output voltage" and "coupled output voltage," respectively, for distinction.

The Laplace transform of the coupled output voltage _V'OUT can be expressed by the following equation (Equation 1).

In the above equation (Equation 1), _TPA (s) represents the reflection coefficient looking back to the output stage 24 of the power amplifier circuit 12, and _TI (s) represents the reflection coefficient to the RF front-end circuit 14. It is worth noting that _TPA (s) and _TI (s) are complex filters containing amplitude and phase information. In this respect, _TPA (s), _TI (s), and therefore the voltage distortion filter _HIV (s) depend on factors such as modulation bandwidth, RF frequency, and/or voltage standing wave ratio (VSWR).

Equation (Equation 1) shows that when the power amplifier circuit 12 is coupled to the RF front-end circuit 14, the coupled output voltage _V'OUT will be changed from the uncoupled output voltage _VOUT by the voltage distortion filter _HIV (s). Therefore, the coupled output voltage _V'OUT may be misaligned with the modulated voltage _VCC , thus causing unwanted distortion in the RF signal 22.

It is worth noting that the modulated voltage _VCC can be modified to compensate for the voltage distortion filter _HIV (s), thereby reducing or eliminating the difference between the uncoupled output voltage _VOUT and the coupled output voltage _V'OUT . Therefore, undesirable transient overcompression and/or spectral regrowth caused by the voltage distortion filter _HIV (s) can be reduced.

In this regard, Figure 3 is a schematic diagram of an exemplary transmitter circuit 30 configured to compensate for unwanted voltage distortion filtering H_{_IV}(s) in the existing transmitter circuit 10 of Figure 1A based on equalization filtering H_{_ET} (s). The transmitter circuit 30 is configured to transmit an RF signal 32 modulated over a wide range of modulation bandwidths. In a non-limiting example, the RF signal 32 may be modulated in a modulation bandwidth of 200 MHz or higher and transmitted in the millimeter-wave RF spectrum.

Transmitter circuit 30 includes transceiver circuit 34, power amplifier circuit 36, and ETIC 38. Power amplifier circuit 36 is coupled to transmitter circuit 40 via RF front-end circuit 42. In a non-limiting example, RF front-end circuit 42 may include one or more of a filter circuit and a multiplexer circuit (not shown). The filter circuit may be configured to include a filter network, such as a filter network with a sharp cutoff frequency. Power amplifier circuit 36 may be the same as or functionally equivalent to power amplifier circuit 12 in FIG. 1B. Therefore, power amplifier circuit 36 may also include output stage 24 as in power amplifier circuit 12.

Transceiver circuit 34 includes signal processing circuit 44 and target voltage circuit 46. Signal processing circuit 44 is configured to generate RF signal 32 from time-varying modulation vector b _MOD ^→. Time-varying modulation vector b _MOD ^→ can be generated by digital baseband circuitry (not shown) in transceiver circuit 34 and includes both in-phase (I) and quadrature (Q) components. Target voltage circuit 46 is configured to detect the time-varying amplitude envelope of RF signal 32 from time-varying modulation vector b _MOD ^→. Therefore, target voltage circuit 46 can generate modulated target voltage _VTGT based on the detected time-varying amplitude envelope.

ETIC 38 is configured to generate a modulated voltage _VCC based on the modulated target voltage _VTGT , and provide the modulated voltage _VCC to the power amplifier circuit 36. The power amplifier circuit 36 then amplifies the RF signal 32 to an output voltage _VOUT based on the modulated voltage _VCC for transmission via the RF front-end circuit 42 and the transmitter circuit 40.

As previously described, the output voltage _VOUT depends on the modulated voltage _VCC . In this regard, it is possible to reduce or even eliminate the difference between the uncoupled output voltage _VOUT and the coupled output voltage _V'OUT by generating the modulated voltage _VCC to compensate for the voltage distortion filter _HIV (s). Considering that ETIC 38 is configured to generate _{the modulated voltage VCC based} on the modulated target voltage VTGT, it is possible to reduce or even eliminate the difference between the uncoupled output voltage _VOUT and the coupled output voltage _V'OUT by generating the modulated target voltage _VTGT to compensate for the voltage distortion filter _HIV (s).

In this regard, transceiver circuit 34 further includes equalizer circuit 48. Equalizer circuit 48 is configured to apply an equalization filter _HET (s) to the time-varying modulation vector _bMOD ^→ prior to the generation of the modulated target voltage _VTGT by target voltage circuit 46. In an embodiment, the equalization filter _HET (s) can be described by the following equation (Equation 2).

H _{_ET}(s) = H_{_IQ}(s) * H _{_PA}(s) * H_{_IV}(s) (Equation 2)

In the above equation (Equation 2), _HIQ (s) represents the transfer function of signal processing circuit 44, and _HPA (s) represents the voltage gain transfer function of power amplifier circuit 36. In this respect, the equalization filter _HET (s) is configured to match the combined signal path filter, which includes the transfer function _HIQ (s), the voltage gain transfer function _HPA (s), and the voltage distortion filter _HIV (s).

In one embodiment, equalizer circuit 48 applies equalization filter _HET (s) to time-varying modulation vector _bMOD ^→ to generate equalized time-varying modulation vector bMOD _-E ^→ , and provides the equalized time-varying modulation vector bMOD _-E → to target voltage circuit 46. Target voltage circuit 46 then detects the time-varying amplitude envelope from the equalized time-varying modulation vector bMOD _-E ^→ and generates modulated target voltage _VTGT based on the detected time-varying amplitude envelope. Since the modulated target voltage _VTGT is generated by the equalized time-varying modulation vector _bMOD-E ^→ , the modulated target voltage _VTGT and therefore the modulated voltage _VCC will be able to compensate for voltage distortion filter _HIV (s), which is generated at the output stage 24 of power amplifier circuit 36 by coupling power amplifier circuit 36 to RF front-end circuit 42.

In one embodiment, the target voltage circuit 46 includes an amplitude detector circuit 50, an ET LUT circuit 52, and a digital-to-analog converter (DAC) 54. The amplitude detector circuit 50 is configured to detect the time-varying amplitude envelope from the equalized time-varying modulation vector b _MOD-E ^→. The ET LUT circuit 52 may include an isogain LUT (not shown) that correlates the time-varying amplitude envelope with various voltage levels. The DAC 54 is configured to generate a time-varying digital target voltage V _DTGT based on the detected time-varying amplitude envelope. The DAC 54 is configured to convert the time-varying digital target voltage V _DTGT into a modulated target voltage _VTGT and provide the modulated target voltage _VTGT to the ETIC 38.

In an embodiment, signal processing circuitry 44 may include memory digital predistortion (mDPD) circuitry 56 and modulator circuitry 58. mDPD circuitry 56 is configured to receive a time-varying modulation vector b _MOD-E ^→ and digitally predistort the time-varying modulation vector b _MOD-E ^→ to generate a predistorted time-varying modulation vector b _MOD-DPD ^→ . Modulator circuitry 58 is configured to generate an RF signal 32 from the predistorted time-varying modulation vector b _MOD-DPD ^→ and provide the RF signal 32 to power amplifier circuitry 36.

As previously stated, the RF signal 32 can be modulated within a wide range of modulation bandwidths. Hereinafter, modulation bandwidth refers to the range of RF frequencies to which the RF signal 32 can be modulated and/or to which the transmitting circuit 30 is configured to process. For example, if the RF signal 32 can be modulated between 2554 MHz and 2654 MHz, the modulation bandwidth will be 100 MHz and the center frequency ( _FC ) of the modulation bandwidth will be 2604 MHz. Therefore, any other frequency within the modulation bandwidth will be considered a non-center frequency ( _FC ) (2554 MHz ≤ _FNC < 2604 MHz and 2604 MHz < _FNC ≤ 2654 MHz). Hereinafter, the modulation bandwidth of the RF signal 32 may be interchangeably referred to as the modulation bandwidth of the transmitting circuit 30.

In this regard, the equalization filter _HET (s) needs to suppress voltage distortion filtering _HIV (s) across the entire modulation bandwidth. However, since the isogain LUT in the ET LUT circuit 52 is typically determined based on the center frequency within the modulation bandwidth, the isogain LUT in the ETLUT circuit 52 may not provide a constant isogain for all other frequencies within the modulation bandwidth. Therefore, the equalization filter _HET (s) must be calibrated to ensure that the isogain LUT determined based on the center frequency provides a constant isogain across all frequencies within the modulation bandwidth.

Figures 4A-4C are diagrams providing exemplary illustrations of why the equalization filter _HET (s) in Figure 3 must be calibrated within the modulation bandwidth of the transmitting circuit 30. Common components between Figures 4A-4C are shown with common component labels and will not be described again herein.

Figure 4A shows the center frequency LUT 60 corresponding to the center frequency F _C within the modulation bandwidth of the transmitting circuit 30 and the non-center frequency LUT 62 corresponding to the non-center frequency F _NC within the modulation bandwidth of the transmitting circuit 30.

Figure 4B illustrates the center frequency gain 64 provided by the center frequency LUT 60 and the non-center frequency gain 66 provided by the non-center frequency LUT 62. As shown, when the RF signal 32 is modulated at the center frequency F_{_C} and has an input power P _{_IN} between -25dBm and 3dBm for the center frequency F_{_C}, the center frequency LUT 60 can provide a constant gain of 30dB. On the other hand, when the RF signal 32 is modulated at the non-center frequency F_{_NC} and has an input power P _{_IN} between -25dBm and 4dBm, the non-center frequency LUT 62 can provide a constant gain of 29dB. In this respect, if the ET LUT circuit 52 uses both the center frequency LUT 60 and the non-center frequency LUT 62, it is possible to achieve a constant gain when the RF signal 32 is modulated at both the center frequency F _{_C} and the non-center frequency F_{_NC} .

However, when the ET LUT circuit 52 uses only the center frequency LUT 60, the non-center frequency LUT 62 will not be able to maintain a constant gain of 29 dB at the non-center frequency F _NC . As shown in Figure 4C, the center frequency LUT 60 in Figure 4A provides a gain variation of 29.4 dB to 30.5 dB between -25 dBm and +2 dBm, but does not provide a constant gain of 29 dB when the RF signal 32 is modulated at the non-center frequency F _NC . Therefore, it is desirable to calibrate the equalization filter H _ET (s) to ensure that the center frequency LUT 60 can provide a constant gain at both the center and non-center frequencies within the modulation bandwidth of the RF signal 32.

In this regard, FIG5 is a schematic diagram of an exemplary transceiver circuit 68, which may be configured, according to embodiments of the present disclosure, to calibrate the equalization filter _HET (s) within the modulation bandwidth of the transmitting circuit of FIG3. Common elements between FIG3 and 5 are shown with common component reference numerals and will not be described again herein. In an embodiment, transceiver circuit 68 may be used in transmitting circuit 30 to replace transceiver circuit 34.

In an embodiment, transceiver circuitry 68 includes memory circuitry 70. For example, memory circuitry 70, which may include storage circuitry such as random access memory (RAM), flash memory, solid-state drive (SSD), etc., is configured to store gain offset LUT 72 and delay LUT 74. In a non-limiting example, gain offset LUT 72 includes a plurality of gain offset entries 76(1)-76(N), each gain offset entry being configured to correct a corresponding one of a plurality of calibrated frequencies _F1 - _FN within the modulation bandwidth with a corresponding one of a plurality of gain offsets _ΔG1 - _ΔGN . Herein, calibrated frequencies _F1 - _FN include all non-center frequencies ( _FNC ) and center frequencies ( _FC ) within the modulation bandwidth. In another non-limiting example, delay LUT 74 includes a plurality of delay entries 78(1)-78(N), each delay entry being configured to correlate a corresponding one of the calibrated frequencies _F1 - _FN with a corresponding one of a plurality of delay factors _τ1 - _τN .

In an embodiment, transceiver circuit 68 may be configured to include calibration circuitry 80, which may be, for example, a field-programmable gate array (FPGA). Although calibration circuitry 80 is located within transceiver circuitry 68 as illustrated herein, it should be understood that calibration circuitry 80 may be decoupled from transceiver circuitry 68 but coupled to transceiver circuitry 68 via, for example, a general-purpose input/output (GPIO) interface. As discussed below, calibration circuitry 80 may be configured to determine and populate gain offset LUT 72 and delay LUT 74 such that the equalization filter _HET (s) can be calibrated so that ET LUT circuitry 52 provides constant gain across all calibrated frequencies _F1 – _FN based on, for example, the center frequency LUT 60 in FIG. 4A.

The calibration circuit 80 can be configured to calibrate the equalization filter _HET (s) based on the process. In this regard, FIG6 is a flowchart of an exemplary calibration process 200 that can be used by the calibration circuit 80 in the transceiver circuit 68 of FIG5 to calibrate the equalization filter _HET (s).

In this paper, the calibration circuit 80 is first configured to determine and store a gain offset LUT 72 containing gain offset entries 76(1)-76(N), wherein each of the gain offset entries 76(1)-76(N) is configured to correlate a corresponding one of the calibrated frequencies _F1 - _FN within the modulation bandwidth with a corresponding one of the gain offsets _ΔG1 - _ΔGN (step 202). Next, the calibration circuit 80 is configured to determine and store a delay LUT 74 containing delay entries 78(1)-78(N), wherein each of the delay entries 78(1)-78(N) is configured to correlate a corresponding one of the calibrated frequencies _F1 - _FN with a corresponding one of the delay factors _τ1 - _τN (step 204).

In an embodiment, calibration circuit 80 may determine gain offset LUT 72 based on the process and store it in memory circuit 70 (step 202). In this regard, FIG7 is a flowchart of an exemplary process 206 that can be used by calibration circuit 80 in transceiver circuit 68 of FIG5 to determine gain offset LUT 72 as part of calibration process 200 of FIG6. The components in FIG5 are mentioned together with the discussion of FIG7 and will not be described again herein.

In this document, calibration circuit 80 is configured to determine the minimum reference voltage VCC _-REF and the minimum reference input power PIN _-REF based on the efficiency target, noise target, and/or linearity target of power amplifier circuit 36 (step 208). In other words, the minimum reference voltage _VCC-REF and the minimum reference input power PIN _-REF can be determined empirically to achieve a desired trade-off between the efficiency target, noise target, and/or linearity target of power amplifier circuit 36. Although calibration circuit 80 is configured herein to determine the minimum reference input power PIN _-REF , it should be understood that the input power _PIN- REF can also be replaced with the corresponding output power.

The calibration circuit 80 then determines the reference frequency _FREF among the calibrated frequencies _F1 - _FN within the modulation bandwidth of the power amplifier circuit 36 (step 210). In a non-limiting example, the reference frequency _FREF may be the center frequency _FC among the calibrated frequencies _F1 - _FN .

Next, the calibration circuit 80 determines the reference target voltage (VTGT-REF) based on the expected root mean square (RMS) of the modulated voltage _VCC (e.g., 2.5V) to be provided to the power amplifier circuit 36 for amplifying the RF signal 32 in the transmitter circuit ₃₀ of FIG3 (step 212).

Next, calibration circuit 80 selects a calibrated frequency F_{_i} from the calibrated frequencies F _₁ - F _{_N} within the modulation bandwidth (step 214). Calibration circuit 80 then determines the corresponding gain Gi of power amplifier circuit 36 when it amplifies the test signal 82 generated at the selected calibrated frequency F_{_i} and the minimum reference input power P _{_IN-REF, based on the minimum reference voltage V_CC-REF} (step 216). It is worth noting that the test signal 82 can be generated by calibration circuit 80 or a separate signal generator (not shown). In a non-limiting example, calibration circuit 80 can measure the output power P _{_OUT} of power amplifier circuit 36 and determine the corresponding reference gain Gi _{_REF} based on the measured output power P _{_OUT} and the determined minimum reference input power P _{_IN-REF}. Subsequently, calibration circuit 80 can determine the corresponding modulated voltage _VCCj (1≦j≦M) and the corresponding input power _PINj (1≦j≦M) that enable power amplifier circuit ₃₆ to amplify RF signal 32 at a selected calibrated frequency F _i (step 218). Hereinafter, M may be the same as or different from N. Therefore, calibration circuit 80 can store the corresponding modulated voltage _VCCj and the corresponding input power _PINj in a temporary voltage LUT (not shown) in memory circuit 70 (step 220). Calibration circuit 80 is configured to repeat steps 214-220 for each of the calibrated frequencies F _i-F_{_N}.

Referring again to Figure 7, calibration circuit 80 selects the calibrated frequency _Fi (1≦i≦N) from the calibrated frequencies _F1 - _FN within the modulation bandwidth (step 222). Calibration circuit 80 then determines the corresponding adjusted input power PIN _-ADJi (1≦i≦N) relative to the input power _PINj (1≦j≦M) in the temporary voltage LUT associated with the modulated voltage _VCCj equal to the reference target voltage _VTGT-REF (step 224). Subsequently, calibration circuit 80 determines the corresponding gain offset _ΔGi (1≦i≦N) between the corresponding adjusted input power at _the reference frequency _FREF and the corresponding adjusted input power PIN _-ADJi at the selected calibrated frequency Fi (step 226). Calibration circuit 80 then stores the selected calibrated frequency _Fi in association with the corresponding gain offset ΔGi in gain offset LUT 72 (step 228). It is worth noting that the calibration circuit 80 is configured to repeat steps 222-228 for each of the calibrated frequencies _F1 - _FN .

Referring back to Figure 5, for each of the calibrated frequencies _F1 - _FN , the equalizer circuit 48 is configured to generate an equalization filter HET(s) based on the gain offset LUT 72, and apply the equalization filter _HET (s) to the time-varying modulation vector _bMOD ^→ to generate an equalized time-varying modulation vector bMOD _-E ^→ . Figures 8A-8B are graphs illustrating the effects of the equalization filter calibration performed based on process 200 of Figure 6 and process 206 of Figure 7.

Figure 8A shows the center frequency LUT 84 corresponding to the center frequency F _{_C in} the calibrated frequencies F_₁-F_{_N} and the non-center frequency LUT 86 corresponding to the non-center frequency F_{_NC} in the calibrated frequencies F₁-F_N. It is noteworthy that both the center frequency LUT 84 and the non-center frequency LUT 86 are based on the same minimum reference voltage V _{_CC-REF} and the same minimum reference input power P _{_IN-REF} . The center frequency LUT 84 will be stored in the ET LUT circuit 52 in the transmitting circuit 30 for generating the time-varying digital target voltage V _{_DTGT} from the detected time-varying amplitude envelope. On the other hand, the non-center frequency LUT 86 is not stored in the ET LUT circuit 52 and can be considered a “virtual” LUT. The equalization filter H _{_ET} (s) can superimpose the non-center frequency LUT 86 onto the center frequency LUT 84 using the corresponding gain offset Δ_{_i} (1≦i≦N) in the non-center frequency _F _NC. As shown in Figure 8A, this is equivalent to shifting the non-center frequency LUT 86 to the left to overlap with the center frequency LUT 84. Therefore, as shown in Figure 8B, both the center frequency gain 88 and the non-center frequency gain 90 are relatively constant.

In an embodiment, calibration circuit 80 may determine gain offset LUT 72 based on an substitution process and store it in memory circuit 70 (step 202). In this regard, FIG9 is a flowchart of an exemplary process 230 that can be used by calibration circuit 80 in transceiver circuit 68 of FIG5 to determine gain offset LUT 72 according to another embodiment of the present disclosure. The elements in FIG5 are mentioned together with the discussion of FIG9 and will not be described again herein.

In this document, calibration circuit 80 is configured to determine the reference voltage _VCC-REF and the reference input power PIN _-REF based on the efficiency and/or noise targets of power amplifier circuit 36 (step 232). In other words, the reference voltage VCC- _REF and the reference input power PIN _-REF can be determined empirically to achieve a desired trade-off between the efficiency and noise targets of power amplifier circuit 36. Although calibration circuit 80 is configured herein to determine the reference input power PIN _-REF , it should be understood that the reference input power PIN _-REF can also be replaced by the corresponding reference output power.

The calibration circuit 80 then determines the reference frequency _FREF among the calibrated frequencies _F1 - _FN within the modulation bandwidth of the power amplifier circuit 36 (step 234). In a non-limiting example, the reference frequency _FREF may be the center frequency _FC among the calibrated frequencies _F1 - _FN .

Next, the calibration circuit 80 determines the reference target voltage ( _VTGT-REF ) based on the expected RMS of the modulated voltage _VCC (e.g., 2.5V) to be provided to the power amplifier circuit 36 for amplifying the RF signal 32 in the transmitter circuit 30 of FIG3 (step 236).

Next, the calibration circuit 80 selects the calibrated frequency F_{_i} from the calibrated frequencies F _₁ - _{F_N} within the modulation bandwidth (step 238). The calibration circuit 80 determines the corresponding gain Gi ( _1≦i ≦N) of the power amplifier circuit 36 when the power amplifier circuit 36 amplifies the test signal 82 generated at the selected calibrated frequency F_i and the reference input power P_IN-REF based on the reference voltage _V _{_CC-REF} (step 240).

The calibration circuit 80 then adjusts the corresponding gain _Gi based on the determined compression gain G _CMP to determine the compressed reference gain G _REF-CMP (step 242). It is worth noting that the calibration circuit 80 can empirically determine the compressed gain G _CMP to achieve the desired linearity target of the power amplifier circuit 36.

The calibration circuit 80 then determines the corresponding modulated voltage _VCCj (1≦j≦M) and the corresponding input power PINj (1≦j≦M) that will cause the power amplifier circuit 36 to amplify the test signal 82 at the selected _calibrated frequency F _i to have a compressed reference gain G _{_REF-CMP} (step 244). Hereinafter, M may be the same as or different from N. Therefore, the calibration circuit 80 may store the corresponding modulated voltage _VCCj and the corresponding input power _PINj in a temporary voltage LUT (not shown) in the memory circuit 70 (step 246). The calibration circuit 80 is configured to repeat steps 238-246 for each of the calibrated frequencies F _i-F_{_N}.

Referring again to Figure 9, calibration circuit 80 selects the calibrated frequency F_i (1≦i≦N) from the calibrated frequencies _{F ₁} - F_{_N} within the modulation bandwidth (step 248). Calibration circuit 80 then determines the corresponding adjusted input power P _IN-ADJi (1≦i≦N) in the temporary voltage LUT associated with the modulated voltage V _{_CCj} (1≦j≦M) equal to the reference target voltage V_{_TGT-REF} (step 250).

Subsequently, calibration circuit 80 determines the corresponding gain offset ΔG_{_i} (1≦i≦N) between the corresponding adjusted input power at the reference frequency F _{_REF} and the corresponding adjusted input power P _{_IN-ADJi} at the selected calibrated frequency F_i (step 252). Calibration circuit 80 then stores the selected calibrated frequency F_i in association with the corresponding gain offset _Gi in gain offset LUT 72 (step 254). It is worth noting that calibration circuit 80 is configured to repeat steps 248-254 for each of the calibrated frequencies F _₁ - F_{_N} .

In an embodiment, calibration circuit 80 may determine the delay LUT 74 based on the process and store it in memory circuit 70 (step 204). In this regard, FIG10 is a flowchart of an exemplary process 256 that can be used by transceiver circuit 68 of FIG5 to determine the delay LUT 74 as part of calibration process 200 of FIG6. The components in FIG5 are mentioned together with the discussion of FIG10 and will not be described again herein.

In this paper, calibration circuit 80 first determines an arbitrary delay offset Δt (step 258). Next, calibration circuit 80 selects a calibrated frequency F_i (1≦i≦N) from the calibrated frequencies _{F ₁} - F_{_N} within the modulation bandwidth (step 260). Calibration circuit 80 then determines an arbitrary delay factor τ (step 264). Calibration circuit 80 then measures a pair of output powers P _{_OUT1} and P _{_OUT2} of power amplifier circuit 36 when power amplifier circuit 36 amplifies a test signal 82 generated at the selected calibrated frequency F_{_i} and delayed by τ±Δt (step 264).

The calibration circuit 80 checks whether a pair of output powers _POUT1 and _POUT2 are equal (step 266). In an embodiment, if the difference between a pair of output powers _POUT1 and _POUT2 is less than a predefined threshold, the calibration circuit 80 may consider a pair of output powers _POUT1 and _POUT2 to be equal.

If a pair of output powers P _OUT1 and P _OUT2 are equal, the calibration circuit 80 stores the selected calibrated frequency F _i in association with an arbitrary delay factor τ in the delay LUT 74 (step 268). Otherwise, the calibration circuit 80 returns to step 262 and determines a new arbitrary delay factor τ. If a pair of output powers P _OUT1 and P _OUT2 are still unequal after several iterations, the calibration circuit 80 may adjust (e.g., increase) a predefined threshold. It is worth noting that the calibration circuit 80 is configured to repeat steps 260-268 for each of the calibrated frequencies F ₁ - F _N.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims (20)

1. A transceiver circuit, comprising: Memory circuits; and A calibration circuit, coupled to a power amplifier circuit and configured to: A gain offset lookup table (LUT) is determined and stored in the memory circuit to correlate multiple calibrated frequencies within the modulation bandwidth of the power amplifier circuit with multiple gain offsets, respectively; and Determine the delay offset LUT and store it in the memory circuit to correlate the plurality of calibrated frequencies with the plurality of delay factors, respectively. 2. The transceiver circuit of claim 1, wherein each of the plurality of gain offsets is determined relative to a reference frequency within the modulation bandwidth. 3. The transceiver circuit according to claim 2, wherein the reference frequency corresponds to the center frequency of the modulation bandwidth. 4. The transceiver circuit according to claim 1, wherein the calibration circuit is further configured to: Determine the minimum reference voltage and minimum reference input power; Determine a reference frequency among the plurality of calibrated frequencies within the modulation bandwidth; The reference target voltage is determined based on the expected root mean square (RMS) of the modulated voltage to be provided to the power amplifier circuit for amplifying the radio frequency (RF) signal; and For each of the plurality of calibrated frequencies: The corresponding gain of the power amplifier circuit, which amplifies the test signal generated at the calibrated frequency and the determined minimum reference input power, is determined based on the determined minimum reference voltage. Determine the corresponding modulated voltage and corresponding input power that enable the power amplifier circuit to amplify the test signal at the calibrated frequency with the corresponding gain; and The corresponding modulated voltage is stored in a temporary voltage LUT in association with the corresponding input power. 5. The transceiver circuit of claim 4, wherein the calibration circuit is further configured to determine the minimum reference voltage and the minimum reference input power based on a trade-off between one or more of the following: The efficiency target of the power amplifier circuit; The noise target of the power amplifier circuit; and The linear target of the power amplifier circuit. 6. The transceiver circuit of claim 4, wherein, for each of the plurality of calibrated frequencies, the calibration circuit is further configured to: Determine the corresponding adjusted input power relative to the input power in the temporary voltage LUT associated with the modulated voltage equal to the reference target voltage; Determine a corresponding one of the plurality of gain offsets between the corresponding adjusted input power at the reference frequency and the corresponding adjusted input power at the calibrated frequency; and The corresponding calibrated frequency is stored in the gain offset LUT in association with the corresponding one of the plurality of gain offsets. 7. The transceiver circuit of claim 1, wherein the calibration circuit is further configured to: Determine the reference voltage and reference input power; Determine a reference frequency among the plurality of calibrated frequencies within the modulation bandwidth; The reference target voltage is determined based on the expected root mean square (RMS) of the modulated voltage to be provided to the power amplifier circuit for amplifying the radio frequency (RF) signal; and For each of the plurality of calibrated frequencies: The corresponding gain of the power amplifier circuit that amplifies the test signal generated at the calibrated frequency and the determined reference input power is determined based on the determined reference voltage. The corresponding gain is adjusted based on the determined compression gain to determine the compressed gain; It is determined that the power amplifier circuit will have the corresponding modulated voltage and corresponding input power with the compressed gain when amplifying the test signal at the calibrated frequency; and The corresponding modulated voltage and the corresponding input power are stored in a temporary voltage LUT. 8. The transceiver circuit of claim 7, wherein the calibration circuit is further configured to determine the reference voltage and the reference input power based on a trade-off between one or more of the following: The efficiency target of the power amplifier circuit; and The noise target of the power amplifier circuit. 9. The transceiver circuit of claim 7, wherein, for each of the plurality of calibrated frequencies, the calibration circuit is further configured to: Determine the corresponding adjusted input power relative to the input power in the temporary voltage LUT associated with the modulated voltage equal to the reference target voltage; Determine a corresponding one of the plurality of gain offsets between the corresponding input power at the reference frequency and the corresponding input power at the calibrated frequency; and The calibrated frequency is stored in the gain offset LUT in association with the corresponding one of the plurality of gain offsets. 10. The transceiver circuit of claim 1, wherein, for each of the plurality of calibrated frequencies, the calibration circuit is further configured to: Determine any delay factor; Measure the pair of output power of the power amplifier circuit when it amplifies a test signal generated at the corresponding calibrated frequency and delayed by the arbitrary delay factor minus the arbitrary delay offset and the arbitrary delay factor plus the arbitrary delay offset; and In response to the pair of output powers being equal, the corresponding calibrated frequency is stored in the delay LUT in association with the arbitrary delay factor. 11. The transceiver circuit of claim 10, wherein the calibration circuit is further configured to: A new arbitrary delay factor is determined in response to the inequality of the pair of output powers; Measure the new pair of output power generated by the power amplifier circuit at the corresponding calibrated frequency and delayed by the new arbitrary delay factor minus the arbitrary delay offset and the new arbitrary delay factor plus the arbitrary delay offset; and In response to the pair of output powers being equal, the corresponding calibrated frequency is stored in the delay LUT in association with the new arbitrary delay factor. 12. A method for calibrating equalization filtering in a transceiver circuit, comprising: Determine and store gain offset lookup tables (LUTs) to correlate multiple calibrated frequencies within the modulation bandwidth with multiple gain offsets, respectively; and Determine and store delay offset LUTs to correlate the plurality of calibrated frequencies with the plurality of delay factors, respectively. 13. The method of claim 12, further comprising determining each of the plurality of gain offsets relative to a reference frequency within the modulation bandwidth. 14. The method of claim 13, further comprising selecting the center frequency of the modulation bandwidth as the reference frequency. 15. The method of claim 12, further comprising: Determine the minimum reference voltage and minimum reference input power; Determine a reference frequency among the plurality of calibrated frequencies within the modulation bandwidth; The reference target voltage is determined based on the expected root mean square (RMS) of the modulated voltage to be supplied to the power amplifier circuit for amplifying the radio frequency (RF) signal; and For each of the plurality of calibrated frequencies: The corresponding gain of the power amplifier circuit, which amplifies the test signal generated at the calibrated frequency and the determined minimum reference input power, is determined based on the determined minimum reference voltage. Determine the corresponding modulated voltage and corresponding input power that enable the power amplifier circuit to have the corresponding gain when amplifying the test signal at the calibrated frequency; and The corresponding modulated voltage is stored in a temporary voltage LUT in association with the corresponding input power. 16. The method of claim 15, further comprising, for each of the plurality of calibrated frequencies: Determine the corresponding adjusted input power relative to the input power in the temporary voltage LUT associated with the modulated voltage equal to the target voltage; Determine a corresponding one of the plurality of gain offsets between the corresponding adjusted input power at the reference frequency and the corresponding adjusted input power at the calibrated frequency; and The corresponding calibrated frequency is stored in the gain offset LUT in association with the corresponding one of the plurality of gain offsets. 17. The method of claim 12, further comprising: Determine the reference voltage and reference input power; Determine a reference frequency among the plurality of calibrated frequencies within the modulation bandwidth; The reference target voltage is determined based on the expected root mean square (RMS) of the modulated voltage to be supplied to the power amplifier circuit for amplifying the radio frequency (RF) signal; and For each of the plurality of calibrated frequencies: The corresponding gain of the power amplifier circuit that amplifies the test signal generated at the calibrated frequency and the determined reference input power is determined based on the determined reference voltage. The corresponding gain is adjusted based on the determined compression gain to determine the compressed reference gain; and Determine the corresponding modulated voltage and corresponding input power that will enable the power amplifier circuit to amplify the test signal at the calibrated frequency with the compressed reference gain; and The corresponding modulated voltage and the corresponding input power are stored in a temporary voltage LUT. 18. The method of claim 17, further comprising, for each of the plurality of calibrated frequencies: Determine the corresponding adjusted input power relative to the input power in the temporary voltage LUT associated with the modulated voltage equal to the target voltage; Determine a corresponding one of the plurality of gain offsets between the corresponding input power at the reference frequency and the corresponding input power at the calibrated frequency; and The corresponding calibrated frequency is stored in the gain offset LUT in association with the corresponding one of the plurality of gain offsets. 19. The method of claim 12, further comprising, for each of the plurality of calibrated frequencies: Determine any delay factor; The measurement power amplifier circuit amplifies a pair of output powers when a test signal generated at the corresponding calibrated frequency and delayed by the arbitrary delay factor minus the arbitrary delay offset and the arbitrary delay factor plus the arbitrary delay offset; and In response to the pair of output powers being equal, the corresponding calibrated frequency is stored in the delay LUT in association with the arbitrary delay factor. 20. The method of claim 19, further comprising: A new arbitrary delay factor is determined in response to the inequality of the pair of output powers; Measure the new pair of output power generated by the power amplifier circuit at the corresponding calibrated frequency and delayed by the new arbitrary delay factor minus the arbitrary delay offset and the new arbitrary delay factor plus the arbitrary delay offset; and In response to the pair of output powers being equal, the corresponding calibrated frequency is stored in the delay LUT in association with the new arbitrary delay factor.