CN117134711A

CN117134711A - Doherty Power Amplifier System

Info

Publication number: CN117134711A
Application number: CN202310575624.5A
Authority: CN
Inventors: G·马克西姆; N·卡拉特; B·斯科特
Original assignee: Qorvo US Inc
Current assignee: Qorvo US Inc
Priority date: 2022-05-26
Filing date: 2023-05-22
Publication date: 2023-11-28

Abstract

A doherty amplifier system is disclosed. The doherty amplifier system comprises: a carrier amplifier having a carrier input and a carrier output; and a peak amplifier having a peak input coupled to the carrier input and a peak output coupled to the carrier output. Analog predistortion circuitry is configured to linearize the carrier amplifier and linearize the peak amplifier by compensating for base-to-collector capacitive loading of the carrier amplifier and the peak amplifier during operation.

Description

Doherty power amplifier system

RELATED APPLICATIONS

The present application claims the benefit of provisional patent application Ser. No. 63/411,792, filed on month 9, 2022, and provisional patent application Ser. No. 63/346,130, filed on month 5, 2022, 26, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to amplifiers, and in particular to improving linearity of Doherty-type (Doherty-type) amplifiers.

Background

Digital Predistortion (DPD) control of the power amplifier used in the primary phone provides good linearity performance at a trade-off of increased complexity and more complex system calibration. DPD control of power amplifiers is becoming a more popular method of linearizing power amplifiers while providing lower collector supply currents, in many cases comparable to envelope tracking system currents. One disadvantage of DPD control of a power amplifier is the need for a large DPD coefficient table that is needed to account for dynamic changes in the operating conditions of the power amplifier during DPD linearization. Non-memory and memory-based DPD linearization has been developed. The memory-less DPD linearization uses polynomials of different orders to provide predistortion that eliminates the inherent power amplifier distortion.

Typically, the baseband processor controls both the DPD linearization and the power management integrated circuit. Thus, the baseband processor has access to the current value of the average power tracking supply voltage, whereby the baseband processor can adjust the coefficients of the polynomial DPD to accommodate the different behavior of the power amplifier at different supply voltages.

Further, the baseband processor can access which communication channel is currently in operation and can change DPD coefficients depending on the operating channel frequency. Excess memory is required to store DPD linearization coefficients for a large matrix of operating conditions including, but not limited to, supply voltage, channel frequency, and collector current. For doherty power amplifiers, capturing supply and voltage standing wave ratio dependencies and using DPD coefficient sets to accommodate such dynamic operating conditions results in the need for a relatively very complex calibration system. Thus, there remains a need for doherty power amplifiers that are structured such that no complex calibration system is required.

Disclosure of Invention

In another aspect, any of the foregoing aspects, and/or the various individual aspects and features as described herein, may be combined singly or together to obtain additional advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

Those skilled in the art will recognize the scope of the present disclosure and appreciate additional aspects thereof upon reading the following detailed description of the preferred embodiments and the associated drawings.

Drawings

The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 is a schematic diagram of a first exemplary embodiment of a doherty power amplifier system structured to employ Digital Predistortion (DPD) and Analog Predistortion (APD) to provide linearization of the carrier and peak amplifiers making up the hybrid doherty amplifier.

Fig. 2 is a schematic diagram of a second exemplary embodiment of a doherty amplifier including digital input/output circuitry configured to interface a baseband processor with a calibration controller configured to control calibration of APD circuitry.

Fig. 3 is a schematic diagram of a third exemplary embodiment of a doherty amplifier in which APD circuitry provides both AM-AM linearization and AM-PM linearization with a relatively substantially higher control bandwidth compared to the signal modulation bandwidth.

Fig. 4 is a schematic diagram of an exemplary embodiment of a hybrid gallium arsenide-complementary metal oxide semiconductor (GaAs-CMOS) version of a doherty amplifier system, wherein the CMOS portion of the front end incorporates individual path gain and phase adjustment and optional digital register control and calibration.

Fig. 5 is a schematic diagram of an embodiment of a doherty power amplifier system illustrating the principle of baseband activation for doherty power amplifier APD linearization using a dedicated envelope-based activation path that includes time alignment.

Fig. 6 is a schematic diagram of an embodiment of a doherty power amplifier system illustrating the principle of baseband activation for doherty power amplifier APD linearization using a dedicated envelope-based activation path that includes time alignment.

Fig. 7A is a graph depicting a linear analog signal for peak power amplifier activation.

Fig. 7B is a graph of a nonlinear analog signal used to accelerate peak power amplifier activation.

Fig. 8A is an example of peak power amplifier activation alignment using analog predistortion threshold adjustment.

Fig. 8B is an example of peak power amplifier activation alignment using analog predistortion slope adjustment.

Fig. 9 is a schematic diagram of a wireless communication device incorporating the doherty amplifier system of the present disclosure.

Detailed Description

The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "over" or "extending over" another element, it can extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms, such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising" (comprises, comprising) and/or (includes, including) when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements may vary, and are expected to vary from the illustrated shapes due to, for example, manufacturing techniques and/or tolerances. For example, a region illustrated or described as square or rectangular may have rounded or curved features, and a region shown as a straight line may have some irregularities. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present disclosure. In addition, the size of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes, and thus structures or regions are provided to illustrate the general structures of the present invention and may or may not be drawn to scale. Common elements between the drawings may be shown with common element numbers herein and will not be described later.

Doherty power amplifiers are well known for their large distortion upon activation of the peak power amplifier. Digital Predistortion (DPD) -only linearization scheme is used to linearize the doherty power amplifier. However, such schemes are not apparent to any dynamic conditions under which the power amplifier may operate. These dynamic conditions, such as local power amplifier temperature, local power amplifier supply voltage, and load voltage standing wave ratio, can have a very large impact on the power amplifier distortion characteristics and are difficult to correct with DPD (and may require a large memory table). Furthermore, the nonlinearity from the base-to-collector capacitance (Cbc) loading is difficult to compensate at baseband level. It is much easier to correct for such nonlinear effects directly in the front-end using analog techniques.

The present disclosure relates to hybrid gallium arsenide (GaAs) -Complementary Metal Oxide Semiconductor (CMOS) doherty power amplifiers that are linearized using Analog Predistortion (APD) or digital and analog predistortion (DPD-APD). APD linearization mainly involves Cbc nonlinear loading effects that are easy to adjust and calibrate if the front-end driver is implemented in a CMOS die. The GaAs output stage die may have temperature sensors, supply voltage sensors, load sensors, process corner sensors, and may send detected signals to the CMOS front end to take action to correct for any such dynamic changes. The activation of the peak amplifier can be accomplished in two ways: a carrier power amplifier saturation detector with threshold and gain adjustment is used, or an envelope activation signal (analog or digital activation signal) from the baseband is used. The driver stage, inter-stage matching network with phase shift capability, and any crossover feed forward amplifier used for Cbc effect neutralization can be digitally controlled and calibrated. The hybrid analog and digital predistortion may have APD as the primary linearization or DPD as the primary linearization. These techniques may be applied to doherty power amplifiers based on average power tracking Power Management Integrated Circuits (PMICs) and doherty power amplifiers based on envelope tracking PMICs. The analog envelope signal may use linear or non-linear envelope dependencies and have additional shape adjustment blocks. The analog envelope signal may be used to drive a dynamic APD phase shift and/or a dynamic APD gain peak stage to linearize the doherty power amplifier.

The doherty power amplifier operated from APT PMIC supply may be an attractive alternative to standard power amplifiers operated with ET PMIC requiring very complex calibration and control schemes.

For a highly efficient doherty power amplifier, the key is the way the peak power amplifier is activated, and the correction of distortion resulting from the activation of the peak power amplifier by load modulation to increase efficiency. In general, embodiments of the present disclosure provide:

envelope tracking dynamic phase shift

Dedicated baseband dynamic phase shift

Internal dynamic phase shift controlled by the signal generated in the doherty power amplifier, for example by sensing saturation of the carrier power amplifier (when the peak power amplifier needs to be active).

The present disclosure includes doherty power amplifiers with single ended carrier and peak power amplifiers, differential carrier and peak power amplifiers, or a combination of single ended and differential stages. In a multi-stage doherty power amplifier, the driver stage and the output stage may be single ended or differential, or the multi-stage doherty power amplifier may have single ended drivers and differential output stages, and vice versa.

As depicted in fig. 1, the present disclosure relates to a doherty power amplifier system 10 that does not require a complex calibration system for the doherty power amplifier. In general, the disclosed doherty power amplifier system 10 employs amplifier linearization using analog techniques that include APD and DPD in a hybrid DPD-APD and APD-DPD structure. The disclosed doherty power amplifier system 10 and related method greatly reduce the size of memory required to store DPD coefficients while also greatly reducing the complexity of the doherty power amplifier calibration process.

In many cases, the baseband processor 12 with DPD circuitry 14 disposed in the baseband chipset needs to operate with various power amplifiers, often from different suppliers and with different characteristics. The baseband processor 12 needs to obtain a thorough characterization of each power amplifier used and calibration of DPD coefficients for each mode of operation.

The current doherty power amplifier system 10 is configured to employ DPD and APD to provide linearization of the carrier amplifier 16 and peak amplifier 18 that make up the hybrid doherty amplifier 20. Carrier driver stage 22 is coupled between RF input terminal 24 and carrier amplifier 16. The peak driver input stage 26 is coupled between the peak amplifier 18 and the RF input terminal 24 through a 90 deg. coupler/divider 28. An impedance inverter (impedance inverter) 30 is coupled between the outputs of the carrier and peak amplifiers 16, 18 and the RF output terminal 32. Hybrid doherty power amplifier 20 employs one or more methods to activate peak amplifier 18. The first method employed by the doherty power amplifier system 10 uses cross feed forward control that senses when the carrier power amplifier 16 begins to compress with the saturation detector 34 and in response generates a compression detection signal. APD circuitry 36 receives the compressed detection signal and, in response, activates peak amplifier 18 through peak driver input stage 26 to flatten the gain curve of peak amplifier 18. APD coefficient memory block 38 stores APD coefficients that APD circuitry 36 is configured to adjust the activation signal. APD circuitry provides both amplitude modulation-amplitude modulation (AM-AM) linearization and amplitude modulation-phase modulation (AM-PM) linearization.

A supply Voltage (VCC) detector 40 coupled to Average Power Tracking (APT) circuitry 42 is configured to generate a supply detector signal that is received by APD circuitry 36, which in response further adjusts the activation signal. Additional detectors include, but are not limited to, a Voltage Standing Wave (VSWR) detector 44 and a temperature detector 46. The VSWR detector 44 generates a VSWR signal that indicates the state of the VSWR of the amplified RF signal output from the RF output terminal 32. The temperature detector 46 generates a temperature signal proportional to the operating temperature of the hybrid doherty amplifier 20.

Hybrid DPD-APD circuitry 48 within baseband processor 12 is configured to receive the compression detection signal, the supply detector signal, the VSWR signal, and the temperature signal and to generate coefficient signals that select the appropriate DPD coefficients and activation points from DPD coefficient memory 50. The DPD coefficient memory 50 is in turn configured to pass the DPD coefficients to the DPD circuitry 14. Based on the DPD coefficients, DPD circuitry 14 drives Transmitter (TRX) circuitry 52 to predistort the RF signal input into RF input terminal 24. In the exemplary embodiment of fig. 1, the components comprising hybrid doherty amplifier 20, APD circuitry 36, APD coefficient memory block 38, saturation detector 34, VCC detector 40, VSWR detector 40, and temperature detector 46 constitute a front end module 54. Some components may be integrated into a CMOS die and other components may be integrated into a GaAs die. For example, the hybrid doherty amplifier 20 can be integrated into a GaAs die, and APD linearization can be driven by a dedicated CMOS Transmit (TX) controller, or can be integrated into a hybrid GaAs-CMOS version of the hybrid doherty amplifier 20 with APDs implemented in CMOS die, respectively.

Another approach employed by the hybrid doherty amplifier 20 uses a predefined direct baseband feed forward activation based on the hybrid doherty amplifier 20, which saves the activation point in the DPD coefficient memory 50 of the baseband processor 12. The baseband processor 12 uses the stored activation points to determine when the peak amplifier 18 needs to be activated under various environmental operating conditions, which may include, but are not limited to, VCC, operating temperature, and load VSWR.

In some cases, the activation signal is a linear analog signal for peak power amplifier activation. The lower slope of the activation signal results in a slower activation of the peak amplifier 18, while the higher slope results in a faster activation of the peak amplifier 18. In other cases, the activation signal is a nonlinear analog signal that is used to accelerate the peak power amplifier activation.

The activation of the peak amplifier 18 may be effected directly from the envelope signal provided by the baseband processor 12 or from an activation signal generated by an internal current, such as a saturation detection signal generated by the saturation detector 34. Additional shape processing may be used to optimize peak power amplifier activation. Predistortion of the envelope signal may be used. The non-linear activation as a function of the envelope characteristics results in an accelerated activation of the peak amplifier 18.

In some embodiments, the hybrid doherty power amplifier 20 with Complementary Metal Oxide Semiconductor (CMOS) front end allows mixed signal technology to control, adjust or calibrate the activation of the peak amplifier 18. Further, activation of peak amplifier 18 may be aligned using both APD threshold adjustment and APD slope adjustment, respectively. Furthermore, the slope adjustment and the threshold adjustment may be driven by a calibration circuit for linearization of the doherty power amplifier APD.

The use of the saturation detector 34 of the carrier amplifier 16 to activate the peak amplifier 18 does not always provide sufficient flexibility in adjusting the doherty power amplifier linearity performance. Any process variations and local mismatch, local temperature differences, and other environmental operating conditions may misalign the linearization with the inherent distortion of the power amplifier. Compensating for such effects may require providing an additional level of control over the activation of the peak amplifier 18.

Two components of the activation signal for peak amplifier 18 may be employed by doherty power amplifier system 10. The first component is a threshold adjustment that can move the envelope signal value up and down when the peak amplifier 18 is activated. The second component is the slope of the peak power amplifier activation, the speed of its activation, and the amount of load modulation it provides. This is the slope adjustment of the peak power amplifier activation signal.

Digital adjustment of both the threshold and slope of the activation signal of peak amplifier 18 helps to improve alignment of APD correction with the native distortion of carrier power amplifier 16. In this way, any offset in the saturation detector 34 may be compensated for, resulting in a higher linearity of the overall APD correction of the hybrid doherty amplifier 20.

Depending on the current operating band, the hybrid doherty amplifier 20 sees the input loading of different acoustic filters (not shown). This results in different compression characteristics for a large number of operating bands. The APD scheme with digital control allows for the local preservation of different APD coefficients for each operating band and deployment of such settings as a function of the given filter path selected.

For very wide radio bands, such as ultra-high band (UHB) B78, B79 bands, the loading on the hybrid doherty amplifier 20 can also vary significantly within a given frequency band. The digitally adjustable analog APD linearization provided by the doherty power amplifier system 10 can also use different APD coefficients for different sections of the wireless operating band. This gives a sub-band for APD linearization of the hybrid doherty amplifier 20. The baseband may convey the exact operating sub-band used to select APD coefficients to the front end.

APD linearization by a doherty power amplifier and hybrid analog and digital predistortion (APD-DPD) linearization of hybrid doherty amplifier 20, since one of the predistortion methods may be primary and one may be secondary, it is possible to have a hybrid APD-DPD embodiment or a hybrid DPD-APD embodiment.

The disclosed doherty power amplifier linearization method can include the following two methods. The first method is independent APD linearization, where all control of the APD is generated internally in front-end module 54. An optional baseband auxiliary control signal, e.g., frequency bands and subbands of operation, may be provided. The second approach is hybrid analog and DPD linearization, where the front end APD works with the baseband DPD.

When implementing hybrid DPD and APD doherty power amplifier linearization, one of the two linearization methods may be primary, while the other may be a secondary or auxiliary linearization scheme.

In general, DPD linearization is relatively better at compensating for memory effects and implementing higher order linearization schemes. Thus, in many cases it is advantageous to leave the baseband DPD as the primary linearization scheme, while APD linearization acts more as a support/auxiliary linearization that handles dynamic local variability, such as local temperature effects, load-VSWR effects, and local dynamic supply variation effects. Thus, the front end module 54 may include a number of local analog detectors that may sense power amplifier real-time temperature, dynamic changes in VCC, dynamic load VSWR changes, and the like. The local analog detectors of the exemplary embodiment of fig. 1 are the saturation detector 34, the VCC detector 40, the VSWR detector 44, and the temperature detector 46, and these constitute the front end module 54.

Reducing the range of variation of the non-linear power amplifier characteristics can result in a simple calibration procedure and smaller memory size required for DPD circuitry 14 because fewer sets of coefficients are required to cover the entire operating space, as many local dynamics are locally compensated for by the APD loop.

Several ways in which the doherty power amplifier system 10 can be partitioned include, but are not limited to, the following:

1. a conventional full GaAs power amplifier solution would have a carrier driver stage 22, carrier amplifier 16, peak driver input stage 26, and peak amplifier 18 integrated on a GaAs die, while a typical TX controller (not shown) is typically implemented using CMOS die. One major drawback of this conventional all GaAs power amplifier solution is the lack of direct contact with the Radio Frequency (RF) node from the CMOS side, where the primary interface between GaAs die and CMOS die is a dc bias signal.

2. The improved split according to the present disclosure is to use a hybrid GaAs-CMOS implementation where only the carrier amplifier 16 and peak amplifier 18 are integrated into the GaAs die, while the carrier driver stage 22, peak driver input stage 26, and APD circuitry 36 are integrated into the CMOS die. The improved splitting provides advantages in digital control and tunability (gain and phase tuning) of the power amplifier front-end, and access from the CMOS side to the RF nodes within the hybrid doherty amplifier 20.

As depicted in fig. 2, digital input/output (I/O) circuitry 56 is configured to interface baseband processor 12 with a calibration controller 58 configured to control calibration of APD circuitry 36. Calibration memory 60 is configured to store calibration data for APD circuitry 36. The calibration memory 60 is configured to communicate with the calibration controller 58. Integrating APD circuitry 36 with digital I/O circuitry 56, calibration controller 58, and calibration memory 60 in CMOS is relatively easier than GaAs. In contrast, in some embodiments, such as the exemplary embodiment of fig. 2, the saturation detector 34, the supply detector 40, and the temperature detector 46 are integrated in GaAs.

Digital I/O circuitry 56 provides an interface to the baseband DPD linearization scheme. Any detector signals may be passed to baseband processor 12 and processed by DPD circuitry 14 to enhance the digital DPD linearization scheme. For example, when a large change in the real-time temperature of the power amplifier is sensed, the DPD coefficients stored in the DPD coefficient memory 50 may change. Similarly, when the load VSWR has changed significantly, the DPD coefficient may change.

In the exemplary embodiment depicted in fig. 2, the phase adjustment in the carrier path is implemented with carrier interstage impedance matching circuitry 62 configured to adjust the phase of the first portion of the carrier signal in response to the first phase adjustment signal generated by APD circuitry 36. Similarly, phase adjustment in the peak path is implemented with peak interstage impedance matching circuitry 64 configured to adjust the phase of the second portion of the carrier signal in response to the second phase adjustment signal generated by APD circuitry 36. The first and second phase adjustment signals may be generated by APD circuitry 36 in response to any or all of the detector signals generated by analog detectors such as saturation detector 34, VCC detector 40, and temperature detector 46. Depending on the given application, the analog detector may be a linear sensor or

A nonlinear sensor.

The activation of the peak amplifier 18 may be triggered by the saturation detector 34 in various ways. In one mode of operation, only the bias of the peak amplifier 18 is boosted by the activation signal generated by the saturation detector 34, while the peak driver input stage 26 remains active. In this case, the activation signal drives the bias circuitry 65. In another mode of operation, the peak driver input stage 26 driving the peak amplifier 18 is configured for Variable Gain Amplifier (VGA) control based on an activation signal generated by the saturation detector 34 and processed by the APD circuitry 36. In the third mode of operation, both the bias and the variable gain of the peak driver input stage 26 are controlled by the activation signal generated by the saturation detector 34.

One of the main distortion effects in the doherty amplifier system comes from parasitic currents due to the base-to-collector capacitance (Cbc) of the peak amplifier 18 when on. To compensate for the Cbc loading of the peak power amplifier output stage, it is necessary to supply the current of Cbc through a path different from the peak path. This can be achieved by adding a feed forward amplifier tapped from the carrier amplifier input. The problem is that there is a time delay in the inter-stage matching network and the active stage. Such delays may shift the compensation current and time and cause it to appear at the wrong time, causing distortion.

A better solution is to tap the control of the crossover feed forward amplifier 66 for driving Cbc of the carrier amplifier 16 directly from the base of the peak amplifier 18, as shown in fig. 3. This avoids time delays and results in self-alignment correction. The neutralization current injected into Cbc of carrier amplifier 16 neutralizes the Cbc loading of carrier amplifier 16. In a similar manner, loading of Cbc from peak amplifier 18 may be neutralized by using a crossover feed forward amplifier 68 driven by a portion of the carrier signal at the base of carrier amplifier 16, as shown in fig. 3.

Although the two crossed feed forward neutralization amplifiers appear to be connected in a positive feedback loop, this is not the case, as the signals involved are not always present and do not have a phase relationship that results in positive feedback instability.

As depicted in fig. 3, the local dynamic loop through APD circuitry 36 provides faster control of hybrid doherty amplifier 20. In this regard, APD circuitry 36 that provides AM-AM linearization and AM-PM linearization has a relatively substantially higher control bandwidth than the signal modulation bandwidth. The control bandwidth needs to be 2 to 3 times the modulation bandwidth for the relevant section of APD circuitry 36 that provides AM-AM linearization, and 5 to 6 times the modulation bandwidth for the relevant section of APD circuitry 36 for AM-PM linearization. When the modulation bandwidth is 20MHz or 40MHz, the required current consumption and relatively low circuit complexity can be achieved. As the modulation bandwidth reaches 100MHz and above, it is relatively more difficult to achieve a control bandwidth of 500 MHz. For example, AM-AM gain boosting is limited by the relatively large ballast resistance required for thermal stability of the power amplifier. If the ballast resistance is reduced, a wide bandwidth of hundreds of megahertz may be implemented in the bias circuitry 65.

In this regard, embodiments of the present disclosure use a feedback ballast architecture in which a majority of the ballast resistors are placed inside the feedback loop of the bias circuitry 65, and only small ballast resistors are implemented outside the loop. The in-loop ballast resistance divided by the loop gain of the bias circuitry 65 and thus appears much smaller when contributing to the main control electrode at the input of the power amplifier output stage. The in-loop ballast resistor provides sufficient differential thermal stability between the different power cells of the power amplifier. The out-of-loop ballast resistance contributes to the global common mode thermal stability of the power amplifier. Furthermore, the saturation detector 34 as shown in fig. 3 has only a single device in the feedback path and thus achieves a very large bandwidth with only a small delay time.

In real world circuits there is a limited mismatch between carrier path and peak path gain and phase. This may come from device mismatch and a radically different local temperature level between the relatively hot carrier amplifier 16 operating at a high power level and the relatively cold peak amplifier 18 just at the moment the peak amplifier 18 is on. Having a hybrid GaAs-CMOS doherty power amplifier configuration allows easy adjustment and calibration of the gain and phase between the carrier and peak paths.

Fig. 4 shows an exemplary embodiment of a hybrid GaAs-CMOS version of doherty amplifier system 10, wherein the CMOS portion of the front end incorporates individual path gain and phase adjustment and optional digital register control and calibration.

Digital controller/driver 70 may readily implement specific registers for use in calibrating gain and phase matching through APD circuitry 36. Local memory in the front-end module TX controller (not shown) may be used to hold APD coefficients for various operating conditions:

different frequency bands or sub-bands

Different VCC levels

Different temperature levels

All of these linearization and calibration circuits are located in front of the carrier and peak power amplifier output stages and thus can be easily implemented in a CMOS die. This is done in CMOS, allowing its digital gain control to be done using special register settings in the digital I/O block. A local memory block may be used to hold all such APD coefficients for both the carrier and peak paths. The input and output phase shift circuits (lumped or transmission lines) may be implemented in a laminate or may be integrated on a die. The input phase splitting circuit on the CMOS side may also have digital trimming/adjusting circuitry. The signal level of the driver stage is not so high, allowing CMOS implementations without any particular drawbacks.

Given all of these calibration and APD circuitry, the high efficiency doherty power amplifier is not significantly simpler than the high efficiency ET power amplifier. However, an advantage is that complexity can be contained within the front-end module without exposure to the customer. Many original equipment manufacturers avoid using ET PMIC solutions, particularly because of their well-known complexity and difficulty of calibration and control.

APD AM-PM linearization can largely compensate for strong phase distortion that occurs when the peak amplifier is activated. This is one of the major obstacles to deploying doherty configuration in cellular applications that require very high linearity (e.g., 5G front end).

As described at the beginning of this disclosure, another way to activate the peak amplifier is to use an auxiliary control signal from baseband. The baseband knows when the envelope grows and thus the power amplifier will likely start to compress. This is when the peak amplifier needs to be activated. Either the analog or digital envelope activation signal may be used for the peak power amplifier.

Analog predistortion may be used to create a desired profile of the peak power amplifier control signal starting from an analog or digital envelope activation signal. The analog envelope activation signal is easier to use due to its continuous nature. However, running additional analog signals from baseband to front end is not always possible or desirable. This of course requires a significant change in the baseband architecture. Thus, not all base bands may support such an architecture. Any customization in the direction of the analog envelope signal may limit the front end modules for which the signal may be used.

In contrast, digital envelope activation signals are easier to use, but conventional digital I/O circuits may not have a sufficiently high clock frequency to provide well-aligned envelope digital control. Particularly in very wide modulation bandwidths (e.g., 100MHz or 200 MHz), conventional radio frequency front end interfaces cannot be used.

A dedicated high-speed digital signal may be used to activate the peak amplifier. This is more desirable than analog envelope signals that are more prone to noise coupling. If digital activation of the peak amplifier is used, digital and analog predistortion schemes are generated. All signal processing of the envelope activation signal may be performed in the analog front end. Alternatively, some signal processing, such as time delay of the digital activation signal, may be done in the baseband chip.

The envelope signal activation control may come directly from the baseband processor 12, where a hybrid DPD-APD linearization scheme may be implemented with digital components as the primary linearization scheme.

In such direct baseband peak power amplifier activation, one of three configurations may be used:

1. the driver of the peak amplifier is enabled at all times and the output peak stage is enabled from the activation signal provided by the baseband;

2. Having both the driver stage and the output stage of the peak amplifier activated by the envelope signal from baseband; and

3. the use of a variable gain amplifier/programmable gain amplifier gain control at the driver stage and letting the output stage rectify itself at high power to become a less desirable solution in operation is still possible.

Analog or digital activation using only a peak amplifier is not sufficient to obtain a highly linear doherty power amplifier for cellular applications. Additional linearization techniques need to be deployed to compensate for the distortion generated by the peak amplifier activation.

Furthermore, in this baseband-activated peak amplifier scheme, the drivers and interstage blocks are implemented in CMOS die, and thus may have gain and phase adjustment and calibration features. In this case APD is used to create the required control signal from the envelope activation signal provided by the baseband (analog or most likely digital). CMOS front-ends also allow for implementation of temperature, supply or even load dependent adjustments that are difficult to implement in GaAs.

The baseband may provide a dedicated activation signal for the peak power amplifier. A digital or analog activation signal may be used. In the case of ET PMIC, the baseband processor has provided an analog envelope tracking signal to the PMIC power management chip/module. This analog envelope dependent signal may be used to activate the peak power amplifier path.

In doherty power amplifiers, it is usually the phase distortion that dominates the error vector magnitude. The phase distortion of the doherty power amplifier is highly correlated with the activation of the peak power amplifier. Thus, the same analog envelope signal may be used to perform AM-PM phase linearization using the dynamic phase shift provided by either or both of carrier interstage impedance matching circuitry 62 and peak interstage impedance matching circuitry 64 configured for the dynamic phase shift.

In the embodiment depicted in fig. 4, the baseband processor 12 is configured to provide a separate analog envelope signal (es_a) and/or an envelope derivative/dependency signal (es_d). Additional signal shaping (predistortion) may be used to achieve the desired dynamic linearization control signal. In still other embodiments, the general dynamic phase shifter and/or the variable gain amplifier may be controlled by an activation signal.

The cross feed forward approach does not have stability problems, but the delay in the analog activation path is relatively important to ensure that the peak activation is aligned with the compression of the carrier amplifier 16. The cross feed forward method is particularly suitable for modulation bandwidths less than 100 MHz.

For signals with modulation bandwidths exceeding 100MHz, it may be more difficult to achieve a delay in the APD feed forward path that is small enough to maintain good linearity. In this case, the digitally adjustable time delay circuitry 72 may be used with direct digital activation synchronized with the modulation envelope of the signal.

Fig. 5 is a schematic diagram of an embodiment of the doherty power amplifier system 10 showing the principle of baseband activation for doherty power amplifier APD linearization using dedicated envelope-based activation paths that include time alignment, envelope signal shaping (on the baseband or on the front end side), and control for AM-AM and AM-PM APD linearization.

As depicted in fig. 5, baseband processor 12 includes an in-phase signal and quadrature signal (I/Q) modulator 76 configured to generate a digital in-phase signal and a digital quadrature signal from I/Q data.

The homogeneous digital-to-analog converter 78 is configured to convert digital data

The in-phase signal is converted to an analog in-phase signal and the quadrature digital-to-analog converter 80 is configured to convert a digital quadrature signal to an analog quadrature signal. The mixer 82 is configured to receive and mix the analog In-phase signal and the analog quadrature signal to produce an RF signal that is pre-amplified by a pre-amplifier 84 configured to output the pre-amplified RF signal to an RF input (RF In) of the hybrid doherty amplifier 20.

The time alignment between the dedicated envelope-based activation path containing the peak amplifier and the amplified RF signal is provided by a time alignment block 86 configured to delay or advance the reference signal output by the I/Q modulator in response to the I/Q data. The time alignment block 86 may be fabricated in digital circuitry such as logic gates or may be implemented by firmware or software processor instructions.

The alternative envelope shaping block 88 is configured to digitally generate and shape the envelope of the digital distortion compensation signal that controls APD circuitry 36 and bias circuitry 65. The compensation signal digital-to-analog converter 90 is configured to convert the digital distortion compensation signal to an analog compensation signal. Analog envelope shaping circuitry 92 is configured to shape the analog compensation signal in place of the substitute envelope shaping block 88 in applications where digital processing is not feasible due to bandwidth limitations. In some embodiments, the substitution envelope shaping block 88 and analog envelope shaping circuitry may work together in some embodiments to shape the compensation signal. Analog envelope shaping circuitry 92 may be fabricated from typical circuit elements such as diodes and/or transistors, and passive elements such as resistors, inductors, and capacitors.

The baseband may provide a dedicated activation signal for linearization of the doherty power amplifier APD. Digital and analog activation signals may be used. Baseband chipsets for APT applications typically do not have an envelope output.

In the case of a baseband chipset for an envelope tracking application, the baseband processor 12 provides an analog envelope tracking signal to the average power tracking power management integrated circuit 74. This analog envelope dependent signal may be reused to activate the peak power amplifier path.

In doherty power amplifiers, it is usually the phase distortion that dominates the error vector magnitude. The phase distortion of hybrid doherty amplifier 20 is highly correlated to the activation of peak power amplifier 18. Thus, the same analog envelope signal may be used to perform AM-PM phase linearization using a dynamic phase shifter.

The embodiment of fig. 5 provides:

● Envelope tracking dynamic phase shift

● Special baseband dynamic phase shift

● The internal dynamic phase shift, controlled by the signal generated in the doherty power amplifier, is controlled, for example, by sensing saturation of the carrier power amplifier (when the peak power amplifier needs to be active).

Fig. 6 is a schematic diagram of an embodiment doherty power amplifier system 10 showing the principle of baseband activation for doherty power amplifier APD linearization using dedicated envelope-based activation paths that include time alignment, envelope signal shaping (on the baseband or on the front end side), and control for AM-AM and AM-PM APD linearization.

The baseband processor 12 may provide a dedicated activation signal for linearization of the doherty power amplifier APD. A digital or analog activation signal may be used. Baseband chipsets for APT applications typically do not have an envelope output.

In the case of a baseband chipset for ET applications, baseband processor 12 has provided an analog ET signal to a PMIC power management chip/module, depicted as ET/APT PMIC 94. This analog envelope dependent signal may be reused to activate the peak power amplifier path.

In doherty power amplifiers, it is usually the phase distortion that dominates the error vector magnitude. The phase distortion of the doherty power amplifier is highly correlated with the activation of the peak power amplifier. Thus, the same analog envelope signal may be used to perform AM-PM phase linearization using a dynamic phase shifter.

A common dynamic phase shifter 96 may be placed at the RF In input of the doherty power amplifier (optional analog phase shifter shown In dashed lines). The dynamic phase shifter 96 is responsive to a phase Control (CTRL) signal derived from the envelope signal output from the compensation signal digital-to-analog converter 90. Another option is to have separate phase shifters 62 and 64 in the carrier and peak paths, which can apply a dynamic phase shift according to the envelope signal.

In yet another embodiment, the baseband may provide a separate analog envelope signal (or envelope derivation/dependency signal). Additional signal shaping (predistortion) may be used to achieve the desired dynamic linearization control signal. The embodiment of fig. 6 provides:

● Envelope tracking dynamic phase shift

● Special baseband dynamic phase shift

Fig. 7A is a graph depicting a linear analog signal for peak power amplifier activation. The lower the slope, the slower the activation, and the higher the slope, the faster the activation. Fig. 7B is a graph of a nonlinear analog signal used to accelerate peak power amplifier activation.

Fig. 8A and 8B are examples of peak power amplifier activation alignment using both APD threshold adjustment (fig. 8A) and APD slope adjustment (fig. 8B). The two alignments may be driven by a calibration circuit for linearization of the doherty power amplifier APD.

Referring to fig. 9, the concepts described above may be implemented in various types of wireless communication devices or user elements 98, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, etc., that support wireless communications, such as cellular, wireless Local Area Network (WLAN), bluetooth, and near field communications. The user element 98 will generally include a control system 100, a baseband processor 12, transmit circuitry 102, receive circuitry 104, antenna switching circuitry 106, a plurality of antennas 108, and user interface circuitry 110. Receive circuitry 104 receives radio frequency signals from one or more base stations via antenna 108 and through antenna switching circuitry 106. The low noise amplifier and the filter cooperate to amplify and cancel wideband interference from the received signal for processing. The filtered received signal is then down-converted to an intermediate or baseband frequency signal by down-conversion and digitizing circuitry (not shown) which then digitizes the signal into one or more digital streams.

The baseband processor 12 processes the digitized received signal to extract the information or data bits conveyed in the received signal. Such processing typically includes demodulation, decoding, and error correction operations. The baseband processor 12 is typically implemented in one or more Digital Signal Processors (DSPs) and Application Specific Integrated Circuits (ASICs). For transmission, the baseband processor 12 receives digitized data, which may represent voice, data, or control information, from the control system 100, which it encodes for transmission. The encoded data is output to transmit circuitry 102, where it is used by a modulator to modulate a carrier signal at a desired transmit frequency or frequencies. The doherty power amplifier system 10 amplifies the modulated carrier signal to a level suitable for transmission and delivers the modulated carrier signal to the antenna 108 through the antenna switching circuitry 106. Multiple antennas 108 and duplicated transmit circuitry 102 and receive circuitry 104 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

It is contemplated that any of the foregoing aspects may be combined and/or various individual aspects and features described herein to achieve additional advantages. Any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.

Claims

1. A doherty amplifier system, comprising:

● A carrier amplifier having a carrier input and a carrier output;

● A peak amplifier having a peak input coupled to the carrier input and a peak output coupled to the carrier output; and

● Analog Predistortion (APD) circuitry configured to linearize the carrier amplifier and linearize the peak amplifier by compensating for base-to-collector capacitance (Cbc) loading of the carrier amplifier and the peak amplifier during operation.

2. The doherty amplifier system of claim 1 further comprising:

● An input impedance inverter coupled between the carrier input and the peak input; and

● An output impedance inverter coupled between the carrier output and the peak output.

3. The doherty amplifier system of claim 2 further comprising:

● A carrier driver input stage having a carrier driver output coupled to the carrier input; and

● A peak driver input stage having a peak driver output coupled to the peak input.

4. The doherty amplifier system of claim 3 wherein the carrier driver input stage and the peak driver input stage are of the Complementary Metal Oxide Semiconductor (CMOS) type.

5. The doherty amplifier system of claim 1 wherein the carrier amplifier and the peak amplifier are of the bipolar type.

6. The doherty amplifier system of claim 1 wherein the APD circuitry is configured to adjust a gain of a carrier amplification path comprising the carrier amplifier in response to a detector.

7. The doherty amplifier system of claim 1 wherein the APD circuitry is configured to adjust a gain of a peak amplification path containing the peak amplifier in response to a detector.

8. The doherty amplifier system of claim 1 wherein the APD circuitry is configured to adjust a gain of a carrier amplification path containing the carrier amplifier and adjust a gain of a peak amplification path containing the peak amplifier in response to a sensor.

9. The doherty amplifier system of claim 1 further comprising Digital Predistortion (DPD) circuitry configured to linearize the carrier amplifier and linearize the peak amplifier by compensating Cbc loading of the carrier amplifier and the peak amplifier during operation.

10. The doherty amplifier system of claim 9 wherein the APD circuitry and the DPD circuitry are configured to substantially equally compensate Cbc loading the carrier amplifier and the peak amplifier.

11. The doherty amplifier system of claim 9, wherein the APD circuitry is configured to provide greater than 50% of the compensation of Cbc loading of the carrier amplifier and the peak amplifier as compared to the DPD circuitry.

12. The doherty amplifier system of claim 9, wherein the DPD circuitry is configured to provide greater than 50% of the compensation of Cbc loading of the carrier amplifier and the peak amplifier as compared to the APD circuitry.

13. The doherty amplifier system of claim 1 further comprising:

● An in-phase/quadrature (I/Q) modulator configured to generate a digital RF signal and a distortion compensation signal; and

● A time alignment block configured to align the distortion compensation signal with the RF signal.

14. The doherty amplifier system of claim 13, further comprising an envelope shaping block configured to digitally generate and shape an envelope of the distortion compensation signal that controls the APD circuitry.

15. The doherty amplifier system of claim 14, further comprising bias circuitry configured to generate a bias for the peak amplifier in response to the distortion compensation signal.

16. The doherty amplifier system of claim 14 wherein the envelope shaping block is configured to output the compensation signal to an envelope tracking/average power tracking power management integrated circuit.

17. A method of operating a doherty amplifier system, comprising:

● Providing a carrier amplifier having a carrier input and a carrier output;

● Providing a peak amplifier having a peak input coupled to the carrier input and a peak output coupled to the carrier output;

● Providing Analog Predistortion (APD) circuitry; and

● The carrier amplifier is linearized by means of the APD circuitry compensating for base-to-collector capacitance (Cbc) loading of the carrier amplifier during operation.

18. The method of operating a doherty amplifier system of claim 17, further comprising: the peak amplifier is linearized by means of the APD circuitry compensating Cbc loading of the peak amplifier during operation.

19. The method of operating a doherty amplifier system of claim 18 further comprising providing Digital Predistortion (DPD) circuitry configured to linearize the carrier amplifier and linearize the peak amplifier by means of the DPD circuitry compensating Cbc loading of the carrier amplifier and the peak amplifier during operation.

20. The method of operating a doherty amplifier system of claim 19 wherein the APD circuitry and the DPD circuitry substantially equally compensate for the Cbc loading of the carrier amplifier and the peak amplifier.

21. The method of operating a doherty amplifier system of claim 17 comprising:

● Providing a baseband processor including an in-phase/quadrature (I/Q) modulator and a time alignment block;

● Generating a digital RF signal and a distortion compensation signal using the I/Q modulator;

● The distortion compensation signal is aligned with the RF signal using the time alignment block.

22. The method of operating a doherty amplifier system of claim 21, further comprising:

● Providing an envelope shaping block;

● Digitally generating and shaping an envelope of the distortion compensation signal with the envelope shaping block;

● The APD circuitry is controlled using the shaped envelope of the distortion compensation signal.

23. The method of operating a doherty amplifier system of claim 22, further comprising:

● Providing bias circuitry for the peak amplifier;

● The bias circuitry is used to generate a bias for the peak amplifier in response to the distortion compensation signal.

24. The method of operating a doherty amplifier system of claim 21, further comprising:

● Configuring the envelope shaping block to output the compensation signal;

● The output compensation signal is sent to an envelope tracking/average power tracking power management integrated circuit.

25. The wireless communication device of claim 21, further comprising Digital Predistortion (DPD) circuitry configured to linearize the carrier amplifier and linearize the peak amplifier by compensating Cbc loading of the carrier amplifier and the peak amplifier during operation.

26. The wireless communication apparatus of claim 25, wherein the APD circuitry and the DPD circuitry are configured to substantially equally compensate Cbc loading of the carrier amplifier and the peak amplifier.

27. The wireless communication apparatus of claim 25, wherein the APD circuitry is configured to provide greater than 50% of the compensation of Cbc loading of the carrier amplifier and the peak amplifier as compared to the DPD circuitry.

28. The wireless communication apparatus of claim 25, wherein the DPD circuitry is configured to provide greater than 50% of the compensation of Cbc loading of the carrier amplifier and the peak amplifier as compared to the APD circuitry.

29. The wireless communication device of claim 25, wherein the baseband processor comprises:

30. The wireless communication device of claim 29, further comprising an envelope shaping block configured to digitally generate and shape an envelope of the distortion compensation signal that controls the APD circuitry.

31. The wireless communication device of claim 30, further comprising bias circuitry configured to generate a bias for the peak amplifier in response to the distortion compensation signal.

32. The wireless communication device of claim 30, wherein the envelope shaping block is configured to output the compensation signal to an envelope tracking/average power tracking power management integrated circuit.

33. A wireless communication device, comprising:

● A baseband processor;

● Transmit circuitry configured to receive encoded data from the baseband processor and modulate a carrier signal with the encoded data, wherein the transmit circuitry comprises:

● A carrier amplifier having a carrier input configured to receive the carrier signal and a carrier output;

● APD circuitry configured to linearize the carrier amplifier and linearize the peak amplifier by compensating for base-to-collector capacitance (Cbc) loading of the carrier amplifier and the peak amplifier during operation; and

● At least one antenna coupled to the transmit circuitry to transmit the carrier signal.

34. The wireless communication device of claim 33, wherein the APD circuitry is configured to adjust a gain of a carrier amplification path including the carrier amplifier in response to a detector.

35. The wireless communication device of claim 33, wherein the APD circuitry is configured to adjust a gain of a peak amplification path including the peak amplifier in response to a detector.

36. The wireless communication device of claim 33, wherein the APD circuitry is configured to adjust a gain of a carrier amplification path including the carrier amplifier and adjust a gain of a peak amplification path including the peak amplifier in response to a sensor.