HK24196A - Methods and apparatus for maintaining cache integrity - Google Patents

Methods and apparatus for maintaining cache integrity

Info

Publication number
HK24196A
HK24196A HK24196A HK24196A HK24196A HK 24196 A HK24196 A HK 24196A HK 24196 A HK24196 A HK 24196A HK 24196 A HK24196 A HK 24196A HK 24196 A HK24196 A HK 24196A
Authority
HK
Hong Kong
Prior art keywords
methods
maintaining cache
cache integrity
integrity
maintaining
Prior art date
Application number
HK24196A
Other languages
English (en)
Inventor
Son Hung Lam
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of HK24196A publication Critical patent/HK24196A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
HK24196A 1990-10-26 1996-02-08 Methods and apparatus for maintaining cache integrity HK24196A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/604,837 US5193170A (en) 1990-10-26 1990-10-26 Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram

Publications (1)

Publication Number Publication Date
HK24196A true HK24196A (en) 1996-02-16

Family

ID=24421248

Family Applications (1)

Application Number Title Priority Date Filing Date
HK24196A HK24196A (en) 1990-10-26 1996-02-08 Methods and apparatus for maintaining cache integrity

Country Status (9)

Country Link
US (1) US5193170A (xx)
EP (1) EP0482752B1 (xx)
JP (1) JPH0797353B2 (xx)
KR (1) KR950013261B1 (xx)
CN (1) CN1024599C (xx)
AU (1) AU652178B2 (xx)
CA (1) CA2052766C (xx)
DE (1) DE69109803T2 (xx)
HK (1) HK24196A (xx)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0510242A2 (en) * 1991-04-22 1992-10-28 Acer Incorporated System and method for managing the routing execution in a computer system
US5319768A (en) * 1991-05-01 1994-06-07 Sgs-Thomson Microelectronics, Inc. Control circuit for resetting a snoop valid bit in a dual port cache tag memory
US5341487A (en) * 1991-12-20 1994-08-23 International Business Machines Corp. Personal computer having memory system with write-through cache and pipelined snoop cycles
US5966728A (en) * 1992-01-02 1999-10-12 International Business Machines Corp. Computer system and method for snooping date writes to cacheable memory locations in an expansion memory device
US5724549A (en) * 1992-04-06 1998-03-03 Cyrix Corporation Cache coherency without bus master arbitration signals
US5313593A (en) * 1992-09-17 1994-05-17 International Business Machines Corp. Personal computer system with bus noise rejection
US5603011A (en) * 1992-12-11 1997-02-11 International Business Machines Corporation Selective shadowing and paging in computer memory systems
US5526512A (en) * 1993-09-20 1996-06-11 International Business Machines Corporation Dynamic management of snoop granularity for a coherent asynchronous DMA cache
CN1052550C (zh) * 1993-09-20 2000-05-17 国际商业机器公司 对高速缓冲存储器探测粒度的动态管理
DE69429777T2 (de) * 1993-09-30 2002-10-17 Apple Computer System zur dezentralen massenspeichersteuerung eines rechners mit virtuellem speicher
US5526503A (en) * 1993-10-06 1996-06-11 Ast Research, Inc. Virtual addressing buffer circuit
US6421776B1 (en) * 1994-10-14 2002-07-16 International Business Machines Corporation Data processor having BIOS packing compression/decompression architecture
US5617557A (en) * 1994-11-14 1997-04-01 Compaq Computer Corporation Using an address pin as a snoop invalidate signal during snoop cycles
EP0735481B1 (en) * 1995-03-31 2003-05-14 Sun Microsystems, Inc. System level mechanism for invalidating data stored in the external cache of a processor in a computer system
US5652859A (en) * 1995-08-17 1997-07-29 Institute For The Development Of Emerging Architectures, L.L.C. Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues
US5940850A (en) * 1996-10-31 1999-08-17 International Business Machines Corporation System and method for selectively enabling load-on-write of dynamic ROM data to RAM
US5900017A (en) * 1997-05-14 1999-05-04 International Business Machines Corporation Snooping a variable number of cache addresses in a multiple processor system by a single snoop request
US6003103A (en) * 1997-09-30 1999-12-14 Micron Electronics, Inc. Method for attachment or integration of a bios device into a computer system using a local bus
US6076118A (en) * 1997-09-30 2000-06-13 Micron Electronics, Inc. Attachment or integration of a BIOS device into a computer system using the system memory address and data bus
US6182213B1 (en) 1997-09-30 2001-01-30 Micron Electronics, Inc. Method for attachment of a bios device into a computer system using the system memory data bus
US6009522A (en) * 1997-09-30 1999-12-28 Micron Electronics, Inc. Attachment or integration of a BIOS device into a computer system using the system memory data bus
TW480404B (en) * 1999-08-31 2002-03-21 Ibm Memory card with signal processing element
JP4097883B2 (ja) * 2000-07-04 2008-06-11 松下電器産業株式会社 データ転送装置および方法
EP1320035A1 (en) * 2001-12-11 2003-06-18 Thomson Licensing S.A. Storage device cache management
US20130124800A1 (en) * 2010-07-27 2013-05-16 Freescale Semiconductor, Inc. Apparatus and method for reducing processor latency

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4392200A (en) * 1980-01-28 1983-07-05 Digital Equipment Corporation Cached multiprocessor system with pipeline timing
JPS59121677A (ja) * 1982-12-28 1984-07-13 Mitsubishi Electric Corp 記憶装置
JPS6115252A (ja) * 1984-06-29 1986-01-23 Mitsubishi Electric Corp 主記憶デイスク装置
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
JPS63308653A (ja) * 1987-06-10 1988-12-16 Fujitsu Ltd ブロック・イン方式
US5091850A (en) * 1987-09-28 1992-02-25 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
EP0309995B1 (en) * 1987-09-28 1994-11-30 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
JPH083803B2 (ja) * 1987-12-25 1996-01-17 株式会社日立製作所 Ｎｍｉ処理方法
JPH01303546A (ja) * 1988-05-31 1989-12-07 Nec Corp メモリ制御方式
JP2613258B2 (ja) * 1988-06-08 1997-05-21 株式会社日立製作所 情報処理方法及び装置
US5119485A (en) * 1989-05-15 1992-06-02 Motorola, Inc. Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation

Also Published As

Publication number Publication date
JPH0581128A (ja) 1993-04-02
KR950013261B1 (ko) 1995-10-26
AU8482491A (en) 1992-04-30
JPH0797353B2 (ja) 1995-10-18
EP0482752A3 (en) 1992-07-08
CA2052766C (en) 1996-01-02
CA2052766A1 (en) 1992-04-27
KR920008601A (ko) 1992-05-28
EP0482752B1 (en) 1995-05-17
US5193170A (en) 1993-03-09
CN1024599C (zh) 1994-05-18
AU652178B2 (en) 1994-08-18
CN1060916A (zh) 1992-05-06
DE69109803D1 (de) 1995-06-22
DE69109803T2 (de) 1995-11-30
EP0482752A2 (en) 1992-04-29

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Legal Events

Date Code Title Description
PF Patent in force
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20060916