HK127896A - A fully decoded multistage leading zero detector and normalization apparatus - Google Patents

A fully decoded multistage leading zero detector and normalization apparatus

Info

Publication number
HK127896A
HK127896A HK127896A HK127896A HK127896A HK 127896 A HK127896 A HK 127896A HK 127896 A HK127896 A HK 127896A HK 127896 A HK127896 A HK 127896A HK 127896 A HK127896 A HK 127896A
Authority
HK
Hong Kong
Prior art keywords
leading zero
zero detector
fully decoded
normalization apparatus
multistage leading
Prior art date
Application number
HK127896A
Other languages
English (en)
Inventor
Jack T Poon
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of HK127896A publication Critical patent/HK127896A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/012—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising in floating-point computations

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
HK127896A 1992-01-06 1996-07-18 A fully decoded multistage leading zero detector and normalization apparatus HK127896A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/817,302 US5241490A (en) 1992-01-06 1992-01-06 Fully decoded multistage leading zero detector and normalization apparatus

Publications (1)

Publication Number Publication Date
HK127896A true HK127896A (en) 1996-07-26

Family

ID=25222769

Family Applications (1)

Application Number Title Priority Date Filing Date
HK127896A HK127896A (en) 1992-01-06 1996-07-18 A fully decoded multistage leading zero detector and normalization apparatus

Country Status (5)

Country Link
US (1) US5241490A (xx)
JP (1) JPH06236252A (xx)
GB (1) GB2263001B (xx)
HK (1) HK127896A (xx)
SG (1) SG42990A1 (xx)

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DE69317602T2 (de) * 1992-01-24 1998-10-01 Digital Equipment Corp Paritäts-und hochgeschwindigkeitsnormierungskreis für ein massivparalleles verarbeitungssystem
EP0800133A1 (en) * 1992-01-24 1997-10-08 Digital Equipment Corporation Databus parity and high speed normalization circuit for a massively parallel processing system
US5915054A (en) * 1992-03-05 1999-06-22 Fuji Xerox Co., Ltd. Star coupler for an optical communication network
US5375078A (en) * 1992-12-15 1994-12-20 International Business Machines Corporation Arithmetic unit for performing XY+B operation
GB2274224B (en) * 1993-01-07 1997-02-26 Sony Broadcast & Communication Data compression
US5390134A (en) * 1993-01-29 1995-02-14 Hewlett-Packard Company System and method for reducing latency in a floating point processor
US5485476A (en) * 1993-06-14 1996-01-16 International Business Machines Corporation Method and system for error tolerant synchronization character detection in a data storage system
US5392228A (en) * 1993-12-06 1995-02-21 Motorola, Inc. Result normalizer and method of operation
US5673407A (en) * 1994-03-08 1997-09-30 Texas Instruments Incorporated Data processor having capability to perform both floating point operations and memory access in response to a single instruction
US5574670A (en) * 1994-08-24 1996-11-12 Advanced Micro Devices, Inc. Apparatus and method for determining a number of digits leading a particular digit
US5568410A (en) 1994-09-29 1996-10-22 International Business Machines Corporation Method and apparatus for determining the amount of leading zeros or ones in a binary data field
US5576982A (en) * 1994-10-17 1996-11-19 Unisys Corporation Fast significant bit calculator and its application to integer multiplication and division
US5668984A (en) * 1995-02-27 1997-09-16 International Business Machines Corporation Variable stage load path and method of operation
RU95107478A (ru) * 1995-05-18 1997-02-10 А.И. Грушин Способ устранения старших незначащих цифр при вычислениях с плавающей запятой и устройство для его осуществления
US5831877A (en) * 1995-05-26 1998-11-03 National Semiconductor Corporation Bit searching through 8, 16, or 32 bit operands using a 32 bit data path
US5808926A (en) * 1995-06-01 1998-09-15 Sun Microsystems, Inc. Floating point addition methods and apparatus
US5633819A (en) * 1995-10-24 1997-05-27 Exponential Technology, Inc. Inexact leading-one/leading-zero prediction integrated with a floating-point adder
US5798958A (en) * 1996-06-05 1998-08-25 Samsung Electronics Co., Ltd. Zero detect for binary sum
US5844830A (en) * 1996-08-07 1998-12-01 Sun Microsystems, Inc. Executing computer instrucrions by circuits having different latencies
US6018757A (en) * 1996-08-08 2000-01-25 Samsung Electronics Company, Ltd. Zero detect for binary difference
US5880978A (en) * 1996-08-20 1999-03-09 Intel Corporation Method and apparatus for creating an output vector from an input vector
US5940625A (en) * 1996-09-03 1999-08-17 Cray Research, Inc. Density dependent vector mask operation control apparatus and method
US5923574A (en) * 1996-09-18 1999-07-13 International Business Machines Corporation Optimized, combined leading zeros counter and shifter
US5844826A (en) * 1996-10-18 1998-12-01 Samsung Electronics Co., Ltd. Leading zero count circuit
US6108678A (en) * 1998-05-05 2000-08-22 Mentor Graphics Corporation Method and apparatus to detect a floating point mantissa of all zeros or all ones
US6058403A (en) * 1998-08-06 2000-05-02 Intel Corporation Broken stack priority encoder
US6173300B1 (en) 1998-08-11 2001-01-09 Advanced Micro Devices, Inc. Method and circuit for determining leading or trailing zero count
US6513053B1 (en) 2000-01-12 2003-01-28 Arm Limited Data processing circuit and method for determining the first and subsequent occurences of a predetermined value in a sequence of data bits
US6593778B1 (en) 2000-09-05 2003-07-15 Intel Corporation Zero detect circuit and method for high frequency integrated circuits
EP1686694A3 (en) * 2001-01-31 2006-12-13 Matsushita Electric Industrial Co., Ltd. Decoding devices and decoding method f
KR100486255B1 (ko) * 2002-08-28 2005-05-03 삼성전자주식회사 데이터 검출회로 및 데이터 검출 방법
US7991947B2 (en) 2002-12-30 2011-08-02 Micron Technology, Inc. Multi-priority encoder
US8209366B2 (en) * 2005-02-28 2012-06-26 Hitachi Global Storage Technologies Netherlands B.V. Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations
US7516252B2 (en) * 2005-06-08 2009-04-07 Intel Corporation Port binding scheme to create virtual host bus adapter in a virtualized multi-operating system platform environment
US20070050435A1 (en) * 2005-08-30 2007-03-01 Christian Jacobi Leading-Zero Counter and Method to Count Leading Zeros
JP4232838B2 (ja) * 2007-03-29 2009-03-04 日本電気株式会社 再構成可能なｓｉｍｄ型プロセッサ
US8631056B2 (en) * 2008-01-09 2014-01-14 Qualcomm Incorporated Processor and method of determining a normalization count
US8788549B2 (en) * 2011-05-02 2014-07-22 Saankhya Labs Private Limited Zero overhead block floating point implementation in CPU's
US8954833B2 (en) * 2012-06-06 2015-02-10 International Business Machines Corporation Half width counting leading zero circuit using comparators
GB2587040B (en) 2020-02-28 2022-03-02 Imagination Tech Ltd Look ahead normaliser

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Publication number Priority date Publication date Assignee Title
US4064421A (en) * 1976-07-22 1977-12-20 Burroughs Corporation High speed modular arithmetic apparatus having a mask generator and a priority encoder
JPS59216245A (ja) * 1983-05-25 1984-12-06 Nec Corp 正規化回路
JPS62229436A (ja) * 1986-03-31 1987-10-08 Toshiba Corp 二進数デ−タ判別回路
JPH0746310B2 (ja) * 1987-06-30 1995-05-17 三菱電機株式会社 半導体論理回路
US4979141A (en) * 1988-09-28 1990-12-18 Data General Corporation Technique for providing a sign/magnitude subtraction operation in a floating point computation unit
US5111415A (en) * 1989-11-06 1992-05-05 Hewlett-Packard Company Asynchronous leading zero counter employing iterative cellular array

Also Published As

Publication number Publication date
SG42990A1 (en) 1997-10-17
US5241490A (en) 1993-08-31
JPH06236252A (ja) 1994-08-23
GB9226829D0 (en) 1993-02-17
GB2263001A (en) 1993-07-07
GB2263001B (en) 1996-03-13

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