HK1216200A1 - 具有早期解碼終止檢測的解碼器 - Google Patents

具有早期解碼終止檢測的解碼器

Info

Publication number
HK1216200A1
HK1216200A1 HK16104181.3A HK16104181A HK1216200A1 HK 1216200 A1 HK1216200 A1 HK 1216200A1 HK 16104181 A HK16104181 A HK 16104181A HK 1216200 A1 HK1216200 A1 HK 1216200A1
Authority
HK
Hong Kong
Prior art keywords
decoder
early decoding
termination detection
decoding termination
detection
Prior art date
Application number
HK16104181.3A
Other languages
English (en)
Inventor
.陸
.蒲
Original Assignee
Western Digital Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/918,400 external-priority patent/US20140223255A1/en
Application filed by Western Digital Tech Inc filed Critical Western Digital Tech Inc
Publication of HK1216200A1 publication Critical patent/HK1216200A1/zh

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148Structural properties of the code parity-check or generator matrix
    • H03M13/116Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1128Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1131Scheduling of bit node or check node processing
    • H03M13/1137Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105Decoding
    • H03M13/1131Scheduling of bit node or check node processing
    • H03M13/114Shuffled, staggered, layered or turbo decoding schedules
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6508Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65Purpose and implementation aspects
    • H03M13/6561Parallelized implementations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1191Codes on graphs other than LDPC codes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
HK16104181.3A 2013-04-30 2016-04-13 具有早期解碼終止檢測的解碼器 HK1216200A1 (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201361817421P 2013-04-30 2013-04-30
US13/918,400 US20140223255A1 (en) 2012-12-18 2013-06-14 Decoder having early decoding termination detection
PCT/US2014/036255 WO2014179502A1 (en) 2013-04-30 2014-04-30 Decoder having early decoding termination detection

Publications (1)

Publication Number Publication Date
HK1216200A1 true HK1216200A1 (zh) 2016-10-21

Family

ID=51843935

Family Applications (1)

Application Number Title Priority Date Filing Date
HK16104181.3A HK1216200A1 (zh) 2013-04-30 2016-04-13 具有早期解碼終止檢測的解碼器

Country Status (5)

Country Link
EP (1) EP2992429B1 (zh)
KR (1) KR101913900B1 (zh)
CN (1) CN105164646B (zh)
HK (1) HK1216200A1 (zh)
WO (1) WO2014179502A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9595977B2 (en) 2014-09-29 2017-03-14 Apple Inc. LDPC decoder with efficient circular shifters
US10128869B2 (en) 2016-05-17 2018-11-13 Apple Inc. Efficient convergence in iterative decoding
WO2018042597A1 (ja) * 2016-09-01 2018-03-08 三菱電機株式会社 誤り訂正復号装置及び光送受信装置
US10606694B2 (en) * 2018-04-20 2020-03-31 Micron Technology, Inc. Error correction using hierarchical decoders
CN108683426B (zh) * 2018-05-18 2022-08-26 中国科学院微电子研究所 一种基于bch码的ecc系统及存储器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7904793B2 (en) * 2007-03-29 2011-03-08 Sandisk Corporation Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US8127209B1 (en) * 2007-07-30 2012-02-28 Marvell International Ltd. QC-LDPC decoder with list-syndrome decoding
US20090113256A1 (en) * 2007-10-24 2009-04-30 Nokia Corporation Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding
WO2010019169A1 (en) 2008-08-15 2010-02-18 Lsi Corporation Rom list-decoding of near codewords
US8578256B2 (en) * 2009-04-22 2013-11-05 Agere Systems Llc Low-latency decoder
US8392789B2 (en) * 2009-07-28 2013-03-05 Texas Instruments Incorporated Method and system for decoding low density parity check codes
TWI419481B (zh) * 2009-12-31 2013-12-11 Nat Univ Tsing Hua 低密度奇偶檢查碼編解碼器及其方法
US8572463B2 (en) * 2010-02-01 2013-10-29 Sk Hynix Memory Solutions Inc. Quasi-cyclic LDPC encoding and decoding for non-integer multiples of circulant size
US8499226B2 (en) * 2010-06-29 2013-07-30 Lsi Corporation Multi-mode layered decoding
US8661326B1 (en) * 2010-08-04 2014-02-25 Marvell International Ltd. Non-binary LDPC code decoding early termination
KR101854954B1 (ko) * 2011-07-29 2018-05-04 샌디스크 테크놀로지스 엘엘씨 치환 소행렬의 합을 사용하는 체크섬
US8775896B2 (en) * 2012-02-09 2014-07-08 Lsi Corporation Non-binary LDPC decoder with low latency scheduling

Also Published As

Publication number Publication date
EP2992429B1 (en) 2022-03-09
KR101913900B1 (ko) 2018-10-31
KR20160004338A (ko) 2016-01-12
EP2992429A1 (en) 2016-03-09
EP2992429A4 (en) 2016-12-14
CN105164646B (zh) 2019-06-07
CN105164646A (zh) 2015-12-16
WO2014179502A1 (en) 2014-11-06

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