HK1211102A1 - 種數據處理方法及處理器 - Google Patents

種數據處理方法及處理器

Info

Publication number
HK1211102A1
HK1211102A1 HK15111785.9A HK15111785A HK1211102A1 HK 1211102 A1 HK1211102 A1 HK 1211102A1 HK 15111785 A HK15111785 A HK 15111785A HK 1211102 A1 HK1211102 A1 HK 1211102A1
Authority
HK
Hong Kong
Prior art keywords
processor
processing data
data
processing
Prior art date
Application number
HK15111785.9A
Other languages
English (en)
Inventor
馬凌
姚四海
張磊
Original Assignee
Alibaba Group Holding Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alibaba Group Holding Ltd filed Critical Alibaba Group Holding Ltd
Publication of HK1211102A1 publication Critical patent/HK1211102A1/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28—Using a specific disk cache architecture
    • G06F2212/283—Plural cache memories
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
HK15111785.9A 2014-03-26 2015-12-01 種數據處理方法及處理器 HK1211102A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410117556.9A CN104951240B (zh) 2014-03-26 2014-03-26 一种数据处理方法及处理器

Publications (1)

Publication Number Publication Date
HK1211102A1 true HK1211102A1 (zh) 2016-05-13

Family

ID=54165922

Family Applications (1)

Application Number Title Priority Date Filing Date
HK15111785.9A HK1211102A1 (zh) 2014-03-26 2015-12-01 種數據處理方法及處理器

Country Status (8)

Country Link
US (2) US9715450B2 (zh)
EP (2) EP3441886B1 (zh)
JP (2) JP6470300B2 (zh)
KR (1) KR102398912B1 (zh)
CN (2) CN104951240B (zh)
HK (1) HK1211102A1 (zh)
TW (1) TWI638311B (zh)
WO (1) WO2015148679A1 (zh)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150205721A1 (en) * 2014-01-22 2015-07-23 Advanced Micro Devices, Inc. Handling Reads Following Transactional Writes during Transactions in a Computing Device
CN104951240B (zh) 2014-03-26 2018-08-24 阿里巴巴集团控股有限公司 一种数据处理方法及处理器
US10318295B2 (en) * 2015-12-22 2019-06-11 Intel Corporation Transaction end plus commit to persistence instructions, processors, methods, and systems
KR102593362B1 (ko) * 2016-04-27 2023-10-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
GB2551529B (en) 2016-06-21 2018-09-12 Advanced Risc Mach Ltd Switching between private cache and shared memory to handle atomic operations
US10268580B2 (en) * 2016-09-30 2019-04-23 Intel Corporation Processors and methods for managing cache tiering with gather-scatter vector semantics
US10528471B2 (en) * 2016-12-27 2020-01-07 Eta Scale Ab System and method for self-invalidation, self-downgrade cachecoherence protocols
US11119923B2 (en) * 2017-02-23 2021-09-14 Advanced Micro Devices, Inc. Locality-aware and sharing-aware cache coherence for collections of processors
CN111066007B (zh) * 2017-07-07 2023-10-31 美光科技公司 对受到管理的nand的rpmb改进
CN109614220B (zh) * 2018-10-26 2020-06-30 阿里巴巴集团控股有限公司 一种多核系统处理器和数据更新方法
CN109684237B (zh) * 2018-11-20 2021-06-01 华为技术有限公司 基于多核处理器的数据访问方法和装置
CN109784930B (zh) * 2019-02-18 2023-07-18 深圳市迅雷网络技术有限公司 一种区块链交易数据的处理方法、装置、电子设备及介质
CN110265029A (zh) * 2019-06-21 2019-09-20 百度在线网络技术（北京）有限公司 语音芯片和电子设备
CN112307067B (zh) * 2020-11-06 2024-04-19 支付宝(杭州)信息技术有限公司 一种数据处理方法及装置
US11429910B1 (en) 2021-08-05 2022-08-30 Transit Labs Inc. Dynamic scheduling of driver breaks in a ride-sharing service
CN114356949A (zh) * 2022-01-11 2022-04-15 政采云有限公司 一种保持缓存数据一致性的方法、装置及介质

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH061463B2 (ja) * 1990-01-16 1994-01-05 インターナショナル・ビジネス・マシーンズ・コーポレーション マルチプロセッサ・システムおよびそのプライベート・キャッシュ制御方法
US5428761A (en) * 1992-03-12 1995-06-27 Digital Equipment Corporation System for achieving atomic non-sequential multi-word operations in shared memory
DE4331178A1 (de) * 1993-09-14 1995-03-16 Hoechst Schering Agrevo Gmbh Substituierte Pyridine und Pyrimidine, Verfahren zu ihrer Herstellung und ihre Verwendung als Schädlingsbekämpfungsmittel und Fungizide
US6192451B1 (en) * 1998-02-17 2001-02-20 International Business Machines Corporation Cache coherency protocol for a data processing system including a multi-level memory hierarchy
US6434672B1 (en) * 2000-02-29 2002-08-13 Hewlett-Packard Company Methods and apparatus for improving system performance with a shared cache memory
US6868485B1 (en) * 2002-09-27 2005-03-15 Advanced Micro Devices, Inc. Computer system with integrated directory and processor cache
US9727468B2 (en) * 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
US7237070B2 (en) * 2005-04-19 2007-06-26 International Business Machines Corporation Cache memory, processing unit, data processing system and method for assuming a selected invalid coherency state based upon a request source
US10031848B2 (en) * 2005-06-14 2018-07-24 Intel Corporation Method and apparatus for improving snooping performance in a multi-core multi-processor
US8407432B2 (en) * 2005-06-30 2013-03-26 Intel Corporation Cache coherency sequencing implementation and adaptive LLC access priority control for CMP
US20070143550A1 (en) * 2005-12-19 2007-06-21 Intel Corporation Per-set relaxation of cache inclusion
US7590805B2 (en) * 2005-12-29 2009-09-15 Intel Corporation Monitor implementation in a multicore processor with inclusive LLC
US8683143B2 (en) * 2005-12-30 2014-03-25 Intel Corporation Unbounded transactional memory systems
US8924653B2 (en) 2006-10-31 2014-12-30 Hewlett-Packard Development Company, L.P. Transactional cache memory system
US20090138890A1 (en) * 2007-11-21 2009-05-28 Arm Limited Contention management for a hardware transactional memory
US8051248B2 (en) 2008-05-05 2011-11-01 Globalfoundries Inc. Transient transactional cache
US8627017B2 (en) 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
US8799582B2 (en) * 2008-12-30 2014-08-05 Intel Corporation Extending cache coherency protocols to support locally buffered data
US8782347B2 (en) * 2009-06-26 2014-07-15 Intel Corporation Controllably exiting an unknown state of a cache coherency directory
US8229907B2 (en) * 2009-06-30 2012-07-24 Microsoft Corporation Hardware accelerated transactional memory system with open nested transactions
US8301849B2 (en) * 2009-12-23 2012-10-30 Intel Corporation Transactional memory in out-of-order processors with XABORT having immediate argument
US9274962B2 (en) * 2010-12-07 2016-03-01 Intel Corporation Apparatus, method, and system for instantaneous cache state recovery from speculative abort/commit
US9477600B2 (en) * 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
US8984228B2 (en) * 2011-12-13 2015-03-17 Intel Corporation Providing common caching agent for core and integrated input/output (IO) module
US9274960B2 (en) * 2012-03-20 2016-03-01 Stefanos Kaxiras System and method for simplifying cache coherence using multiple write policies
US20140075124A1 (en) 2012-09-07 2014-03-13 International Business Machines Corporation Selective Delaying of Write Requests in Hardware Transactional Memory Systems
CN104951240B (zh) 2014-03-26 2018-08-24 阿里巴巴集团控股有限公司 一种数据处理方法及处理器

Also Published As

Publication number Publication date
EP3123351A1 (en) 2017-02-01
CN109240945B (zh) 2023-06-06
JP6685437B2 (ja) 2020-04-22
US9715450B2 (en) 2017-07-25
EP3441886A1 (en) 2019-02-13
EP3441886B1 (en) 2020-11-18
EP3123351B1 (en) 2018-12-12
JP2017509985A (ja) 2017-04-06
WO2015148679A1 (en) 2015-10-01
CN104951240A (zh) 2015-09-30
EP3123351A4 (en) 2017-10-25
JP2019083045A (ja) 2019-05-30
CN109240945A (zh) 2019-01-18
US20150278094A1 (en) 2015-10-01
TWI638311B (zh) 2018-10-11
US20170277635A1 (en) 2017-09-28
KR102398912B1 (ko) 2022-05-17
KR20160138025A (ko) 2016-12-02
US9858186B2 (en) 2018-01-02
TW201537454A (zh) 2015-10-01
CN104951240B (zh) 2018-08-24
JP6470300B2 (ja) 2019-02-13

Similar Documents

Publication Publication Date Title
ZA201800870B (en) Data processing method and device
HK1211354A1 (zh) 種數據處理方法和裝置
HK1211095A1 (zh) 大數據處理方法及平台
HK1211102A1 (zh) 種數據處理方法及處理器
EP3188081A4 (en) Data processing method and device
HK1207710A1 (zh) 種數據搜索處理方法及裝置
EP2991268A4 (en) METHOD AND DEVICE FOR DATA PROCESSING
EP3110010A4 (en) Data processing device and data processing method
HK1211104A1 (zh) 數據搜索處理方法和系統
EP3148090A4 (en) Data processing device and data processing method
EP3094124A4 (en) Data processing method and device
PL3376389T3 (pl) Sposób i urządzenie do przetwarzania danych
EP2988230A4 (en) DATA PROCESSING METHOD AND COMPUTER SYSTEM
HK1199992A1 (zh) 信息處理方法及裝置
EP2937782A4 (en) METHOD AND DEVICE FOR DATA PROCESSING
EP3082303A4 (en) METHOD AND DEVICE FOR DATA PROCESSING
EP3196776A4 (en) Method and device for data processing
EP3101555A4 (en) Data processing method and device
EP3151242A4 (en) Information processor and information processing method
TWI563837B (en) Data processing method and device
EP3096527A4 (en) Data processing device and data processing method
SG10201404660WA (en) Information processing apparatus and information processing program
GB201414750D0 (en) Data processing apparatus and method
HK1211098A1 (zh) 種數據處理的方法及裝置
HK1221311A1 (zh) 種業務數據處理方法及設備

Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20240325