HK1127414A1 - Multi-processor systems and methods of thread-level parallel processing - Google Patents

Multi-processor systems and methods of thread-level parallel processing

Info

Publication number
HK1127414A1
HK1127414A1 HK09105041.9A HK09105041A HK1127414A1 HK 1127414 A1 HK1127414 A1 HK 1127414A1 HK 09105041 A HK09105041 A HK 09105041A HK 1127414 A1 HK1127414 A1 HK 1127414A1
Authority
HK
Hong Kong
Prior art keywords
processors
thread
parallel processing
methods
level parallel
Prior art date
Application number
HK09105041.9A
Other languages
English (en)
Inventor
Russell H Fish Iii
Original Assignee
Russell H Fish Iii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Russell H Fish Iii filed Critical Russell H Fish Iii
Publication of HK1127414A1 publication Critical patent/HK1127414A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138—Extension of register space, e.g. register cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
HK09105041.9A 2006-02-03 2009-06-04 Multi-processor systems and methods of thread-level parallel processing HK1127414A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US76495506P 2006-02-03 2006-02-03
PCT/US2007/003313 WO2007092528A2 (en) 2006-02-03 2007-02-05 Thread optimized multiprocessor architecture

Publications (1)

Publication Number Publication Date
HK1127414A1 true HK1127414A1 (en) 2009-09-25

Family

ID=38345789

Family Applications (1)

Application Number Title Priority Date Filing Date
HK09105041.9A HK1127414A1 (en) 2006-02-03 2009-06-04 Multi-processor systems and methods of thread-level parallel processing

Country Status (11)

Country Link
US (1) US8977836B2 (zh)
EP (2) EP2154607A3 (zh)
JP (1) JP4987882B2 (zh)
KR (1) KR101120398B1 (zh)
CN (1) CN101395578B (zh)
AT (1) ATE536585T1 (zh)
AU (1) AU2007212342B2 (zh)
CA (1) CA2642022A1 (zh)
HK (1) HK1127414A1 (zh)
RU (1) RU2427895C2 (zh)
WO (1) WO2007092528A2 (zh)

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US8984256B2 (en) 2006-02-03 2015-03-17 Russell Fish Thread optimized multiprocessor architecture
AU2007212342B2 (en) * 2006-02-03 2011-05-12 Russell H. Fish Iii Thread optimized multiprocessor architecture
US7962553B2 (en) * 2006-07-31 2011-06-14 Hewlett-Packard Development Company, L.P. Method and system for distribution of maintenance tasks in a multiprocessor computer system
US8755515B1 (en) 2008-09-29 2014-06-17 Wai Wu Parallel signal processing system and method
US8458439B2 (en) * 2008-12-16 2013-06-04 International Business Machines Corporation Block driven computation using a caching policy specified in an operand data structure
US8281106B2 (en) * 2008-12-16 2012-10-02 International Business Machines Corporation Specifying an addressing relationship in an operand data structure
US8407680B2 (en) * 2008-12-16 2013-03-26 International Business Machines Corporation Operand data structure for block computation
US8285971B2 (en) * 2008-12-16 2012-10-09 International Business Machines Corporation Block driven computation with an address generation accelerator
US8327345B2 (en) * 2008-12-16 2012-12-04 International Business Machines Corporation Computation table for block computation
WO2010092483A1 (en) * 2009-02-13 2010-08-19 Alexey Raevsky Devices and methods for optimizing data-parallel processing in multi-core computing systems
JP5367416B2 (ja) * 2009-03-04 2013-12-11 光洋サーモシステム株式会社 搬送ロボット装置
US9535876B2 (en) * 2009-06-04 2017-01-03 Micron Technology, Inc. Conditional operation in an internal processor of a memory device
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US9823928B2 (en) * 2011-09-30 2017-11-21 Qualcomm Incorporated FIFO load instruction
KR101984635B1 (ko) 2012-07-19 2019-05-31 삼성전자주식회사 어플리케이션을 고속으로 처리하는 연산 처리 장치 및 방법
JP6099329B2 (ja) * 2012-08-02 2017-03-22 シャープ株式会社 端末、基地局、通信方法および集積回路
US9760511B2 (en) * 2014-10-08 2017-09-12 International Business Machines Corporation Efficient interruption routing for a multithreaded processor
WO2016099318A2 (ru) * 2014-12-19 2016-06-23 Сергей Анатольевич ГОРИШНИЙ Система и способ управления функционально связанными данными
RU2612569C2 (ru) * 2015-01-27 2017-03-09 Акционерное общество "Научно-исследовательский институт Авиационного оборудования" Способ автоматического управления избыточностью неоднородной вычислительной системы и устройство для его реализации
CN104699449B (zh) * 2015-04-03 2017-09-29 中国科学院软件研究所 一种基于gmp的大整数加法和减法多核并行化实现方法
CN111104062B (zh) * 2019-11-22 2023-05-02 中科寒武纪科技股份有限公司 存储管理方法、装置和存储介质

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Also Published As

Publication number Publication date
EP1979808B1 (en) 2011-12-07
WO2007092528A9 (en) 2009-05-14
JP2009525545A (ja) 2009-07-09
EP2154607A3 (en) 2010-07-14
US8977836B2 (en) 2015-03-10
CN101395578B (zh) 2013-01-09
RU2008135666A (ru) 2010-03-10
EP1979808A2 (en) 2008-10-15
US20070192568A1 (en) 2007-08-16
EP2154607A2 (en) 2010-02-17
ATE536585T1 (de) 2011-12-15
CN101395578A (zh) 2009-03-25
KR20080109743A (ko) 2008-12-17
AU2007212342B2 (en) 2011-05-12
CA2642022A1 (en) 2007-08-16
AU2007212342A1 (en) 2007-08-16
KR101120398B1 (ko) 2012-02-24
WO2007092528A3 (en) 2008-08-28
JP4987882B2 (ja) 2012-07-25
EP1979808A4 (en) 2009-04-08
WO2007092528A2 (en) 2007-08-16
RU2427895C2 (ru) 2011-08-27

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)

Effective date: 20170205